not working rs

rs232_tx.v

@@ -18,14 +18,14 @@
 // Additional Comments: 
 //
 //////////////////////////////////////////////////////////////////////////////////
-module rs232_tx( CLK_TX, RST, TX, DATA, TRG, DONE
+module rs232_tx( CLK_TX, RST, TX, DATA, WR_EN, DONE
     );
-
+	 
 input CLK_TX;
 input RST;
 output reg TX;
 input [7:0]DATA;
-input TRG;
+input WR_EN;
 output reg DONE;
 
 // --------------------
@@ -55,7 +55,7 @@ always @* begin
 							next = WAITING_TRG;
 		end
 		WAITING_TRG: begin 
-			if( TRG )	next = SEND_START;
+			if( WR_EN )	next = SEND_START;
 			else			next = WAITING_TRG;
 		end
 		SEND_START: begin
@@ -100,7 +100,7 @@ always @(posedge CLK_TX) begin
 	endcase
 end
 
-//always @(posedge TRG) begin
+//always @(posedge WR_EN) begin
 //	writing <= 8;
 //	data <= DATA;
 //end

rs232_tx_sim.v

@@ -26,21 +26,21 @@ wire TX;
 reg RST;
 reg [7:0]DATA = 8'b11010010;
 wire DONE;
-reg TRG;
+reg WR_EN;
 
-rs232_tx tx( .CLK_TX(CLK), .RST(RST), .TX(TX), .DATA(DATA), .TRG(TRG), .DONE(DONE) );
+rs232_tx tx( .CLK_TX(CLK), .RST(RST), .TX(TX), .DATA(DATA), .WR_EN(WR_EN), .DONE(DONE) );
 
 initial begin
 	RST = 0;
-	TRG = 0;
+	WR_EN = 0;
 	CLK = 0;
 	#30;
 	RST = 1;
 	#30;
 	RST = 0;
 	#30;
-	TRG = 1;
-	@(posedge DONE) TRG = 0;
+	WR_EN = 1;
+	@(posedge DONE) WR_EN = 0;
 end
 
 

serial_tx_fifo.v

@@ -34,16 +34,23 @@ SERIAL_TX uart_tx
           (.CLK_TX(CLK_TX),.RST(RST),.SEND(tx_send),
            .TX(TX),.DONE(tx_done),.DATA(DATA_OUT));
 
+//rs232_tx uart_tx
+//          (.CLK_TX(CLK_TX),.RST(RST),.WR_EN(tx_send),
+//           .TX(TX),.DONE(tx_done),.DATA(DATA_OUT));
+
 always @(posedge CLK_WR)
 if(~RST) wr_cnt<=0;
 else
  if(WR_EN) wr_cnt<=wr_cnt+1;
 
+
 always @(posedge CLK_WR)
  if (WR_EN) FIFO[wr_cnt]<=DATA;
 
+
 assign DATA_OUT=FIFO[rd_cnt];								
-
+
+
 always @(posedge CLK_WR) //(1)
  if(~RST) st<=0;
  else