xor2 generates or2 in VHDL #2

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metanest opened this Issue Dec 5, 2011 · 1 comment

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metanest commented Dec 5, 2011

folloing is patch

diff --git a/Language/KansasLava/Utils.hs b/Language/KansasLava/Utils.hs
index 47901a5..76a9409 100644
--- a/Language/KansasLava/Utils.hs
+++ b/Language/KansasLava/Utils.hs
@@ -61,7 +61,7 @@ or2 s1 s2 = primXS2 (\ a b -> case (unX a,unX b) of
 xor2 :: ( sig ~ Signal i) => sig Bool -> sig Bool -> sig Bool
 xor2 s1 s2 = primXS2 (\ a b -> case (unX a,unX b) of
         (Just a',Just b') -> optX $ Just (a' /= b')
-             _                 -> optX $ Nothing ) "or2"
+             _                 -> optX $ Nothing ) "xor2"
          s1
          s2

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metanest Jan 18, 2013

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This have fixed ( by Pull Request #5 ). I close.

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metanest commented Jan 18, 2013

This have fixed ( by Pull Request #5 ). I close.

@metanest metanest closed this Jan 18, 2013

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