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imx233: fix clkctrl code (some registers don't have a SET/CLR variant)

Change-Id: I3ce6a77cdc5ea89e1e43bc00c9ec43664e765fdc
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commit eaa83bd64775b87e943d345e2810deed44408776 1 parent 6b7db7e
@pamaury pamaury authored
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17 firmware/target/arm/imx233/clkctrl-imx233.c
@@ -76,16 +76,17 @@ bool imx233_is_clock_enable(enum imx233_clock_t clk)
void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
{
+ /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
switch(clk)
{
case CLK_PIX:
- __REG_CLR(HW_CLKCTRL_PIX) = HW_CLKCTRL_PIX__DIV_BM;
- __REG_SET(HW_CLKCTRL_PIX) = div;
+ HW_CLKCTRL_PIX &= ~HW_CLKCTRL_PIX__DIV_BM;
+ HW_CLKCTRL_PIX |= div;
while(HW_CLKCTRL_PIX & __CLK_BUSY);
break;
case CLK_SSP:
- __REG_CLR(HW_CLKCTRL_SSP) = HW_CLKCTRL_SSP__DIV_BM;
- __REG_SET(HW_CLKCTRL_SSP) = div;
+ HW_CLKCTRL_SSP &= ~HW_CLKCTRL_SSP__DIV_BM;
+ HW_CLKCTRL_SSP |= div;
while(HW_CLKCTRL_SSP & __CLK_BUSY);
break;
case CLK_CPU:
@@ -94,8 +95,8 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
while(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__BUSY_REF_CPU);
break;
case CLK_EMI:
- __REG_CLR(HW_CLKCTRL_EMI) = HW_CLKCTRL_EMI__DIV_EMI_BM;
- __REG_SET(HW_CLKCTRL_EMI) = div;
+ HW_CLKCTRL_EMI &= ~HW_CLKCTRL_EMI__DIV_EMI_BM;
+ HW_CLKCTRL_EMI |= div;
while(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__BUSY_REF_EMI);
break;
case CLK_HBUS:
@@ -104,8 +105,8 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
while(HW_CLKCTRL_HBUS & __CLK_BUSY);
break;
case CLK_XBUS:
- __REG_CLR(HW_CLKCTRL_XBUS) = HW_CLKCTRL_XBUS__DIV_BM;
- __REG_SET(HW_CLKCTRL_XBUS) = div;
+ HW_CLKCTRL_XBUS &= ~HW_CLKCTRL_XBUS__DIV_BM;
+ HW_CLKCTRL_XBUS |= div;
while(HW_CLKCTRL_XBUS & __CLK_BUSY);
break;
default: return;
View
5 firmware/target/arm/imx233/clkctrl-imx233.h
@@ -52,6 +52,7 @@
#define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16)
#define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20)
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
#define HW_CLKCTRL_XBUS__DIV_BP 0
#define HW_CLKCTRL_XBUS__DIV_BM 0x3ff
@@ -62,14 +63,17 @@
#define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28)
#define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30)
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
#define HW_CLKCTRL_PIX__DIV_BP 0
#define HW_CLKCTRL_PIX__DIV_BM 0xfff
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
#define HW_CLKCTRL_SSP__DIV_BP 0
#define HW_CLKCTRL_SSP__DIV_BM 0x1ff
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0))
#define HW_CLKCTRL_EMI__DIV_EMI_BP 0
#define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f
@@ -94,6 +98,7 @@
#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6)
#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7)
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
#define HW_CLKCTRL_RESET_CHIP 0x2
#define HW_CLKCTRL_RESET_DIG 0x1
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