x86/svm: Correctly extract the IP from LBR MSRs

Currently, only bit 63 is ignored when reading LBR MSRs. However,
different AMD CPUs use upper bits of the MSR differently. For example,
some Zen 4 processors document bit 63 in LASTBRACNHFROMIP and bits 63:61
in LASTBRANCHTOIP to be reserved. On the other hand, some Zen 5
processors bits 63:57 to be reserved in both MSRs.

Use the common denominator and always bits 63:57 when reading the LBR
MSRs, which should be sufficient testing. This fixes the test flaking on
some AMD processors that set bit 62 in LASTBRANCHTOIP.

Reported-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev>
Link: https://patch.msgid.link/20251113224639.2916783-1-yosry.ahmed@linux.dev
Signed-off-by: Sean Christopherson <seanjc@google.com>

Author: yosrym93

lib/x86/msr.h

@@ -85,8 +85,12 @@
 #define MSR_IA32_LASTINTFROMIP		0x000001dd
 #define MSR_IA32_LASTINTTOIP		0x000001de
 
-/* Yes, AMD does indeed record mispredict info in the LBR records themselves. */
-#define AMD_LBR_RECORD_MISPREDICT	BIT_ULL(63)
+/*
+ * Different AMD CPUs use the upper bits of the IP LBRs differently. For the
+ * purposes of tests, use the common denominator of the IP bits.
+ */
+#define AMD_LBR_RECORD_IP_BITS		57
+#define AMD_LBR_RECORD_IP_MASK		((1UL << AMD_LBR_RECORD_IP_BITS)-1)
 
 #define LBR_INFO_MISPRED		BIT_ULL(63)
 #define LBR_INFO_IN_TX			BIT_ULL(62)

x86/svm_tests.c

@@ -3008,7 +3008,7 @@ static void svm_no_nm_test(void)
 
 static u64 amd_get_lbr_rip(u32 msr)
 {
-	return rdmsr(msr) & ~AMD_LBR_RECORD_MISPREDICT;
+	return rdmsr(msr) & AMD_LBR_RECORD_IP_MASK;
 }
 
 #define HOST_CHECK_LBR(from_expected, to_expected)					\