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<?xml version="1.0" encoding="UTF-8"?>
<!-- Copyright (c) 2012-2017 The Etnaviv Project
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sub license,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
-->
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>
<!-- Vivante GCxxxx instruction set overview -->
<domain name="VIV_ISA">
<!-- XXX still unsure if rules-ng is a suitable format for ISA descriptions,
I don't really think so, but it will initially help to put notes in a more structured format.
See function assemble() in asm.py and function disassemble() in etnaviv/disasm.py for details on assembling/disassembling
an instruction using the bitfields and instructions defined in this file.
-->
<enum name="INST_OPCODE" brief="Main opcode table">
<!-- Overall the ISA seems to be based on DirectX shader assembly. This is pretty obvious in retrospect
as Vivante started by marketing DirectX-compatible GPUs for playing desktop PC games.
Restrictions:
- only one uniform can be read per instruction, however this single uniform can be used in
multiple arguments.
- when violating this restriction it will be as if the uniform in the last source register
is broadcasted to all arguments that use an uniform.
-->
<doc>
Unused operands of an instruction should have their use flag at 0.
Unless mentioned otherwise, instructions do the same for all four components of the vector-valued
operands.
Operands src0,src1 and src2 can come from a temporary register or an uniform.
Immediate values
-----------------
On GC3000 it is possible to provide immediate values inline for source
arguments for other instructions than control flow instructions.
The encoding is different. How this works is that SRCx_RGROUP is set to
7. Then the immediate value is scattered over several fields of that
source operand. This in total gives 20 bits of integer range for
signed and unsigned values.
The 20-bit value can also be interpreted as floating point, in the following way:
bit
------------------------------------------------------------
|19|18 17 16 15 14 13 12 11|10 9 8 7 6 5 4 3 2 1 0|
+--+-----------------------+-------------------------------+
|s |e e e e e e e e |m m m m m m m m m m m|
------------------------------------------------------------
s Sign bit
e Exponent
m Mantissa
1 sign bit, 8 exponent bits, 11 mantissa bits. Exponent bits appear to be interpreted
the same as for IEEE 754 single precision. A useful observation is that
this is the upper 20 bits of a 32-bit floating point value.
- SRCx_RGROUP is 7
- SRCx_REG contains bit 8..0
- SRCx_SWIZZLE contains bit 16..9
- SRCx_NEG contains bit 17 of i
- SRCx_ABS contains bit 18 of i
- SRCx_AMODE determines type conversion and sign, as well as bit 19 of i:
AMODE | Type| Value
------+-----+---------------------
000 | f32 | i.x
001 | f32 | -i.x
010 | s32 | 0 + i
011 | s32 | -0x80000 + i
100 | u32 | 0 + i (same as 010)
101 | u32 | 0x80000 + i
110 | ? | ?
111 | ? | ?
Immediates values are broadcasted to all lanes of the source argument.
The conversion type does not have to match the instruction type. It is valid
for an instruction to have multiple immediates values, one for each source argument,
of different conversion types. This can be useful for the STORE instruction
to store a fixed value at a fixed offset.
Dual-16 mode
-----------------
Some GPUs support dual-16 mode for the pixel shader. The Vivante driver uses this
when only mediump/lowp precision is used. This changes the execution mode of the
fragment mode to process two 16 bit values at once. The interpretation of instructions
is changed.
Bits 13 and 24 of the third instruction word (SEL_BIT0 and SEL_BIT1) can be used to
make an instruction run on only one half of the threads. This is used for sampling
textures. For example,
void main()
{
gl_FragColor = 3.0 * vVaryingColor * texture2D(in_texture, coord);\n"
}
Gets assembled to
0: texld.s0 t3, tex0, th1.xyyy, void, void
1: texld.s1 t3, tex0, th1.zwww, void, void
2: mul t1, u0.xxxx, t2, void
3: mul t1, t1, t3, void
Full-precision register accesses can be done by using the register group th
instead of t.
There might be other ISA restrictions as well. For example, the blob refuses to
generate immediate values.
</doc>
<value value="0x00" name="NOP" brief="No operation"/>
<value value="0x01" name="ADD" brief="Add">
<doc>
dst := src0 + src2
f32: src0 is added to src2 and the result is put into temporary register dst. This
is a four-wide vector operation.
u32, GC2000: src0.x is added to src2.x and the result is put into the first enabled component
of register dst. This is a scalar operation, the result is broadcasted to multiple components.
u32, GC3000: Every component of src0 is added that of src2 in a SIMD operation.
</doc>
</value>
<value value="0x02" name="MAD" brief="Multiply add">
<doc>
dst := src0 * src1 + src2
src0 is multipied with src1, then src2 is added. The result is put into temporary
register dst.
</doc>
</value>
<value value="0x03" name="MUL" brief="Multiply">
<doc>
dst := src0 * src1
src0 is multipied with src1 and the result is put into temporary register dst.
</doc>
</value>
<value value="0x04" name="DST" brief="Calculates a distance vector">
<doc>
dst.x := 1
dst.y := src0.y * src1.y
dst.z := src0.z
dst.w := src1.w
http://msdn.microsoft.com/en-us/library/windows/desktop/bb219790%28v=vs.85%29.aspx
</doc>
</value>
<value value="0x05" name="DP3" brief="3-component dot product">
<doc>
dst := src0.x * src1.x + src0.y * src1.y + src0.z * src1.z
Computes the component-wise dot product of the first three components between src0 and src1 and
broadcasts the results to all destination components in temporary register dst.
</doc>
</value>
<value value="0x06" name="DP4" brief="4-component dot product">
<doc>
dst := src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src0.w * src1.w
Computes the component-wise dot product between src0 and src1 and broadcasts the results to all destination
components in temporary register dst.
</doc>
</value>
<value value="0x07" name="DSX" brief="Compute derivative relative to X"/>
<value value="0x08" name="DSY" brief="Compute derivative relative to Y"/>
<value value="0x09" name="MOV" brief="Move to temporary register">
<doc>
dst := src2
Copies the value of operand src2 to temporary register dst.
</doc>
</value>
<value value="0x0A" name="MOVAR" brief="Move address to address register"/>
<value value="0x0B" name="MOVAF" brief="Move float to address register">
<doc>
dst := src2
Copies the floating point value of operand src2 to address register dst.
XXX does this round or floor?
</doc>
</value>
<value value="0x0C" name="RCP" brief="Reciprocal">
<doc>
dst := 1.0 / src2
Computes the reciprocal of src2, and puts the result into temporary register dst.
</doc>
</value>
<value value="0x0D" name="RSQ" brief="Reciprocal square root">
<doc>
dst := 1.0 / sqrt(src2)
Computes the reciprocal of the square root of src2, and puts the result into
temporary register dst.
</doc>
</value>
<value value="0x0E" name="LITP" brief="Partial lighting computation">
<doc>
dst.x := 1
dst.y := src1.y IF (src1.z > 0 AND src0.y > 0) else 0
dst.z := exp(src2.x) IF (src1.z > 0 AND src0.z > 0) else 0
dst.w := 1
Partial http://msdn.microsoft.com/en-us/library/windows/desktop/bb174703%28v=vs.85%29.aspx
Note: If src0 is disabled, src0.y > 0 and src0.z > 0 evaluate as true.
</doc>
</value>
<value value="0x0F" name="SELECT" brief="Choose input based on condition">
<doc>
dst := src1 COND src0 ? src2 : src1 (binary condition)
dst := COND(src0) ? src1 : src2 (unary condition)
Sets temporary register dst to src2 if (src1 COND src0) holds, otherwise to src1.
This operation is performed per-component. It is used to implement MIN(a,b) and MAX(a,b)
in the following way:
- MIN(a,b): SELECT.GT dst, a, b, a (b > a ? a : b)
- MAX(a,b): SELECT.LT dst, a, b, a (b &lt; a ? a : b)
</doc>
</value>
<value value="0x10" name="SET">
<doc>
dst := src0 COND src1
Sets temporary register dst to 1.0 if (src0 COND src1), otherwise to 0.0.
</doc>
</value>
<value value="0x11" name="EXP" brief="2^x">
<doc>
dst := exp2(src2.x)
Sets temporary register dst to the 2-exponent of the x component of src2).
This is a scalar operation, the result is broadcasted over all active destination components.
</doc>
</value>
<value value="0x12" name="LOG" brief="log2">
<doc>
dst := log2(src2.x)
Sets temporary register dst to the 2-log of the x component of src2).
This is a scalar operation, the result is broadcasted over all active destination components.
Note: if HAS_FAST_TRANSCENDENTALS feature is enabled, the GPU implements a completely
different instruction:
dst.x * dst.y := log2(src2.x)
- x and y of the result need to be multiplied to get the result of the logarithm
- TEX.AMODE needs to be set to 1
</doc>
</value>
<value value="0x13" name="FRC" brief="Return fractional portion">
<doc>
dst := frc(src2)
Sets temporary register dst to the fractional portion of src2 for positive values. For negative values,
the returned value will be 1.0 - the fractional portion. For example, 1.5 will become 0.5, and -0.1
will be turned into 0.9.
</doc>
</value>
<value value="0x14" name="CALL" brief="Function call"/>
<value value="0x15" name="RET" brief="Return from function"/>
<value value="0x16" name="BRANCH" brief="Jump to address">
<doc>
pc := src2_imm *if src0 COND src1*
Changes the current value of the instruction pointer if (src0 COND src1) evaluates
to true.
</doc>
</value>
<value value="0x17" name="TEXKILL" brief="Cancels rendering of the current fragment">
<doc>
Discards (kills) the current fragment. Can only be used in PS.
Kill fragment if src0 *COND* src1.
</doc>
</value>
<value value="0x18" name="TEXLD" brief="Texture load">
<doc>
dst := textureND(tex, src0)
Samples texture coordinate src0 with sampler tex, and returns the sampled color in temporary register dst.
</doc>
</value>
<value value="0x19" name="TEXLDB" brief="Texture load (biased)"/>
<value value="0x1A" name="TEXLDD" brief="Texture load (manually specified gradients)"/>
<value value="0x1B" name="TEXLDL" brief="Texture load (at particular LOD)"/>
<value value="0x1C" name="TEXLDPCF" brief="Texture load"/>
<value value="0x1D" name="REP" brief="Begins a REPEAT block"/>
<value value="0x1E" name="ENDREP" brief="Ends a REPEAT block"/>
<value value="0x1F" name="LOOP" brief="Begins a LOOP block"/>
<value value="0x20" name="ENDLOOP" brief="Ends a LOOP block"/>
<value value="0x21" name="SQRT" brief="Square root"> <!-- HAS_SQRT_TRIG -->
<doc>
dst := sqrt(src2)
Computes the square root of src2 and puts the result in temporary register dst.
</doc>
</value>
<value value="0x22" name="SIN" brief="Sine"> <!-- HAS_SQRT_TRIG -->
<doc>
dst := sin(src2 * (PI/2))
Computes the sine of src2 and puts the result in temporary register dst.
The period of the sine is 4 and not 2 PI, thus to get normal behavior the instruction
should be prefixed by a division by PI/2.
Note: on GC2000 the src register cannot be the same as dst. This limitation does not
appear to exist on GC3000.
Note: if HAS_FAST_TRANSCENDENTALS feature is enabled, the GPU implements a completely
different instruction:
dst.x * dst.y := sin(src2 * PI)
- The period of the sine is 2 instead of 4
- x and y of the result need to be multiplied to get the result of the sine
- TEX.AMODE needs to be set to 1
</doc>
</value>
<value value="0x23" name="COS" brief="Cosine"> <!-- HAS_SQRT_TRIG -->
<doc>
dst := cos(src2 * (PI/2))
Computes the cosine of src2 and puts the result in temporary register dst.
The period of the cosine is 4 and not 2 PI, thus to get normal behavior the instruction
should be prefixed by a division by PI/2.
Note: on GC2000 the src register cannot be the same as dst. This limitation does not
appear to exist on GC3000.
Note: if HAS_FAST_TRANSCENDENTALS feature is enabled, the GPU implements a completely
different instruction:
dst.x * dst.y := cos(src2 * PI)
- The period of the sine is 2 instead of 4
- x and y of the result need to be multiplied to get the result of the cosine
- TEX.AMODE needs to be set to 1
</doc>
</value>
<value value="0x25" name="FLOOR" brief="Largest integral value not greater than the argument"> <!-- HAS_SIGN_FLOOR_CEIL -->
<doc>
dst := floor(src2)
Computes the largest integral value not greater than the argument, and puts the result in temporary
register dst.
</doc>
</value>
<value value="0x26" name="CEIL" brief="Smallest integral value not less than the argument"> <!-- HAS_SIGN_FLOOR_CEIL -->
<doc>
dst := ceil(src2)
Computes the smallest integral value not less than the argument, and puts the result in temporary
register dst.
</doc>
</value>
<value value="0x27" name="SIGN" brief="Return sign of the argument"> <!-- HAS_SIGN_FLOOR_CEIL -->
<doc>
dst := sign(src2)
Return 1.0 if the sign is positive or zero, -1.0 if negative.
</doc>
</value>
<!-- OpenCL (GC2000+) -->
<value value="0x28" name="ADDLO"/> <!-- unverified -->
<value value="0x29" name="MULLO"/> <!-- unverified -->
<value value="0x2A" name="BARRIER"/> <!-- unverified -->
<value value="0x2B" name="SWIZZLE"/> <!-- unverified -->
<value value="0x2C" name="I2I"/> <!-- unverified -->
<value value="0x2D" name="I2F" brief="Integer to float">
<doc>
dst := float(src0.x)
Convert source operand to a float and put the result in temporary register dst.
The type of the instruction (at least s32/u32) is taken into account.
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x2E" name="F2I" brief="Float to integer">
<doc>
dst := int(src0.x)
Truncate source operand and convert to an integer and put the result in temporary register dst.
The type of the instruction (at least s32/u32) is taken into account.
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x2F" name="F2IRND"/> <!-- unverified -->
<value value="0x30" name="F2I7"/> <!-- unverified -->
<value value="0x31" name="CMP" brief="Integer compare"/>
<value value="0x32" name="LOAD" brief="Memory load">
<doc>
dst := mem[src0.x+src1.x]
Load dst from address src0.x + src1.x.
The size of the load operation is determined by:
- The INST_TYPE of this instruction
- DST.COMPS: .x loads only one value, .xy two values, .xyz three values, .xyzw four values.
Other combination may be possible but this has not been verified.
This is a scalar operation, the result is broadcasted over all active destination components.
</doc>
</value>
<value value="0x33" name="STORE" brief="Memory store">
<doc>
mem[src0.x+src1.x] := src2.x
Store at src2.x at address src0.x + src1.x.
The size of the store operation is determined by:
- The INST_TYPE of this instruction
- DST.COMPS: .x stores only one value, .xy two values, .xyz three values, .xyzw four values
Other combination may be possible but this has not been verified.
It looks like DST.REG is set to 4 in some cases when __local memory is used,
this must be some kind of synchronization flag.
This is a scalar operation, the result is broadcasted over all active destination components.
</doc>
</value>
<value value="0x34" name="COPYSIGN"/> <!-- unverified -->
<value value="0x35" name="GETEXP"/> <!-- unverified -->
<value value="0x36" name="GETMANT"/> <!-- unverified -->
<value value="0x37" name="NAN"/> <!-- unverified -->
<value value="0x38" name="NEXTAFTER"/> <!-- unverified -->
<value value="0x39" name="ROUNDEVEN"/> <!-- unverified -->
<value value="0x3A" name="ROUNDAWAY"/> <!-- unverified -->
<value value="0x3B" name="IADDSAT"/> <!-- unverified -->
<value value="0x3C" name="IMULLO0" brief="Integer multiply">
<doc>
dst := src0.x * src1.x
This is a scalar operation, the result is broadcasted over all active destination components.
</doc>
</value>
<value value="0x3D" name="IMULLO1"/> <!-- unverified -->
<value value="0x3E" name="IMULLOSAT0"/> <!-- unverified -->
<value value="0x3F" name="IMULLOSAT1"/> <!-- unverified -->
<value value="0x40" name="IMULHI0" brief="High half of the product of x and y">
<doc>
dst := (src0.x * src1.x) >> 32
A 64-bit multiplication between src0.x and src1.x is performed and the upper 32 bits of the
result are returned. Matches the mul_hi intrinsic in OpenCL.
This is a scalar operation, the result is broadcasted over all active destination components.
</doc>
</value>
<value value="0x41" name="IMULHI1"/> <!-- unverified -->
<value value="0x42" name="IMUL0"/> <!-- unverified -->
<value value="0x43" name="IMUL1"/> <!-- unverified -->
<value value="0x44" name="IDIV0"/> <!-- unverified -->
<value value="0x45" name="IDIV1"/> <!-- unverified -->
<value value="0x46" name="IDIV2"/> <!-- unverified -->
<value value="0x47" name="IDIV3"/> <!-- unverified -->
<value value="0x48" name="IMOD0"/> <!-- unverified -->
<value value="0x49" name="IMOD1"/> <!-- unverified -->
<value value="0x4A" name="IMOD2"/> <!-- unverified -->
<value value="0x4B" name="IMOD3"/> <!-- unverified -->
<value value="0x4C" name="IMADLO0" brief="Integer multiply and add">
<doc>
dst := src0.x * src1.x + src2.x
This is a scalar operation, the result is broadcasted over all active destination components.
</doc>
</value>
<value value="0x4D" name="IMADLO1"/> <!-- unverified -->
<value value="0x4E" name="IMADLOSAT0"/> <!-- unverified -->
<value value="0x4F" name="IMADLOSAT1"/> <!-- unverified -->
<value value="0x50" name="IMADHI0"/> <!-- unverified -->
<value value="0x51" name="IMADHI1"/> <!-- unverified -->
<value value="0x52" name="IMADHISAT0"/> <!-- unverified -->
<value value="0x53" name="IMADHISAT1"/> <!-- unverified -->
<value value="0x54" name="HALFADD"/> <!-- unverified -->
<value value="0x55" name="HALFADDINC"/> <!-- unverified -->
<value value="0x56" name="MOVAI"/> <!-- unverified -->
<value value="0x57" name="IABS"/> <!-- unverified -->
<value value="0x58" name="LEADZERO" brief="Count leading zeros">
<doc>
dst := clz(src0.x)
Returns the number of leading 0-bits in src.x, starting at the most significant bit position.
If the input argument is 0, 32 iz returned. Matches the clz intrinsic in OpenCL.
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x59" name="LSHIFT" brief="Bitwise left shift">
<doc>
dst := src0.x &lt;&lt; (src2.x &amp; 31)
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately. This means that
potentially different shifts can be applied to every component.
</doc>
</value>
<value value="0x5A" name="RSHIFT" brief="Bitwise right shift">
<doc>
dst := src0.x &gt;&gt; (src2.x &amp; 31)
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately. This means that
potentially different shifts can be applied to every component.
</doc>
</value>
<value value="0x5B" name="ROTATE" brief="Bitwise rotate left">
<doc>
dst := (src0.x &lt;&lt; (src2.x &amp; 31)) | (src0.x &gt;&gt; ((32-src2.x) &amp; 31))
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately. This means that
potentially different shifts can be applied to every component.
</doc>
</value>
<value value="0x5C" name="OR" brief="Bitwise or">
<doc>
dst := src0.x | src2.x
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x5D" name="AND" brief="Bitwise and">
<doc>
dst := src0.x &amp; src2.x
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x5E" name="XOR" brief="Bitwise exclusive or">
<doc>
dst := src0.x ^ src2.x
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x5F" name="NOT" brief="Bitwise not">
<doc>
dst := ~src2.x
Before GC3000 this is a scalar operation, the result is broadcasted over all active destination components.
On GC3000 this is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x60" name="BITSELECT"/> <!-- unverified -->
<value value="0x61" name="POPCOUNT" brief="Population count">
<doc>
dst := popcount(src2)
Count the number of '1' bits in the source operand.
As the urban myth goes, this instruction is a favorite of the NSA.
Only exists on GC3000+.
This is a SIMD operation, with the operation applied to each component separately.
</doc>
</value>
<value value="0x62" name="STOREB"/> <!-- unverified -->
<value value="0x63" name="RGB2YUV"/> <!-- unverified -->
<value value="0x64" name="DIV"> <!-- HAS_FAST_TRANSCENDENTALS -->
<doc>
dst.x * dst.y := src1.x / src2.x
Computes the result of a floating point division between src1.x and
src2.x. This is supposed to have a higher precision than
conventional RCP followed by MUL.
- x and y of the result need to be multiplied to get the result
- TEX.AMODE needs to be set to 1
</doc>
</value>
<value value="0x65" name="ATOM_ADD"/> <!-- unverified -->
<value value="0x66" name="ATOM_XCHG"/> <!-- unverified -->
<value value="0x67" name="ATOM_CMP_XCHG"/> <!-- unverified -->
<value value="0x68" name="ATOM_MIN"/> <!-- unverified -->
<value value="0x69" name="ATOM_MAX"/> <!-- unverified -->
<value value="0x6A" name="ATOM_OR"/> <!-- unverified -->
<value value="0x6B" name="ATOM_AND"/> <!-- unverified -->
<value value="0x6C" name="ATOM_XOR"/> <!-- unverified -->
<value value="0x6D" name="BIT_REV"/> <!-- unverified -->
<value value="0x6E" name="BYTE_REV"/> <!-- unverified -->
<value value="0x6F" name="TEXLDLPCF"/> <!-- unverified -->
<value value="0x70" name="TEXLDGPCF"/> <!-- unverified -->
<value value="0x71" name="PACK"/> <!-- unverified -->
<value value="0x72" name="CONV"/> <!-- unverified -->
<value value="0x73" name="DP2"> <!-- HALTI2 -->
<doc>
dst := src0.x * src1.x + src0.y * src1.y
Computes the component-wise floating point dot product of the first
two components between src0 and src1 and broadcasts the results to
all destination components in register dst.
</doc>
</value>
<value value="0x74" name="NORM_DP2"/> <!-- unverified -->
<value value="0x75" name="NORM_DP3"/> <!-- unverified -->
<value value="0x76" name="NORM_DP4"/> <!-- unverified -->
<value value="0x77" name="NORM_MUL"/> <!-- unverified -->
<value value="0x78" name="STORE_ATTR"/> <!-- unverified -->
<value value="0x79" name="LOAD_ATTR"/> <!-- unverified -->
<value value="0x7A" name="EMIT"/> <!-- unverified -->
<value value="0x7B" name="RESTART"/> <!-- unverified -->
<value value="0x7C" name="NOP7C"/> <!-- unverified -->
<value value="0x7D" name="NOP7D"/> <!-- unverified -->
<value value="0x7E" name="NOP7E"/> <!-- unverified -->
<value value="0x7F" name="NOP7F"/> <!-- unverified -->
</enum>
<enum name="INST_CONDITION" brief="Condition code">
<value value="0x00" name="TRUE"/>
<value value="0x01" name="GT"/>
<value value="0x02" name="LT"/>
<value value="0x03" name="GE"/>
<value value="0x04" name="LE"/>
<value value="0x05" name="EQ"/>
<value value="0x06" name="NE"/>
<value value="0x07" name="AND"/>
<value value="0x08" name="OR"/>
<value value="0x09" name="XOR"/>
<value value="0x0A" name="NOT"/>
<value value="0x0B" name="NZ"/>
<value value="0x0C" name="GEZ"/>
<value value="0x0D" name="GZ"/>
<value value="0x0E" name="LEZ"/>
<value value="0x0F" name="LZ"/>
</enum>
<bitset name="INST_COMPS" brief="Vector components">
<bitfield pos="0" name="X" brief="Component 0"/>
<bitfield pos="1" name="Y" brief="Component 1"/>
<bitfield pos="2" name="Z" brief="Component 2"/>
<bitfield pos="3" name="W" brief="Component 3"/>
</bitset>
<enum name="INST_RGROUP" brief="Register group">
<value value="0" name="TEMP" brief="Temporary"/>
<value value="1" name="INTERNAL" brief="Derived values">
Only one register in this range is known:
- 0.x: gl_FrontFacing (PS)
</value>
<value value="2" name="UNIFORM_0" brief="Uniforms 0..127"/>
<value value="3" name="UNIFORM_1" brief="Uniforms 128..255"/>
<!-- 4..7 alias 0..3 -->
</enum>
<enum name="INST_AMODE" brief="Addressing mode">
<value value="0" name="DIRECT"/>
<value value="1" name="ADD_A_X" brief="Add a.x to the sampler or register index"/>
<value value="2" name="ADD_A_Y" brief="Add a.y to the sampler or register index"/>
<value value="3" name="ADD_A_Z" brief="Add a.z to the sampler or register index"/>
<value value="4" name="ADD_A_W" brief="Add a.w to the sampler or register index"/>
</enum>
<enum name="INST_SWIZ_COMP" brief="Swizzle source component">
<value value="0" name="X" brief="Component 0"/>
<value value="1" name="Y" brief="Component 1"/>
<value value="2" name="Z" brief="Component 2"/>
<value value="3" name="W" brief="Component 3"/>
</enum>
<bitset name="INST_SWIZ" brief="Swizzling mode">
<bitfield high="1" low="0" name="X" type="INST_SWIZ_COMP" brief="Source for component 0"/>
<bitfield high="3" low="2" name="Y" type="INST_SWIZ_COMP" brief="Source for component 1"/>
<bitfield high="5" low="4" name="Z" type="INST_SWIZ_COMP" brief="Source for component 2"/>
<bitfield high="7" low="6" name="W" type="INST_SWIZ_COMP" brief="Source for component 3"/>
</bitset>
<enum name="INST_TYPE" brief="Instruction operand type">
<!--
Some instructions accept a type operand (gc2000+):
1_21 2_31 2_30
===============
-->
<value value="0" name="F32"/><!-- 0 0 0 (default) -->
<value value="1" name="S32"/><!-- 0 0 1 -->
<value value="2" name="S8"/> <!-- 0 1 0 -->
<value value="3" name="U16"/><!-- 0 1 1 -->
<value value="4" name="F16"/><!-- 1 0 0 -->
<value value="5" name="S16"/><!-- 1 0 1 -->
<value value="6" name="U32"/><!-- 1 1 0 -->
<value value="7" name="U8"/> <!-- 1 1 1 -->
</enum>
<enum name="INST_ROUND_MODE">
<value value="0" name="DEFAULT"/>
<value value="1" name="RTZ"/>
<value value="2" name="RTNE"/>
</enum>
<!-- The four instruction words. Vivante has a fixed-size, predictable instruction format
with explicit inputs and outputs. This does simplify code generation,
compared to a weird flow pipe system like the Mali 200/400.
-->
<reg32 offset="0x00000" name="WORD_0">
<bitfield high="5" low="0" name="OPCODE" type="INST_OPCODE"/>
<bitfield high="10" low="6" name="COND" type="INST_CONDITION"/>
<bitfield high="11" low="11" name="SAT" brief="Saturate"/>
<bitfield high="12" low="12" name="DST_USE" brief="Destination used"/>
<bitfield high="15" low="13" name="DST_AMODE" brief="Destination addressing mode"/>
<bitfield high="22" low="16" name="DST_REG" brief="Destination register"/>
<bitfield high="26" low="23" name="DST_COMPS" type="INST_COMPS" brief="Destination components"/>
<bitfield high="31" low="27" name="TEX_ID" brief="Texture sampler id"/>
</reg32>
<reg32 offset="0x00004" name="WORD_1">
<!-- TEX_AMODE is also: rounding mode for ALU instructions -->
<bitfield high="2" low="0" name="TEX_AMODE" type="INST_AMODE" brief="Texture addressing mode"/>
<bitfield high="1" low="0" name="RMODE" type="INST_ROUND_MODE" brief="Rounding mode"/>
<bitfield pos="2" name="PMODE" brief="Pack mode"/>
<bitfield high="10" low="3" name="TEX_SWIZ" type="INST_SWIZ" brief="Texture swizzle">
<doc>This swizzle is applied to the components of the value fetched from the texture.</doc>
</bitfield>
<!-- operand 0 -->
<bitfield high="11" low="11" name="SRC0_USE" brief="Source operand 0 used"/>
<bitfield high="20" low="12" name="SRC0_REG" brief="Source operand 0 register"/>
<bitfield high="21" low="21" name="TYPE_BIT2"/>
<!--
Integer instructions:
1_21 2_31 2_30
===============
0 0 0 f32 / default
0 0 1 s32
0 1 0 s8
0 1 1 u16
1 0 0 f16
1 0 1 s16
1 1 0 u32
1 1 1 u8
-->
<bitfield high="29" low="22" name="SRC0_SWIZ" type="INST_SWIZ" brief="Source operand 0 swizzle"/>
<bitfield high="30" low="30" name="SRC0_NEG" brief="Source operand 0 negate"/>
<bitfield high="31" low="31" name="SRC0_ABS" brief="Source operand 0 absolute"/>
</reg32>
<reg32 offset="0x00008" name="WORD_2">
<bitfield high="2" low="0" name="SRC0_AMODE" type="INST_AMODE" brief="Source operand 0 addressing mode"/>
<bitfield high="5" low="3" name="SRC0_RGROUP" type="INST_RGROUP" brief="Source operand 0 register group"/>
<!-- operand 1 -->
<bitfield high="6" low="6" name="SRC1_USE" brief="Source operand 1 used"/>
<bitfield high="15" low="7" name="SRC1_REG" brief="Source operand 1 register"/>
<bitfield high="16" low="16" name="OPCODE_BIT6" brief="Opcode bit 6 (GC2000+)"/>
<bitfield high="24" low="17" name="SRC1_SWIZ" type="INST_SWIZ" brief="Source operand 1 swizzle"/>
<bitfield high="25" low="25" name="SRC1_NEG" brief="Source operand 1 negate"/>
<bitfield high="26" low="26" name="SRC1_ABS" brief="Source operand 1 absolute"/>
<bitfield high="29" low="27" name="SRC1_AMODE" type="INST_AMODE" brief="Source operand 1 addressing mode"/>
<bitfield high="31" low="30" name="TYPE_BIT01"/>
</reg32>
<reg32 offset="0x0000C" name="WORD_3">
<bitfield high="2" low="0" name="SRC1_RGROUP" type="INST_RGROUP" brief="Source operand 1 register group"/>
<!-- bits 7..21: instruction address, effectively takes the place of src2 operand -->
<bitfield high="21" low="7" name="SRC2_IMM" brief="Immediate (address) operand"/>
<!-- operand 2 -->
<bitfield high="3" low="3" name="SRC2_USE" brief="Source operand 2 used"/>
<bitfield high="12" low="4" name="SRC2_REG" brief="Source operand 2 register"/>
<bitfield high="13" low="13" name="SEL_BIT0"/> <!-- Select instruction for subset of threads in dual-16 mode -->
<bitfield high="21" low="14" name="SRC2_SWIZ" type="INST_SWIZ" brief="Source operand 2 swizzle"/>
<bitfield high="22" low="22" name="SRC2_NEG" brief="Source operand 2 negate"/>
<bitfield high="23" low="23" name="SRC2_ABS" brief="Source operand 2 absolute"/>
<bitfield high="24" low="24" name="SEL_BIT1"/> <!-- Select instruction for subset of threads in dual-16 mode -->
<bitfield high="27" low="25" name="SRC2_AMODE" type="INST_AMODE" brief="Source operand 2 addressing mode"/>
<bitfield high="30" low="28" name="SRC2_RGROUP" type="INST_RGROUP" brief="Source operand 2 register group"/>
<bitfield high="31" low="31" name="UNK3_31"/>
</reg32>
</domain>
</database>
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