Skip to content
Permalink
Branch: master
Find file Copy path
Fetching contributors…
Cannot retrieve contributors at this time
9759 lines (9459 sloc) 373 KB
// Generator : SpinalHDL v1.3.1 git head : 9fe87c98746a5306cb1d5a828db7af3137723649
// Date : 17/03/2019, 08:13:32
// Component : MuraxArduino
`define EnvCtrlEnum_defaultEncoding_type [0:0]
`define EnvCtrlEnum_defaultEncoding_NONE 1'b0
`define EnvCtrlEnum_defaultEncoding_XRET 1'b1
`define ShiftCtrlEnum_defaultEncoding_type [1:0]
`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11
`define AluCtrlEnum_defaultEncoding_type [1:0]
`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
`define BranchCtrlEnum_defaultEncoding_type [1:0]
`define BranchCtrlEnum_defaultEncoding_INC 2'b00
`define BranchCtrlEnum_defaultEncoding_B 2'b01
`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
`define Src2CtrlEnum_defaultEncoding_type [1:0]
`define Src2CtrlEnum_defaultEncoding_RS 2'b00
`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
`define Src2CtrlEnum_defaultEncoding_PC 2'b11
`define Src1CtrlEnum_defaultEncoding_type [1:0]
`define Src1CtrlEnum_defaultEncoding_RS 2'b00
`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
`define JtagState_defaultEncoding_type [3:0]
`define JtagState_defaultEncoding_RESET 4'b0000
`define JtagState_defaultEncoding_IDLE 4'b0001
`define JtagState_defaultEncoding_IR_SELECT 4'b0010
`define JtagState_defaultEncoding_IR_CAPTURE 4'b0011
`define JtagState_defaultEncoding_IR_SHIFT 4'b0100
`define JtagState_defaultEncoding_IR_EXIT1 4'b0101
`define JtagState_defaultEncoding_IR_PAUSE 4'b0110
`define JtagState_defaultEncoding_IR_EXIT2 4'b0111
`define JtagState_defaultEncoding_IR_UPDATE 4'b1000
`define JtagState_defaultEncoding_DR_SELECT 4'b1001
`define JtagState_defaultEncoding_DR_CAPTURE 4'b1010
`define JtagState_defaultEncoding_DR_SHIFT 4'b1011
`define JtagState_defaultEncoding_DR_EXIT1 4'b1100
`define JtagState_defaultEncoding_DR_PAUSE 4'b1101
`define JtagState_defaultEncoding_DR_EXIT2 4'b1110
`define JtagState_defaultEncoding_DR_UPDATE 4'b1111
`define UartStopType_defaultEncoding_type [0:0]
`define UartStopType_defaultEncoding_ONE 1'b0
`define UartStopType_defaultEncoding_TWO 1'b1
`define UartParityType_defaultEncoding_type [1:0]
`define UartParityType_defaultEncoding_NONE 2'b00
`define UartParityType_defaultEncoding_EVEN 2'b01
`define UartParityType_defaultEncoding_ODD 2'b10
`define UartCtrlTxState_defaultEncoding_type [2:0]
`define UartCtrlTxState_defaultEncoding_IDLE 3'b000
`define UartCtrlTxState_defaultEncoding_START 3'b001
`define UartCtrlTxState_defaultEncoding_DATA 3'b010
`define UartCtrlTxState_defaultEncoding_PARITY 3'b011
`define UartCtrlTxState_defaultEncoding_STOP 3'b100
`define UartCtrlRxState_defaultEncoding_type [2:0]
`define UartCtrlRxState_defaultEncoding_IDLE 3'b000
`define UartCtrlRxState_defaultEncoding_START 3'b001
`define UartCtrlRxState_defaultEncoding_DATA 3'b010
`define UartCtrlRxState_defaultEncoding_PARITY 3'b011
`define UartCtrlRxState_defaultEncoding_STOP 3'b100
`define SpiMasterCtrlCmdMode_defaultEncoding_type [0:0]
`define SpiMasterCtrlCmdMode_defaultEncoding_DATA 1'b0
`define SpiMasterCtrlCmdMode_defaultEncoding_SS 1'b1
`define I2cSlaveCmdMode_defaultEncoding_type [2:0]
`define I2cSlaveCmdMode_defaultEncoding_NONE 3'b000
`define I2cSlaveCmdMode_defaultEncoding_START 3'b001
`define I2cSlaveCmdMode_defaultEncoding_RESTART 3'b010
`define I2cSlaveCmdMode_defaultEncoding_STOP 3'b011
`define I2cSlaveCmdMode_defaultEncoding_DROP 3'b100
`define I2cSlaveCmdMode_defaultEncoding_DRIVE 3'b101
`define I2cSlaveCmdMode_defaultEncoding_READ 3'b110
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_type [3:0]
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_boot 4'b0000
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_IDLE 4'b0001
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_START 4'b0010
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_LOW 4'b0011
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_HIGH 4'b0100
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_RESTART 4'b0101
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_STOP1 4'b0110
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_STOP2 4'b0111
`define bridge_masterLogic_fsm_enumDefinition_defaultEncoding_bridge_masterLogic_fsm_TBUF 4'b1000
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
buffers_0 <= io_initial;
buffers_1 <= io_initial;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
module BufferCC_1_ (
input io_dataIn,
output io_dataOut,
input toplevel_io_mainClk,
input toplevel_resetCtrl_mainClkReset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge toplevel_io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
module UartCtrlTx (
input [2:0] io_configFrame_dataLength,
input `UartStopType_defaultEncoding_type io_configFrame_stop,
input `UartParityType_defaultEncoding_type io_configFrame_parity,
input io_samplingTick,
input io_write_valid,
output reg io_write_ready,
input [7:0] io_write_payload,
output io_txd,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire _zz_1_;
wire [0:0] _zz_2_;
wire [2:0] _zz_3_;
wire [0:0] _zz_4_;
wire [2:0] _zz_5_;
reg clockDivider_counter_willIncrement;
wire clockDivider_counter_willClear;
reg [2:0] clockDivider_counter_valueNext;
reg [2:0] clockDivider_counter_value;
wire clockDivider_counter_willOverflowIfInc;
wire clockDivider_willOverflow;
reg [2:0] tickCounter_value;
reg `UartCtrlTxState_defaultEncoding_type stateMachine_state;
reg stateMachine_parity;
reg stateMachine_txd;
reg stateMachine_txd_regNext;
`ifndef SYNTHESIS
reg [23:0] io_configFrame_stop_string;
reg [31:0] io_configFrame_parity_string;
reg [47:0] stateMachine_state_string;
`endif
assign _zz_1_ = (tickCounter_value == io_configFrame_dataLength);
assign _zz_2_ = clockDivider_counter_willIncrement;
assign _zz_3_ = {2'd0, _zz_2_};
assign _zz_4_ = ((io_configFrame_stop == `UartStopType_defaultEncoding_ONE) ? (1'b0) : (1'b1));
assign _zz_5_ = {2'd0, _zz_4_};
`ifndef SYNTHESIS
always @(*) begin
case(io_configFrame_stop)
`UartStopType_defaultEncoding_ONE : io_configFrame_stop_string = "ONE";
`UartStopType_defaultEncoding_TWO : io_configFrame_stop_string = "TWO";
default : io_configFrame_stop_string = "???";
endcase
end
always @(*) begin
case(io_configFrame_parity)
`UartParityType_defaultEncoding_NONE : io_configFrame_parity_string = "NONE";
`UartParityType_defaultEncoding_EVEN : io_configFrame_parity_string = "EVEN";
`UartParityType_defaultEncoding_ODD : io_configFrame_parity_string = "ODD ";
default : io_configFrame_parity_string = "????";
endcase
end
always @(*) begin
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : stateMachine_state_string = "IDLE ";
`UartCtrlTxState_defaultEncoding_START : stateMachine_state_string = "START ";
`UartCtrlTxState_defaultEncoding_DATA : stateMachine_state_string = "DATA ";
`UartCtrlTxState_defaultEncoding_PARITY : stateMachine_state_string = "PARITY";
`UartCtrlTxState_defaultEncoding_STOP : stateMachine_state_string = "STOP ";
default : stateMachine_state_string = "??????";
endcase
end
`endif
always @ (*) begin
clockDivider_counter_willIncrement = 1'b0;
if(io_samplingTick)begin
clockDivider_counter_willIncrement = 1'b1;
end
end
assign clockDivider_counter_willClear = 1'b0;
assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == (3'b100));
assign clockDivider_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement);
always @ (*) begin
if(clockDivider_willOverflow)begin
clockDivider_counter_valueNext = (3'b000);
end else begin
clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_3_);
end
if(clockDivider_counter_willClear)begin
clockDivider_counter_valueNext = (3'b000);
end
end
always @ (*) begin
stateMachine_txd = 1'b1;
io_write_ready = 1'b0;
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : begin
end
`UartCtrlTxState_defaultEncoding_START : begin
stateMachine_txd = 1'b0;
end
`UartCtrlTxState_defaultEncoding_DATA : begin
stateMachine_txd = io_write_payload[tickCounter_value];
if(clockDivider_willOverflow)begin
if(_zz_1_)begin
io_write_ready = 1'b1;
end
end
end
`UartCtrlTxState_defaultEncoding_PARITY : begin
stateMachine_txd = stateMachine_parity;
end
default : begin
end
endcase
end
assign io_txd = stateMachine_txd_regNext;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
clockDivider_counter_value <= (3'b000);
stateMachine_state <= `UartCtrlTxState_defaultEncoding_IDLE;
stateMachine_txd_regNext <= 1'b1;
end else begin
clockDivider_counter_value <= clockDivider_counter_valueNext;
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : begin
if((io_write_valid && clockDivider_willOverflow))begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_START;
end
end
`UartCtrlTxState_defaultEncoding_START : begin
if(clockDivider_willOverflow)begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_DATA;
end
end
`UartCtrlTxState_defaultEncoding_DATA : begin
if(clockDivider_willOverflow)begin
if(_zz_1_)begin
if((io_configFrame_parity == `UartParityType_defaultEncoding_NONE))begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_STOP;
end else begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_PARITY;
end
end
end
end
`UartCtrlTxState_defaultEncoding_PARITY : begin
if(clockDivider_willOverflow)begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_STOP;
end
end
default : begin
if(clockDivider_willOverflow)begin
if((tickCounter_value == _zz_5_))begin
stateMachine_state <= (io_write_valid ? `UartCtrlTxState_defaultEncoding_START : `UartCtrlTxState_defaultEncoding_IDLE);
end
end
end
endcase
stateMachine_txd_regNext <= stateMachine_txd;
end
end
always @ (posedge toplevel_io_mainClk) begin
if(clockDivider_willOverflow)begin
tickCounter_value <= (tickCounter_value + (3'b001));
end
if(clockDivider_willOverflow)begin
stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd);
end
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : begin
end
`UartCtrlTxState_defaultEncoding_START : begin
if(clockDivider_willOverflow)begin
stateMachine_parity <= (io_configFrame_parity == `UartParityType_defaultEncoding_ODD);
tickCounter_value <= (3'b000);
end
end
`UartCtrlTxState_defaultEncoding_DATA : begin
if(clockDivider_willOverflow)begin
if(_zz_1_)begin
tickCounter_value <= (3'b000);
end
end
end
`UartCtrlTxState_defaultEncoding_PARITY : begin
if(clockDivider_willOverflow)begin
tickCounter_value <= (3'b000);
end
end
default : begin
end
endcase
end
endmodule
module UartCtrlRx (
input [2:0] io_configFrame_dataLength,
input `UartStopType_defaultEncoding_type io_configFrame_stop,
input `UartParityType_defaultEncoding_type io_configFrame_parity,
input io_samplingTick,
output io_read_valid,
output [7:0] io_read_payload,
input io_rxd,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire _zz_1_;
wire bufferCC_5__io_dataOut;
wire _zz_2_;
wire _zz_3_;
wire _zz_4_;
wire [0:0] _zz_5_;
wire [2:0] _zz_6_;
wire sampler_synchroniser;
wire sampler_samples_0;
reg sampler_samples_1;
reg sampler_samples_2;
reg sampler_value;
reg sampler_tick;
reg [2:0] bitTimer_counter;
reg bitTimer_tick;
reg [2:0] bitCounter_value;
reg `UartCtrlRxState_defaultEncoding_type stateMachine_state;
reg stateMachine_parity;
reg [7:0] stateMachine_shifter;
reg stateMachine_validReg;
`ifndef SYNTHESIS
reg [23:0] io_configFrame_stop_string;
reg [31:0] io_configFrame_parity_string;
reg [47:0] stateMachine_state_string;
`endif
assign _zz_2_ = (bitTimer_counter == (3'b000));
assign _zz_3_ = (sampler_tick && (! sampler_value));
assign _zz_4_ = (bitCounter_value == io_configFrame_dataLength);
assign _zz_5_ = ((io_configFrame_stop == `UartStopType_defaultEncoding_ONE) ? (1'b0) : (1'b1));
assign _zz_6_ = {2'd0, _zz_5_};
BufferCC bufferCC_5_ (
.io_initial(_zz_1_),
.io_dataIn(io_rxd),
.io_dataOut(bufferCC_5__io_dataOut),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_systemReset(toplevel_resetCtrl_systemReset)
);
`ifndef SYNTHESIS
always @(*) begin
case(io_configFrame_stop)
`UartStopType_defaultEncoding_ONE : io_configFrame_stop_string = "ONE";
`UartStopType_defaultEncoding_TWO : io_configFrame_stop_string = "TWO";
default : io_configFrame_stop_string = "???";
endcase
end
always @(*) begin
case(io_configFrame_parity)
`UartParityType_defaultEncoding_NONE : io_configFrame_parity_string = "NONE";
`UartParityType_defaultEncoding_EVEN : io_configFrame_parity_string = "EVEN";
`UartParityType_defaultEncoding_ODD : io_configFrame_parity_string = "ODD ";
default : io_configFrame_parity_string = "????";
endcase
end
always @(*) begin
case(stateMachine_state)
`UartCtrlRxState_defaultEncoding_IDLE : stateMachine_state_string = "IDLE ";
`UartCtrlRxState_defaultEncoding_START : stateMachine_state_string = "START ";
`UartCtrlRxState_defaultEncoding_DATA : stateMachine_state_string = "DATA ";
`UartCtrlRxState_defaultEncoding_PARITY : stateMachine_state_string = "PARITY";
`UartCtrlRxState_defaultEncoding_STOP : stateMachine_state_string = "STOP ";
default : stateMachine_state_string = "??????";
endcase
end
`endif
assign _zz_1_ = 1'b0;
assign sampler_synchroniser = bufferCC_5__io_dataOut;
assign sampler_samples_0 = sampler_synchroniser;
always @ (*) begin
bitTimer_tick = 1'b0;
if(sampler_tick)begin
if(_zz_2_)begin
bitTimer_tick = 1'b1;
end
end
end
assign io_read_valid = stateMachine_validReg;
assign io_read_payload = stateMachine_shifter;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
sampler_samples_1 <= 1'b1;
sampler_samples_2 <= 1'b1;
sampler_value <= 1'b1;
sampler_tick <= 1'b0;
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
stateMachine_validReg <= 1'b0;
end else begin
if(io_samplingTick)begin
sampler_samples_1 <= sampler_samples_0;
end
if(io_samplingTick)begin
sampler_samples_2 <= sampler_samples_1;
end
sampler_value <= (((1'b0 || ((1'b1 && sampler_samples_0) && sampler_samples_1)) || ((1'b1 && sampler_samples_0) && sampler_samples_2)) || ((1'b1 && sampler_samples_1) && sampler_samples_2));
sampler_tick <= io_samplingTick;
stateMachine_validReg <= 1'b0;
case(stateMachine_state)
`UartCtrlRxState_defaultEncoding_IDLE : begin
if(_zz_3_)begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_START;
end
end
`UartCtrlRxState_defaultEncoding_START : begin
if(bitTimer_tick)begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_DATA;
if((sampler_value == 1'b1))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end
end
end
`UartCtrlRxState_defaultEncoding_DATA : begin
if(bitTimer_tick)begin
if(_zz_4_)begin
if((io_configFrame_parity == `UartParityType_defaultEncoding_NONE))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_PARITY;
end
end
end
end
`UartCtrlRxState_defaultEncoding_PARITY : begin
if(bitTimer_tick)begin
if((stateMachine_parity == sampler_value))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end
end
end
default : begin
if(bitTimer_tick)begin
if((! sampler_value))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end else begin
if((bitCounter_value == _zz_6_))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end
end
end
end
endcase
end
end
always @ (posedge toplevel_io_mainClk) begin
if(sampler_tick)begin
bitTimer_counter <= (bitTimer_counter - (3'b001));
if(_zz_2_)begin
bitTimer_counter <= (3'b100);
end
end
if(bitTimer_tick)begin
bitCounter_value <= (bitCounter_value + (3'b001));
end
if(bitTimer_tick)begin
stateMachine_parity <= (stateMachine_parity ^ sampler_value);
end
case(stateMachine_state)
`UartCtrlRxState_defaultEncoding_IDLE : begin
if(_zz_3_)begin
bitTimer_counter <= (3'b001);
end
end
`UartCtrlRxState_defaultEncoding_START : begin
if(bitTimer_tick)begin
bitCounter_value <= (3'b000);
stateMachine_parity <= (io_configFrame_parity == `UartParityType_defaultEncoding_ODD);
end
end
`UartCtrlRxState_defaultEncoding_DATA : begin
if(bitTimer_tick)begin
stateMachine_shifter[bitCounter_value] <= sampler_value;
if(_zz_4_)begin
bitCounter_value <= (3'b000);
end
end
end
`UartCtrlRxState_defaultEncoding_PARITY : begin
if(bitTimer_tick)begin
bitCounter_value <= (3'b000);
end
end
default : begin
end
endcase
end
endmodule
//BufferCC_2_ remplaced by BufferCC
//BufferCC_3_ remplaced by BufferCC
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:0] io_occupancy,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [0:0] _zz_5_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [32:0] _zz_2_;
wire [32:0] _zz_3_;
reg [32:0] _zz_4_;
assign _zz_5_ = _zz_2_[0 : 0];
always @ (*) begin
_zz_1_ = 1'b0;
pushPtr_willIncrement = 1'b0;
if(pushing)begin
_zz_1_ = 1'b1;
pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
pushPtr_willClear = 1'b0;
popPtr_willClear = 1'b0;
if(io_flush)begin
pushPtr_willClear = 1'b1;
popPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @ (*) begin
popPtr_willIncrement = 1'b0;
if(popping)begin
popPtr_willIncrement = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (! risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (! full);
always @ (*) begin
if((! empty))begin
io_pop_valid = 1'b1;
io_pop_payload_error = _zz_5_[0];
io_pop_payload_inst = _zz_2_[32 : 1];
end else begin
io_pop_valid = io_push_valid;
io_pop_payload_error = io_push_payload_error;
io_pop_payload_inst = io_push_payload_inst;
end
end
assign _zz_2_ = _zz_3_;
assign io_occupancy = (risingOccupancy && ptrMatch);
assign _zz_3_ = _zz_4_;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
risingOccupancy <= 1'b0;
end else begin
if((pushing != popping))begin
risingOccupancy <= pushing;
end
if(io_flush)begin
risingOccupancy <= 1'b0;
end
end
end
always @ (posedge toplevel_io_mainClk) begin
if(_zz_1_)begin
_zz_4_ <= {io_push_payload_inst,io_push_payload_error};
end
end
endmodule
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input _zz_1_,
input toplevel_io_mainClk,
input toplevel_resetCtrl_mainClkReset);
wire bufferCC_5__io_dataOut;
wire outHitSignal;
reg inputArea_target = 0;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg outputArea_flow_m2sPipe_valid;
reg outputArea_flow_m2sPipe_payload_last;
reg [0:0] outputArea_flow_m2sPipe_payload_fragment;
BufferCC_1_ bufferCC_5_ (
.io_dataIn(inputArea_target),
.io_dataOut(bufferCC_5__io_dataOut),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_mainClkReset(toplevel_resetCtrl_mainClkReset)
);
assign outputArea_target = bufferCC_5__io_dataOut;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = outputArea_flow_m2sPipe_valid;
assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last;
assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment;
always @ (posedge _zz_1_) begin
if(io_input_valid)begin
inputArea_target <= (! inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @ (posedge toplevel_io_mainClk) begin
outputArea_hit <= outputArea_target;
if(outputArea_flow_valid)begin
outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last;
outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment;
end
end
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_mainClkReset) begin
if (toplevel_resetCtrl_mainClkReset) begin
outputArea_flow_m2sPipe_valid <= 1'b0;
end else begin
outputArea_flow_m2sPipe_valid <= outputArea_flow_valid;
end
end
endmodule
module UartCtrl (
input [2:0] io_config_frame_dataLength,
input `UartStopType_defaultEncoding_type io_config_frame_stop,
input `UartParityType_defaultEncoding_type io_config_frame_parity,
input [19:0] io_config_clockDivider,
input io_write_valid,
output io_write_ready,
input [7:0] io_write_payload,
output io_read_valid,
output [7:0] io_read_payload,
output io_uart_txd,
input io_uart_rxd,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire tx_io_write_ready;
wire tx_io_txd;
wire rx_io_read_valid;
wire [7:0] rx_io_read_payload;
reg [19:0] clockDivider_counter;
wire clockDivider_tick;
`ifndef SYNTHESIS
reg [23:0] io_config_frame_stop_string;
reg [31:0] io_config_frame_parity_string;
`endif
UartCtrlTx tx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_write_valid(io_write_valid),
.io_write_ready(tx_io_write_ready),
.io_write_payload(io_write_payload),
.io_txd(tx_io_txd),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_systemReset(toplevel_resetCtrl_systemReset)
);
UartCtrlRx rx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_read_valid(rx_io_read_valid),
.io_read_payload(rx_io_read_payload),
.io_rxd(io_uart_rxd),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_systemReset(toplevel_resetCtrl_systemReset)
);
`ifndef SYNTHESIS
always @(*) begin
case(io_config_frame_stop)
`UartStopType_defaultEncoding_ONE : io_config_frame_stop_string = "ONE";
`UartStopType_defaultEncoding_TWO : io_config_frame_stop_string = "TWO";
default : io_config_frame_stop_string = "???";
endcase
end
always @(*) begin
case(io_config_frame_parity)
`UartParityType_defaultEncoding_NONE : io_config_frame_parity_string = "NONE";
`UartParityType_defaultEncoding_EVEN : io_config_frame_parity_string = "EVEN";
`UartParityType_defaultEncoding_ODD : io_config_frame_parity_string = "ODD ";
default : io_config_frame_parity_string = "????";
endcase
end
`endif
assign clockDivider_tick = (clockDivider_counter == (20'b00000000000000000000));
assign io_write_ready = tx_io_write_ready;
assign io_read_valid = rx_io_read_valid;
assign io_read_payload = rx_io_read_payload;
assign io_uart_txd = tx_io_txd;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
clockDivider_counter <= (20'b00000000000000000000);
end else begin
clockDivider_counter <= (clockDivider_counter - (20'b00000000000000000001));
if(clockDivider_tick)begin
clockDivider_counter <= io_config_clockDivider;
end
end
end
endmodule
module StreamFifo (
input io_push_valid,
output io_push_ready,
input [7:0] io_push_payload,
output io_pop_valid,
input io_pop_ready,
output [7:0] io_pop_payload,
input io_flush,
output [4:0] io_occupancy,
output [4:0] io_availability,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [7:0] _zz_3_;
wire [0:0] _zz_4_;
wire [3:0] _zz_5_;
wire [0:0] _zz_6_;
wire [3:0] _zz_7_;
wire [3:0] _zz_8_;
wire _zz_9_;
reg _zz_1_;
reg logic_pushPtr_willIncrement;
reg logic_pushPtr_willClear;
reg [3:0] logic_pushPtr_valueNext;
reg [3:0] logic_pushPtr_value;
wire logic_pushPtr_willOverflowIfInc;
wire logic_pushPtr_willOverflow;
reg logic_popPtr_willIncrement;
reg logic_popPtr_willClear;
reg [3:0] logic_popPtr_valueNext;
reg [3:0] logic_popPtr_value;
wire logic_popPtr_willOverflowIfInc;
wire logic_popPtr_willOverflow;
wire logic_ptrMatch;
reg logic_risingOccupancy;
wire logic_pushing;
wire logic_popping;
wire logic_empty;
wire logic_full;
reg _zz_2_;
wire [3:0] logic_ptrDif;
reg [7:0] logic_ram [0:15];
assign _zz_4_ = logic_pushPtr_willIncrement;
assign _zz_5_ = {3'd0, _zz_4_};
assign _zz_6_ = logic_popPtr_willIncrement;
assign _zz_7_ = {3'd0, _zz_6_};
assign _zz_8_ = (logic_popPtr_value - logic_pushPtr_value);
assign _zz_9_ = 1'b1;
always @ (posedge toplevel_io_mainClk) begin
if(_zz_1_) begin
logic_ram[logic_pushPtr_value] <= io_push_payload;
end
end
always @ (posedge toplevel_io_mainClk) begin
if(_zz_9_) begin
_zz_3_ <= logic_ram[logic_popPtr_valueNext];
end
end
always @ (*) begin
_zz_1_ = 1'b0;
logic_pushPtr_willIncrement = 1'b0;
if(logic_pushing)begin
_zz_1_ = 1'b1;
logic_pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
logic_pushPtr_willClear = 1'b0;
logic_popPtr_willClear = 1'b0;
if(io_flush)begin
logic_pushPtr_willClear = 1'b1;
logic_popPtr_willClear = 1'b1;
end
end
assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == (4'b1111));
assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement);
always @ (*) begin
logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_5_);
if(logic_pushPtr_willClear)begin
logic_pushPtr_valueNext = (4'b0000);
end
end
always @ (*) begin
logic_popPtr_willIncrement = 1'b0;
if(logic_popping)begin
logic_popPtr_willIncrement = 1'b1;
end
end
assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == (4'b1111));
assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement);
always @ (*) begin
logic_popPtr_valueNext = (logic_popPtr_value + _zz_7_);
if(logic_popPtr_willClear)begin
logic_popPtr_valueNext = (4'b0000);
end
end
assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value);
assign logic_pushing = (io_push_valid && io_push_ready);
assign logic_popping = (io_pop_valid && io_pop_ready);
assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy));
assign logic_full = (logic_ptrMatch && logic_risingOccupancy);
assign io_push_ready = (! logic_full);
assign io_pop_valid = ((! logic_empty) && (! (_zz_2_ && (! logic_full))));
assign io_pop_payload = _zz_3_;
assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value);
assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif};
assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_8_};
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
logic_pushPtr_value <= (4'b0000);
logic_popPtr_value <= (4'b0000);
logic_risingOccupancy <= 1'b0;
_zz_2_ <= 1'b0;
end else begin
logic_pushPtr_value <= logic_pushPtr_valueNext;
logic_popPtr_value <= logic_popPtr_valueNext;
_zz_2_ <= (logic_popPtr_valueNext == logic_pushPtr_value);
if((logic_pushing != logic_popping))begin
logic_risingOccupancy <= logic_pushing;
end
if(io_flush)begin
logic_risingOccupancy <= 1'b0;
end
end
end
endmodule
//StreamFifo_1_ remplaced by StreamFifo
module PinInterruptCtrl (
input io_pinInterrupt_pin,
input io_rising,
input io_falling,
output reg io_interrupt,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg io_pinInterrupt_pin_regNext;
reg io_pinInterrupt_pin_regNext_1_;
always @ (*) begin
io_interrupt = 1'b0;
if(((io_rising && (io_pinInterrupt_pin && (! io_pinInterrupt_pin_regNext))) || (io_falling && ((! io_pinInterrupt_pin) && io_pinInterrupt_pin_regNext_1_))))begin
io_interrupt = 1'b1;
end
end
always @ (posedge toplevel_io_mainClk) begin
io_pinInterrupt_pin_regNext <= io_pinInterrupt_pin;
io_pinInterrupt_pin_regNext_1_ <= io_pinInterrupt_pin;
end
endmodule
module Prescaler (
input io_clear,
input [15:0] io_limit,
output io_overflow,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [15:0] counter;
assign io_overflow = (counter == io_limit);
always @ (posedge toplevel_io_mainClk) begin
counter <= (counter + (16'b0000000000000001));
if((io_clear || io_overflow))begin
counter <= (16'b0000000000000000);
end
end
endmodule
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [0:0] _zz_1_;
wire [15:0] _zz_2_;
reg [15:0] counter;
wire limitHit;
reg inhibitFull;
assign _zz_1_ = (! limitHit);
assign _zz_2_ = {15'd0, _zz_1_};
assign limitHit = (counter == io_limit);
assign io_full = ((limitHit && io_tick) && (! inhibitFull));
assign io_value = counter;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
inhibitFull <= 1'b0;
end else begin
if(io_tick)begin
inhibitFull <= limitHit;
end
if(io_clear)begin
inhibitFull <= 1'b0;
end
end
end
always @ (posedge toplevel_io_mainClk) begin
if(io_tick)begin
counter <= (counter + _zz_2_);
end
if(io_clear)begin
counter <= (16'b0000000000000000);
end
end
endmodule
//Timer_1_ remplaced by Timer
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
pendings <= (2'b00);
end else begin
pendings <= ((pendings & (~ io_clears)) | io_inputs);
end
end
endmodule
module PwmCtrl (
output io_pwm_pin,
input [7:0] io_duty,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [7:0] counter;
assign io_pwm_pin = ((counter <= io_duty) && (! (io_duty == (8'b00000000))));
always @ (posedge toplevel_io_mainClk) begin
counter <= (counter + (8'b00000001));
end
endmodule
module ServoCtrl (
output io_servo_pin,
input [11:0] io_pulseMicros,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [14:0] _zz_1_;
reg [5:0] counter;
reg [14:0] micros;
assign _zz_1_ = {3'd0, io_pulseMicros};
assign io_servo_pin = ((micros < _zz_1_) && (io_pulseMicros != (12'b000000000000)));
always @ (posedge toplevel_io_mainClk) begin
counter <= (counter + (6'b000001));
if((counter == (6'b110001)))begin
micros <= (micros + (15'b000000000000001));
counter <= (6'b000000);
end
if((micros == (15'b100111000011111)))begin
micros <= (15'b000000000000000);
end
end
endmodule
module MuxCtrl (
output [31:0] io_mux_pins,
input [31:0] io_signals);
assign io_mux_pins = io_signals;
endmodule
module MachineTimerCtrl (
output [31:0] io_micros,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [5:0] counter;
reg [31:0] microCounter;
assign io_micros = microCounter;
always @ (posedge toplevel_io_mainClk) begin
counter <= (counter + (6'b000001));
if((counter == (6'b110001)))begin
counter <= (6'b000000);
microCounter <= (microCounter + (32'b00000000000000000000000000000001));
end
end
endmodule
module ToneCtrl (
output io_tone_pin,
input [31:0] io_period,
input [31:0] io_duration,
input io_clear,
output io_done,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [31:0] _zz_1_;
reg [7:0] prescaler_1_;
reg [31:0] counter;
reg [31:0] timeCounter;
reg [31:0] millis;
reg toneOut;
assign _zz_1_ = (io_period - (32'b00000000000000000000000000000001));
assign io_tone_pin = toneOut;
assign io_done = (millis == io_duration);
always @ (posedge toplevel_io_mainClk) begin
if(io_clear)begin
millis <= (32'b00000000000000000000000000000000);
end
if((! io_done))begin
if((timeCounter == (32'b00000000000000001100001101001111)))begin
millis <= (millis + (32'b00000000000000000000000000000001));
timeCounter <= (32'b00000000000000000000000000000000);
end else begin
timeCounter <= (timeCounter + (32'b00000000000000000000000000000001));
end
prescaler_1_ <= (prescaler_1_ + (8'b00000001));
if((prescaler_1_ == (8'b00011000)))begin
prescaler_1_ <= (8'b00000000);
counter <= (counter + (32'b00000000000000000000000000000001));
if((counter == _zz_1_))begin
counter <= (32'b00000000000000000000000000000000);
toneOut <= (! toneOut);
end
end
end else begin
toneOut <= 1'b0;
end
end
endmodule
module ShiftOutCtrl (
output io_shiftOut_dataPin,
output io_shiftOut_clockPin,
input io_bitOrder,
input [7:0] io_value,
input [31:0] io_preScale,
input io_set,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [31:0] _zz_1_;
reg [31:0] prescaler_1_;
reg [7:0] shiftReg;
reg [3:0] bitCounter;
reg clockReg;
assign _zz_1_ = (io_preScale - (32'b00000000000000000000000000000001));
assign io_shiftOut_dataPin = (io_bitOrder ? shiftReg[7] : shiftReg[0]);
assign io_shiftOut_clockPin = clockReg;
always @ (posedge toplevel_io_mainClk) begin
if(io_set)begin
bitCounter <= (4'b1000);
clockReg <= 1'b0;
shiftReg <= io_value;
end
if((! (bitCounter == (4'b0000))))begin
prescaler_1_ <= (prescaler_1_ + (32'b00000000000000000000000000000001));
if((prescaler_1_ == _zz_1_))begin
prescaler_1_ <= (32'b00000000000000000000000000000000);
clockReg <= (! clockReg);
if(clockReg)begin
bitCounter <= (bitCounter - (4'b0001));
if(io_bitOrder)begin
shiftReg <= (shiftReg <<< 1);
end else begin
shiftReg <= (shiftReg >>> 1);
end
end
end
end
end
endmodule
module SpiMasterCtrl (
input io_config_kind_cpol,
input io_config_kind_cpha,
input [31:0] io_config_sclkToogle,
input [0:0] io_config_ss_activeHigh,
input [31:0] io_config_ss_setup,
input [31:0] io_config_ss_hold,
input [31:0] io_config_ss_disable,
input io_cmd_valid,
output reg io_cmd_ready,
input `SpiMasterCtrlCmdMode_defaultEncoding_type io_cmd_payload_mode,
input [8:0] io_cmd_payload_args,
output io_rsp_valid,
output [7:0] io_rsp_payload,
output [0:0] io_spi_ss,
output io_spi_sclk,
output io_spi_mosi,
input io_spi_miso,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire _zz_4_;
wire _zz_5_;
wire _zz_6_;
wire _zz_7_;
wire [0:0] _zz_8_;
wire [3:0] _zz_9_;
wire [8:0] _zz_10_;
wire [0:0] _zz_11_;
wire [0:0] _zz_12_;
wire [7:0] _zz_13_;
wire [2:0] _zz_14_;
wire [2:0] _zz_15_;
reg [31:0] timer_counter;
reg timer_reset;
wire timer_ss_setupHit;
wire timer_ss_holdHit;
wire timer_ss_disableHit;
wire timer_sclkToogleHit;
reg fsm_counter_willIncrement;
wire fsm_counter_willClear;
reg [3:0] fsm_counter_valueNext;
reg [3:0] fsm_counter_value;
wire fsm_counter_willOverflowIfInc;
wire fsm_counter_willOverflow;
reg [7:0] fsm_buffer;
reg [0:0] fsm_ss;
reg _zz_1_;
reg _zz_2_;
reg _zz_3_;
`ifndef SYNTHESIS
reg [31:0] io_cmd_payload_mode_string;
`endif
assign _zz_4_ = (io_cmd_payload_mode == `SpiMasterCtrlCmdMode_defaultEncoding_DATA);
assign _zz_5_ = _zz_11_[0];
assign _zz_6_ = (! fsm_counter_value[0]);
assign _zz_7_ = ((! io_cmd_valid) || io_cmd_ready);
assign _zz_8_ = fsm_counter_willIncrement;
assign _zz_9_ = {3'd0, _zz_8_};
assign _zz_10_ = {fsm_buffer,io_spi_miso};
assign _zz_11_ = io_cmd_payload_args[0 : 0];
assign _zz_12_ = io_cmd_payload_args[8 : 8];
assign _zz_13_ = io_cmd_payload_args[7 : 0];
assign _zz_14_ = ((3'b111) - _zz_15_);
assign _zz_15_ = (fsm_counter_value >>> 1);
`ifndef SYNTHESIS
always @(*) begin
case(io_cmd_payload_mode)
`SpiMasterCtrlCmdMode_defaultEncoding_DATA : io_cmd_payload_mode_string = "DATA";
`SpiMasterCtrlCmdMode_defaultEncoding_SS : io_cmd_payload_mode_string = "SS ";
default : io_cmd_payload_mode_string = "????";
endcase
end
`endif
always @ (*) begin
timer_reset = 1'b0;
fsm_counter_willIncrement = 1'b0;
io_cmd_ready = 1'b0;
if(io_cmd_valid)begin
if(_zz_4_)begin
if(timer_sclkToogleHit)begin
fsm_counter_willIncrement = 1'b1;
timer_reset = 1'b1;
io_cmd_ready = fsm_counter_willOverflowIfInc;
end
end else begin
if(_zz_5_)begin
if(timer_ss_setupHit)begin
io_cmd_ready = 1'b1;
end
end else begin
if(_zz_6_)begin
if(timer_ss_holdHit)begin
fsm_counter_willIncrement = 1'b1;
timer_reset = 1'b1;
end
end else begin
if(timer_ss_disableHit)begin
io_cmd_ready = 1'b1;
end
end
end
end
end
if(_zz_7_)begin
timer_reset = 1'b1;
end
end
assign timer_ss_setupHit = (timer_counter == io_config_ss_setup);
assign timer_ss_holdHit = (timer_counter == io_config_ss_hold);
assign timer_ss_disableHit = (timer_counter == io_config_ss_disable);
assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle);
assign fsm_counter_willClear = 1'b0;
assign fsm_counter_willOverflowIfInc = (fsm_counter_value == (4'b1111));
assign fsm_counter_willOverflow = (fsm_counter_willOverflowIfInc && fsm_counter_willIncrement);
always @ (*) begin
fsm_counter_valueNext = (fsm_counter_value + _zz_9_);
if(fsm_counter_willClear)begin
fsm_counter_valueNext = (4'b0000);
end
end
assign io_rsp_valid = _zz_1_;
assign io_rsp_payload = fsm_buffer;
assign io_spi_ss = (fsm_ss ^ io_config_ss_activeHigh);
assign io_spi_sclk = _zz_2_;
assign io_spi_mosi = _zz_3_;
always @ (posedge toplevel_io_mainClk) begin
timer_counter <= (timer_counter + (32'b00000000000000000000000000000001));
if(timer_reset)begin
timer_counter <= (32'b00000000000000000000000000000000);
end
if(io_cmd_valid)begin
if(_zz_4_)begin
if(timer_sclkToogleHit)begin
if(fsm_counter_value[0])begin
fsm_buffer <= _zz_10_[7:0];
end
end
end
end
_zz_2_ <= (((io_cmd_valid && (io_cmd_payload_mode == `SpiMasterCtrlCmdMode_defaultEncoding_DATA)) && (fsm_counter_value[0] ^ io_config_kind_cpha)) ^ io_config_kind_cpol);
_zz_3_ <= _zz_13_[_zz_14_];
end
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
fsm_counter_value <= (4'b0000);
fsm_ss <= (1'b1);
_zz_1_ <= 1'b0;
end else begin
fsm_counter_value <= fsm_counter_valueNext;
if(io_cmd_valid)begin
if(! _zz_4_) begin
if(_zz_5_)begin
fsm_ss[0] <= 1'b0;
end else begin
if(! _zz_6_) begin
fsm_ss[0] <= 1'b1;
end
end
end
end
_zz_1_ <= (((io_cmd_valid && io_cmd_ready) && (io_cmd_payload_mode == `SpiMasterCtrlCmdMode_defaultEncoding_DATA)) && _zz_12_[0]);
if(_zz_7_)begin
fsm_counter_value <= (4'b0000);
end
end
end
endmodule
module StreamFifo_2_ (
input io_push_valid,
output io_push_ready,
input `SpiMasterCtrlCmdMode_defaultEncoding_type io_push_payload_mode,
input [8:0] io_push_payload_args,
output io_pop_valid,
input io_pop_ready,
output `SpiMasterCtrlCmdMode_defaultEncoding_type io_pop_payload_mode,
output [8:0] io_pop_payload_args,
input io_flush,
output [5:0] io_occupancy,
output [5:0] io_availability,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [9:0] _zz_6_;
wire [0:0] _zz_7_;
wire [4:0] _zz_8_;
wire [0:0] _zz_9_;
wire [4:0] _zz_10_;
wire [4:0] _zz_11_;
wire _zz_12_;
wire [9:0] _zz_13_;
reg _zz_1_;
reg logic_pushPtr_willIncrement;
reg logic_pushPtr_willClear;
reg [4:0] logic_pushPtr_valueNext;
reg [4:0] logic_pushPtr_value;
wire logic_pushPtr_willOverflowIfInc;
wire logic_pushPtr_willOverflow;
reg logic_popPtr_willIncrement;
reg logic_popPtr_willClear;
reg [4:0] logic_popPtr_valueNext;
reg [4:0] logic_popPtr_value;
wire logic_popPtr_willOverflowIfInc;
wire logic_popPtr_willOverflow;
wire logic_ptrMatch;
reg logic_risingOccupancy;
wire logic_pushing;
wire logic_popping;
wire logic_empty;
wire logic_full;
reg _zz_2_;
wire `SpiMasterCtrlCmdMode_defaultEncoding_type _zz_3_;
wire [9:0] _zz_4_;
wire `SpiMasterCtrlCmdMode_defaultEncoding_type _zz_5_;
wire [4:0] logic_ptrDif;
`ifndef SYNTHESIS
reg [31:0] io_push_payload_mode_string;
reg [31:0] io_pop_payload_mode_string;
reg [31:0] _zz_3__string;
reg [31:0] _zz_5__string;
`endif
reg [9:0] logic_ram [0:31];
assign _zz_7_ = logic_pushPtr_willIncrement;
assign _zz_8_ = {4'd0, _zz_7_};
assign _zz_9_ = logic_popPtr_willIncrement;
assign _zz_10_ = {4'd0, _zz_9_};
assign _zz_11_ = (logic_popPtr_value - logic_pushPtr_value);
assign _zz_12_ = 1'b1;
assign _zz_13_ = {io_push_payload_args,io_push_payload_mode};
always @ (posedge toplevel_io_mainClk) begin
if(_zz_1_) begin
logic_ram[logic_pushPtr_value] <= _zz_13_;
end
end
always @ (posedge toplevel_io_mainClk) begin
if(_zz_12_) begin
_zz_6_ <= logic_ram[logic_popPtr_valueNext];
end
end
`ifndef SYNTHESIS
always @(*) begin
case(io_push_payload_mode)
`SpiMasterCtrlCmdMode_defaultEncoding_DATA : io_push_payload_mode_string = "DATA";
`SpiMasterCtrlCmdMode_defaultEncoding_SS : io_push_payload_mode_string = "SS ";
default : io_push_payload_mode_string = "????";
endcase
end
always @(*) begin
case(io_pop_payload_mode)
`SpiMasterCtrlCmdMode_defaultEncoding_DATA : io_pop_payload_mode_string = "DATA";
`SpiMasterCtrlCmdMode_defaultEncoding_SS : io_pop_payload_mode_string = "SS ";
default : io_pop_payload_mode_string = "????";
endcase
end
always @(*) begin
case(_zz_3_)
`SpiMasterCtrlCmdMode_defaultEncoding_DATA : _zz_3__string = "DATA";
`SpiMasterCtrlCmdMode_defaultEncoding_SS : _zz_3__string = "SS ";
default : _zz_3__string = "????";
endcase
end
always @(*) begin
case(_zz_5_)
`SpiMasterCtrlCmdMode_defaultEncoding_DATA : _zz_5__string = "DATA";
`SpiMasterCtrlCmdMode_defaultEncoding_SS : _zz_5__string = "SS ";
default : _zz_5__string = "????";
endcase
end
`endif
always @ (*) begin
_zz_1_ = 1'b0;
logic_pushPtr_willIncrement = 1'b0;
if(logic_pushing)begin
_zz_1_ = 1'b1;
logic_pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
logic_pushPtr_willClear = 1'b0;
logic_popPtr_willClear = 1'b0;
if(io_flush)begin
logic_pushPtr_willClear = 1'b1;
logic_popPtr_willClear = 1'b1;
end
end
assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == (5'b11111));
assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement);
always @ (*) begin
logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_8_);
if(logic_pushPtr_willClear)begin
logic_pushPtr_valueNext = (5'b00000);
end
end
always @ (*) begin
logic_popPtr_willIncrement = 1'b0;
if(logic_popping)begin
logic_popPtr_willIncrement = 1'b1;
end
end
assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == (5'b11111));
assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement);
always @ (*) begin
logic_popPtr_valueNext = (logic_popPtr_value + _zz_10_);
if(logic_popPtr_willClear)begin
logic_popPtr_valueNext = (5'b00000);
end
end
assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value);
assign logic_pushing = (io_push_valid && io_push_ready);
assign logic_popping = (io_pop_valid && io_pop_ready);
assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy));
assign logic_full = (logic_ptrMatch && logic_risingOccupancy);
assign io_push_ready = (! logic_full);
assign io_pop_valid = ((! logic_empty) && (! (_zz_2_ && (! logic_full))));
assign _zz_4_ = _zz_6_;
assign _zz_5_ = _zz_4_[0 : 0];
assign _zz_3_ = _zz_5_;
assign io_pop_payload_mode = _zz_3_;
assign io_pop_payload_args = _zz_4_[9 : 1];
assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value);
assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif};
assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_11_};
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
logic_pushPtr_value <= (5'b00000);
logic_popPtr_value <= (5'b00000);
logic_risingOccupancy <= 1'b0;
_zz_2_ <= 1'b0;
end else begin
logic_pushPtr_value <= logic_pushPtr_valueNext;
logic_popPtr_value <= logic_popPtr_valueNext;
_zz_2_ <= (logic_popPtr_valueNext == logic_pushPtr_value);
if((logic_pushing != logic_popping))begin
logic_risingOccupancy <= logic_pushing;
end
if(io_flush)begin
logic_risingOccupancy <= 1'b0;
end
end
end
endmodule
module StreamFifo_3_ (
input io_push_valid,
output io_push_ready,
input [7:0] io_push_payload,
output io_pop_valid,
input io_pop_ready,
output [7:0] io_pop_payload,
input io_flush,
output [5:0] io_occupancy,
output [5:0] io_availability,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [7:0] _zz_3_;
wire [0:0] _zz_4_;
wire [4:0] _zz_5_;
wire [0:0] _zz_6_;
wire [4:0] _zz_7_;
wire [4:0] _zz_8_;
wire _zz_9_;
reg _zz_1_;
reg logic_pushPtr_willIncrement;
reg logic_pushPtr_willClear;
reg [4:0] logic_pushPtr_valueNext;
reg [4:0] logic_pushPtr_value;
wire logic_pushPtr_willOverflowIfInc;
wire logic_pushPtr_willOverflow;
reg logic_popPtr_willIncrement;
reg logic_popPtr_willClear;
reg [4:0] logic_popPtr_valueNext;
reg [4:0] logic_popPtr_value;
wire logic_popPtr_willOverflowIfInc;
wire logic_popPtr_willOverflow;
wire logic_ptrMatch;
reg logic_risingOccupancy;
wire logic_pushing;
wire logic_popping;
wire logic_empty;
wire logic_full;
reg _zz_2_;
wire [4:0] logic_ptrDif;
reg [7:0] logic_ram [0:31];
assign _zz_4_ = logic_pushPtr_willIncrement;
assign _zz_5_ = {4'd0, _zz_4_};
assign _zz_6_ = logic_popPtr_willIncrement;
assign _zz_7_ = {4'd0, _zz_6_};
assign _zz_8_ = (logic_popPtr_value - logic_pushPtr_value);
assign _zz_9_ = 1'b1;
always @ (posedge toplevel_io_mainClk) begin
if(_zz_1_) begin
logic_ram[logic_pushPtr_value] <= io_push_payload;
end
end
always @ (posedge toplevel_io_mainClk) begin
if(_zz_9_) begin
_zz_3_ <= logic_ram[logic_popPtr_valueNext];
end
end
always @ (*) begin
_zz_1_ = 1'b0;
logic_pushPtr_willIncrement = 1'b0;
if(logic_pushing)begin
_zz_1_ = 1'b1;
logic_pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
logic_pushPtr_willClear = 1'b0;
logic_popPtr_willClear = 1'b0;
if(io_flush)begin
logic_pushPtr_willClear = 1'b1;
logic_popPtr_willClear = 1'b1;
end
end
assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == (5'b11111));
assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement);
always @ (*) begin
logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_5_);
if(logic_pushPtr_willClear)begin
logic_pushPtr_valueNext = (5'b00000);
end
end
always @ (*) begin
logic_popPtr_willIncrement = 1'b0;
if(logic_popping)begin
logic_popPtr_willIncrement = 1'b1;
end
end
assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == (5'b11111));
assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement);
always @ (*) begin
logic_popPtr_valueNext = (logic_popPtr_value + _zz_7_);
if(logic_popPtr_willClear)begin
logic_popPtr_valueNext = (5'b00000);
end
end
assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value);
assign logic_pushing = (io_push_valid && io_push_ready);
assign logic_popping = (io_pop_valid && io_pop_ready);
assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy));
assign logic_full = (logic_ptrMatch && logic_risingOccupancy);
assign io_push_ready = (! logic_full);
assign io_pop_valid = ((! logic_empty) && (! (_zz_2_ && (! logic_full))));
assign io_pop_payload = _zz_3_;
assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value);
assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif};
assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_8_};
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
logic_pushPtr_value <= (5'b00000);
logic_popPtr_value <= (5'b00000);
logic_risingOccupancy <= 1'b0;
_zz_2_ <= 1'b0;
end else begin
logic_pushPtr_value <= logic_pushPtr_valueNext;
logic_popPtr_value <= logic_popPtr_valueNext;
_zz_2_ <= (logic_popPtr_valueNext == logic_pushPtr_value);
if((logic_pushing != logic_popping))begin
logic_risingOccupancy <= logic_pushing;
end
if(io_flush)begin
logic_risingOccupancy <= 1'b0;
end
end
end
endmodule
module I2cSlave (
output io_i2c_sda_write,
input io_i2c_sda_read,
output io_i2c_scl_write,
input io_i2c_scl_read,
input [9:0] io_config_samplingClockDivider,
input [19:0] io_config_timeout,
input [5:0] io_config_tsuData,
output reg `I2cSlaveCmdMode_defaultEncoding_type io_bus_cmd_kind,
output io_bus_cmd_data,
input io_bus_rsp_valid,
input io_bus_rsp_enable,
input io_bus_rsp_data,
output io_internals_inFrame,
output io_internals_sdaRead,
output io_internals_sclRead,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire _zz_10_;
wire _zz_11_;
wire bufferCC_5__io_dataOut;
wire bufferCC_6__io_dataOut;
wire _zz_12_;
wire _zz_13_;
reg [9:0] filter_timer_counter;
wire filter_timer_tick;
wire filter_sampler_sclSync;
wire filter_sampler_sdaSync;
wire filter_sampler_sclSamples_0;
wire filter_sampler_sclSamples_1;
wire filter_sampler_sclSamples_2;
wire _zz_1_;
reg _zz_2_;
reg _zz_3_;
wire filter_sampler_sdaSamples_0;
wire filter_sampler_sdaSamples_1;
wire filter_sampler_sdaSamples_2;
wire _zz_4_;
reg _zz_5_;
reg _zz_6_;
reg filter_sda;
reg filter_scl;
wire sclEdge_rise;
wire sclEdge_fall;
wire sclEdge_toggle;
reg filter_scl_regNext;
wire sdaEdge_rise;
wire sdaEdge_fall;
wire sdaEdge_toggle;
reg filter_sda_regNext;
wire detector_start;
wire detector_stop;
reg [5:0] tsuData_counter;
wire tsuData_done;
reg tsuData_reset;
reg ctrl_inFrame;
reg ctrl_inFrameData;
reg ctrl_sdaWrite;
reg ctrl_sclWrite;
wire ctrl_rspBufferIn_valid;
wire ctrl_rspBufferIn_ready;
wire ctrl_rspBufferIn_payload_enable;
wire ctrl_rspBufferIn_payload_data;
wire ctrl_rspBufferIn_m2sPipe_valid;
reg ctrl_rspBufferIn_m2sPipe_ready;
wire ctrl_rspBufferIn_m2sPipe_payload_enable;
wire ctrl_rspBufferIn_m2sPipe_payload_data;
reg _zz_7_;
reg _zz_8_;
reg _zz_9_;
wire ctrl_rspAhead_valid;
wire ctrl_rspAhead_payload_enable;
wire ctrl_rspAhead_payload_data;
reg [19:0] timeout_counter;
reg timeout_tick;
reg ctrl_sclWrite_regNext;
reg ctrl_sdaWrite_regNext;
`ifndef SYNTHESIS
reg [55:0] io_bus_cmd_kind_string;
`endif
assign _zz_12_ = (detector_stop || timeout_tick);
assign _zz_13_ = (sclEdge_toggle || (! ctrl_inFrame));
BufferCC bufferCC_5_ (
.io_initial(_zz_10_),
.io_dataIn(io_i2c_scl_read),
.io_dataOut(bufferCC_5__io_dataOut),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_systemReset(toplevel_resetCtrl_systemReset)
);
BufferCC bufferCC_6_ (
.io_initial(_zz_11_),
.io_dataIn(io_i2c_sda_read),
.io_dataOut(bufferCC_6__io_dataOut),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_systemReset(toplevel_resetCtrl_systemReset)
);
`ifndef SYNTHESIS
always @(*) begin
case(io_bus_cmd_kind)
`I2cSlaveCmdMode_defaultEncoding_NONE : io_bus_cmd_kind_string = "NONE ";
`I2cSlaveCmdMode_defaultEncoding_START : io_bus_cmd_kind_string = "START ";
`I2cSlaveCmdMode_defaultEncoding_RESTART : io_bus_cmd_kind_string = "RESTART";
`I2cSlaveCmdMode_defaultEncoding_STOP : io_bus_cmd_kind_string = "STOP ";
`I2cSlaveCmdMode_defaultEncoding_DROP : io_bus_cmd_kind_string = "DROP ";
`I2cSlaveCmdMode_defaultEncoding_DRIVE : io_bus_cmd_kind_string = "DRIVE ";
`I2cSlaveCmdMode_defaultEncoding_READ : io_bus_cmd_kind_string = "READ ";
default : io_bus_cmd_kind_string = "???????";
endcase
end
`endif
assign filter_timer_tick = (filter_timer_counter == (10'b0000000000));
assign _zz_10_ = 1'b1;
assign filter_sampler_sclSync = bufferCC_5__io_dataOut;
assign _zz_11_ = 1'b1;
assign filter_sampler_sdaSync = bufferCC_6__io_dataOut;
assign _zz_1_ = filter_sampler_sclSync;
assign filter_sampler_sclSamples_0 = _zz_1_;
assign filter_sampler_sclSamples_1 = _zz_2_;
assign filter_sampler_sclSamples_2 = _zz_3_;
assign _zz_4_ = filter_sampler_sdaSync;
assign filter_sampler_sdaSamples_0 = _zz_4_;
assign filter_sampler_sdaSamples_1 = _zz_5_;
assign filter_sampler_sdaSamples_2 = _zz_6_;
assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl);
assign sclEdge_fall = (filter_scl_regNext && (! filter_scl));
assign sclEdge_toggle = (filter_scl_regNext != filter_scl);
assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda);
assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda));
assign sdaEdge_toggle = (filter_sda_regNext != filter_sda);
assign detector_start = (filter_scl && sdaEdge_fall);
assign detector_stop = (filter_scl && sdaEdge_rise);
assign tsuData_done = (tsuData_counter == (6'b000000));
always @ (*) begin
tsuData_reset = 1'b0;
ctrl_sdaWrite = 1'b1;
ctrl_sclWrite = 1'b1;
ctrl_rspBufferIn_m2sPipe_ready = 1'b0;
io_bus_cmd_kind = `I2cSlaveCmdMode_defaultEncoding_NONE;
if(ctrl_inFrame)begin
if(sclEdge_rise)begin
io_bus_cmd_kind = `I2cSlaveCmdMode_defaultEncoding_READ;
end
if(sclEdge_fall)begin
ctrl_rspBufferIn_m2sPipe_ready = 1'b1;
end
end
if(ctrl_inFrameData)begin
if(((! ctrl_rspBufferIn_m2sPipe_valid) || ctrl_rspBufferIn_m2sPipe_ready))begin
io_bus_cmd_kind = `I2cSlaveCmdMode_defaultEncoding_DRIVE;
end
if(((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))))begin
ctrl_sclWrite = 1'b0;
end
tsuData_reset = (! ctrl_rspAhead_valid);
if((ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable))begin
ctrl_sdaWrite = ctrl_rspAhead_payload_data;
end
end
if(detector_start)begin
io_bus_cmd_kind = (ctrl_inFrame ? `I2cSlaveCmdMode_defaultEncoding_RESTART : `I2cSlaveCmdMode_defaultEncoding_START);
end
if(_zz_12_)begin
if(ctrl_inFrame)begin
io_bus_cmd_kind = (timeout_tick ? `I2cSlaveCmdMode_defaultEncoding_DROP : `I2cSlaveCmdMode_defaultEncoding_STOP);
end
end
end
assign ctrl_rspBufferIn_ready = ((1'b1 && (! ctrl_rspBufferIn_m2sPipe_valid)) || ctrl_rspBufferIn_m2sPipe_ready);
assign ctrl_rspBufferIn_m2sPipe_valid = _zz_7_;
assign ctrl_rspBufferIn_m2sPipe_payload_enable = _zz_8_;
assign ctrl_rspBufferIn_m2sPipe_payload_data = _zz_9_;
assign ctrl_rspAhead_valid = (ctrl_rspBufferIn_m2sPipe_valid ? ctrl_rspBufferIn_m2sPipe_valid : ctrl_rspBufferIn_valid);
assign ctrl_rspAhead_payload_enable = (ctrl_rspBufferIn_m2sPipe_valid ? ctrl_rspBufferIn_m2sPipe_payload_enable : ctrl_rspBufferIn_payload_enable);
assign ctrl_rspAhead_payload_data = (ctrl_rspBufferIn_m2sPipe_valid ? ctrl_rspBufferIn_m2sPipe_payload_data : ctrl_rspBufferIn_payload_data);
assign ctrl_rspBufferIn_valid = io_bus_rsp_valid;
assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable;
assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data;
assign io_bus_cmd_data = filter_sda;
always @ (*) begin
timeout_tick = (timeout_counter == (20'b00000000000000000000));
if(_zz_13_)begin
timeout_tick = 1'b0;
end
end
assign io_internals_inFrame = ctrl_inFrame;
assign io_internals_sdaRead = filter_sda;
assign io_internals_sclRead = filter_scl;
assign io_i2c_scl_write = ctrl_sclWrite_regNext;
assign io_i2c_sda_write = ctrl_sdaWrite_regNext;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
filter_timer_counter <= (10'b0000000000);
_zz_2_ <= 1'b1;
_zz_3_ <= 1'b1;
_zz_5_ <= 1'b1;
_zz_6_ <= 1'b1;
filter_sda <= 1'b1;
filter_scl <= 1'b1;
filter_scl_regNext <= 1'b1;
filter_sda_regNext <= 1'b1;
tsuData_counter <= (6'b000000);
ctrl_inFrame <= 1'b0;
ctrl_inFrameData <= 1'b0;
_zz_7_ <= 1'b0;
timeout_counter <= (20'b00000000000000000000);
ctrl_sclWrite_regNext <= 1'b1;
ctrl_sdaWrite_regNext <= 1'b1;
end else begin
filter_timer_counter <= (filter_timer_counter - (10'b0000000001));
if(filter_timer_tick)begin
filter_timer_counter <= io_config_samplingClockDivider;
end
if(filter_timer_tick)begin
_zz_2_ <= _zz_1_;
end
if(filter_timer_tick)begin
_zz_3_ <= _zz_2_;
end
if(filter_timer_tick)begin
_zz_5_ <= _zz_4_;
end
if(filter_timer_tick)begin
_zz_6_ <= _zz_5_;
end
if(filter_timer_tick)begin
if((((filter_sampler_sdaSamples_0 != filter_sda) && (filter_sampler_sdaSamples_1 != filter_sda)) && (filter_sampler_sdaSamples_2 != filter_sda)))begin
filter_sda <= filter_sampler_sdaSamples_2;
end
if((((filter_sampler_sclSamples_0 != filter_scl) && (filter_sampler_sclSamples_1 != filter_scl)) && (filter_sampler_sclSamples_2 != filter_scl)))begin
filter_scl <= filter_sampler_sclSamples_2;
end
end
filter_scl_regNext <= filter_scl;
filter_sda_regNext <= filter_sda;
if((! tsuData_done))begin
tsuData_counter <= (tsuData_counter - (6'b000001));
end
if(tsuData_reset)begin
tsuData_counter <= io_config_tsuData;
end
if(ctrl_rspBufferIn_ready)begin
_zz_7_ <= ctrl_rspBufferIn_valid;
end
if(ctrl_inFrame)begin
if(sclEdge_fall)begin
ctrl_inFrameData <= 1'b1;
end
end
if(detector_start)begin
ctrl_inFrame <= 1'b1;
ctrl_inFrameData <= 1'b0;
end
timeout_counter <= (timeout_counter - (20'b00000000000000000001));
if(_zz_13_)begin
timeout_counter <= io_config_timeout;
end
if(_zz_12_)begin
ctrl_inFrame <= 1'b0;
ctrl_inFrameData <= 1'b0;
end
ctrl_sclWrite_regNext <= ctrl_sclWrite;
ctrl_sdaWrite_regNext <= ctrl_sdaWrite;
end
end
always @ (posedge toplevel_io_mainClk) begin
if(ctrl_rspBufferIn_ready)begin
_zz_8_ <= ctrl_rspBufferIn_payload_enable;
_zz_9_ <= ctrl_rspBufferIn_payload_data;
end
end
endmodule
module PulseInCtrl (
input io_pulseIn_pin,
input [31:0] io_timeout,
input io_value,
input io_req,
output [31:0] io_pulseLength,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [31:0] _zz_1_;
reg [31:0] pulseOut;
reg [31:0] micros;
reg [7:0] counter;
reg req;
reg [1:0] state;
assign _zz_1_ = (io_timeout - (32'b00000000000000000000000000000001));
assign io_pulseLength = pulseOut;
always @ (posedge toplevel_io_mainClk) begin
if(io_req)begin
req <= 1'b1;
pulseOut <= (32'b00000000000000000000000000000000);
end
if(req)begin
counter <= (counter + (8'b00000001));
if((counter == (8'b00110001)))begin
micros <= (micros + (32'b00000000000000000000000000000001));
counter <= (8'b00000000);
end
if((((32'b00000000000000000000000000000000) < io_timeout) && (_zz_1_ <= micros)))begin
req <= 1'b0;
pulseOut <= (32'b11111111111111111111111111111111);
end else begin
if(((state == (2'b00)) && (io_pulseIn_pin != io_value)))begin
state <= (2'b01);
end else begin
if(((state == (2'b01)) && (io_pulseIn_pin == io_value)))begin
state <= (2'b10);
counter <= (8'b00000000);
micros <= (32'b00000000000000000000000000000000);
end else begin
if(((state == (2'b10)) && (io_pulseIn_pin != io_value)))begin
if((micros == (32'b00000000000000000000000000000000)))begin
pulseOut <= (32'b11111111111111111111111111111111);
end else begin
pulseOut <= micros;
end
req <= 1'b0;
end
end
end
end
end else begin
counter <= (8'b00000000);
micros <= (32'b00000000000000000000000000000000);
state <= (2'b00);
end
end
endmodule
module SevenSegmentCtrl (
output io_sevenSegment_digitPin,
output [6:0] io_sevenSegment_segPins,
input [7:0] io_value,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [6:0] _zz_1_;
wire [3:0] _zz_2_;
wire [6:0] segROM_0;
wire [6:0] segROM_1;
wire [6:0] segROM_2;
wire [6:0] segROM_3;
wire [6:0] segROM_4;
wire [6:0] segROM_5;
wire [6:0] segROM_6;
wire [6:0] segROM_7;
wire [6:0] segROM_8;
wire [6:0] segROM_9;
wire [6:0] segROM_10;
wire [6:0] segROM_11;
wire [6:0] segROM_12;
wire [6:0] segROM_13;
wire [6:0] segROM_14;
wire [6:0] segROM_15;
reg [23:0] prescaler_1_;
reg digPos;
reg [6:0] segOut;
assign _zz_2_ = (digPos ? io_value[3 : 0] : io_value[7 : 4]);
always @(*) begin
case(_zz_2_)
4'b0000 : begin
_zz_1_ = segROM_0;
end
4'b0001 : begin
_zz_1_ = segROM_1;
end
4'b0010 : begin
_zz_1_ = segROM_2;
end
4'b0011 : begin
_zz_1_ = segROM_3;
end
4'b0100 : begin
_zz_1_ = segROM_4;
end
4'b0101 : begin
_zz_1_ = segROM_5;
end
4'b0110 : begin
_zz_1_ = segROM_6;
end
4'b0111 : begin
_zz_1_ = segROM_7;
end
4'b1000 : begin
_zz_1_ = segROM_8;
end
4'b1001 : begin
_zz_1_ = segROM_9;
end
4'b1010 : begin
_zz_1_ = segROM_10;
end
4'b1011 : begin
_zz_1_ = segROM_11;
end
4'b1100 : begin
_zz_1_ = segROM_12;
end
4'b1101 : begin
_zz_1_ = segROM_13;
end
4'b1110 : begin
_zz_1_ = segROM_14;
end
default : begin
_zz_1_ = segROM_15;
end
endcase
end
assign segROM_0 = (7'b1111110);
assign segROM_1 = (7'b0110000);
assign segROM_2 = (7'b1101101);
assign segROM_3 = (7'b1111001);
assign segROM_4 = (7'b0110011);
assign segROM_5 = (7'b1011011);
assign segROM_6 = (7'b1011111);
assign segROM_7 = (7'b1110000);
assign segROM_8 = (7'b1111111);
assign segROM_9 = (7'b1111011);
assign segROM_10 = (7'b1110111);
assign segROM_11 = (7'b0011111);
assign segROM_12 = (7'b1101110);
assign segROM_13 = (7'b0111101);
assign segROM_14 = (7'b1001111);
assign segROM_15 = (7'b1000111);
assign io_sevenSegment_digitPin = digPos;
assign io_sevenSegment_segPins = segOut;
always @ (posedge toplevel_io_mainClk) begin
prescaler_1_ <= (prescaler_1_ + (24'b000000000000000000000001));
if((prescaler_1_ == (24'b000000001100001101010000)))begin
prescaler_1_ <= (24'b000000000000000000000000);
digPos <= (! digPos);
segOut <= _zz_1_;
end
end
endmodule
module ShiftInCtrl (
input io_shiftIn_dataPin,
output io_shiftIn_clockPin,
output [7:0] io_value,
input io_req,
input [31:0] io_preScale,
input io_bitOrder,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
wire [31:0] _zz_1_;
reg [7:0] shiftReg;
reg [3:0] bitCounter;
reg clockReg;
reg [31:0] prescaler_1_;
assign _zz_1_ = (io_preScale - (32'b00000000000000000000000000000001));
assign io_value = shiftReg;
assign io_shiftIn_clockPin = clockReg;
always @ (posedge toplevel_io_mainClk) begin
if(io_req)begin
bitCounter <= (4'b1000);
end
if(((4'b0000) < bitCounter))begin
prescaler_1_ <= (prescaler_1_ + (32'b00000000000000000000000000000001));
if((prescaler_1_ == _zz_1_))begin
prescaler_1_ <= (32'b00000000000000000000000000000000);
clockReg <= (! clockReg);
if((! clockReg))begin
bitCounter <= (bitCounter - (4'b0001));
if(io_bitOrder)begin
shiftReg <= (shiftReg <<< 1);
end else begin
shiftReg <= (shiftReg >>> 1);
end
end else begin
if(io_bitOrder)begin
shiftReg[7] <= io_shiftIn_dataPin;
end else begin
shiftReg[0] <= io_shiftIn_dataPin;
end
end
end
end
end
endmodule
module BufferCC_4_ (
input io_dataIn,
output io_dataOut,
input toplevel_io_mainClk);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge toplevel_io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
module MuraxMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_valid,
output io_iBus_rsp_payload_error,
output [31:0] io_iBus_rsp_payload_inst,
input io_dBus_cmd_valid,
output reg io_dBus_cmd_ready,
input io_dBus_cmd_payload_wr,
input [31:0] io_dBus_cmd_payload_address,
input [31:0] io_dBus_cmd_payload_data,
input [1:0] io_dBus_cmd_payload_size,
output io_dBus_rsp_ready,
output io_dBus_rsp_error,
output [31:0] io_dBus_rsp_data,
output reg io_masterBus_cmd_valid,
input io_masterBus_cmd_ready,
output io_masterBus_cmd_payload_write,
output [31:0] io_masterBus_cmd_payload_address,
output [31:0] io_masterBus_cmd_payload_data,
output [3:0] io_masterBus_cmd_payload_mask,
input io_masterBus_rsp_valid,
input [31:0] io_masterBus_rsp_payload_data,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset);
reg [3:0] _zz_1_;
reg rspPending;
reg rspTarget;
always @ (*) begin
io_masterBus_cmd_valid = (io_iBus_cmd_valid || io_dBus_cmd_valid);
io_iBus_cmd_ready = (io_masterBus_cmd_ready && (! io_dBus_cmd_valid));
io_dBus_cmd_ready = io_masterBus_cmd_ready;
if((rspPending && (! io_masterBus_rsp_valid)))begin
io_iBus_cmd_ready = 1'b0;
io_dBus_cmd_ready = 1'b0;
io_masterBus_cmd_valid = 1'b0;
end
end
assign io_masterBus_cmd_payload_write = (io_dBus_cmd_valid && io_dBus_cmd_payload_wr);
assign io_masterBus_cmd_payload_address = (io_dBus_cmd_valid ? io_dBus_cmd_payload_address : io_iBus_cmd_payload_pc);
assign io_masterBus_cmd_payload_data = io_dBus_cmd_payload_data;
always @ (*) begin
case(io_dBus_cmd_payload_size)
2'b00 : begin
_zz_1_ = (4'b0001);
end
2'b01 : begin
_zz_1_ = (4'b0011);
end
default : begin
_zz_1_ = (4'b1111);
end
endcase
end
assign io_masterBus_cmd_payload_mask = (_zz_1_ <<< io_dBus_cmd_payload_address[1 : 0]);
assign io_iBus_rsp_valid = (io_masterBus_rsp_valid && (! rspTarget));
assign io_iBus_rsp_payload_inst = io_masterBus_rsp_payload_data;
assign io_iBus_rsp_payload_error = 1'b0;
assign io_dBus_rsp_ready = (io_masterBus_rsp_valid && rspTarget);
assign io_dBus_rsp_data = io_masterBus_rsp_payload_data;
assign io_dBus_rsp_error = 1'b0;
always @ (posedge toplevel_io_mainClk or posedge toplevel_resetCtrl_systemReset) begin
if (toplevel_resetCtrl_systemReset) begin
rspPending <= 1'b0;
rspTarget <= 1'b0;
end else begin
if(io_masterBus_rsp_valid)begin
rspPending <= 1'b0;
end
if(((io_masterBus_cmd_valid && io_masterBus_cmd_ready) && (! io_masterBus_cmd_payload_write)))begin
rspTarget <= io_dBus_cmd_valid;
rspPending <= 1'b1;
end
end
end
endmodule
module VexRiscv (
output iBus_cmd_valid,
input iBus_cmd_ready,
output [31:0] iBus_cmd_payload_pc,
input iBus_rsp_valid,
input iBus_rsp_payload_error,
input [31:0] iBus_rsp_payload_inst,
input timerInterrupt,
input externalInterrupt,
input debug_bus_cmd_valid,
output reg debug_bus_cmd_ready,
input debug_bus_cmd_payload_wr,
input [7:0] debug_bus_cmd_payload_address,
input [31:0] debug_bus_cmd_payload_data,
output reg [31:0] debug_bus_rsp_data,
output debug_resetOut,
output dBus_cmd_valid,
input dBus_cmd_ready,
output dBus_cmd_payload_wr,
output [31:0] dBus_cmd_payload_address,
output [31:0] dBus_cmd_payload_data,
output [1:0] dBus_cmd_payload_size,
input dBus_rsp_ready,
input dBus_rsp_error,
input [31:0] dBus_rsp_data,
input toplevel_io_mainClk,
input toplevel_resetCtrl_systemReset,
input toplevel_resetCtrl_mainClkReset);
wire _zz_151_;
reg [31:0] _zz_152_;
reg [31:0] _zz_153_;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
wire _zz_154_;
wire _zz_155_;
wire _zz_156_;
wire _zz_157_;
wire _zz_158_;
wire _zz_159_;
wire _zz_160_;
wire _zz_161_;
wire [5:0] _zz_162_;
wire [1:0] _zz_163_;
wire [1:0] _zz_164_;
wire _zz_165_;
wire [1:0] _zz_166_;
wire [1:0] _zz_167_;
wire [2:0] _zz_168_;
wire [31:0] _zz_169_;
wire [2:0] _zz_170_;
wire [0:0] _zz_171_;
wire [2:0] _zz_172_;
wire [0:0] _zz_173_;
wire [2:0] _zz_174_;
wire [0:0] _zz_175_;
wire [2:0] _zz_176_;
wire [0:0] _zz_177_;
wire [0:0] _zz_178_;
wire [0:0] _zz_179_;
wire [0:0] _zz_180_;
wire [0:0] _zz_181_;
wire [0:0] _zz_182_;
wire [0:0] _zz_183_;
wire [0:0] _zz_184_;
wire [0:0] _zz_185_;
wire [0:0] _zz_186_;
wire [0:0] _zz_187_;
wire [2:0] _zz_188_;
wire [4:0] _zz_189_;
wire [11:0] _zz_190_;
wire [11:0] _zz_191_;
wire [31:0] _zz_192_;
wire [31:0] _zz_193_;
wire [31:0] _zz_194_;
wire [31:0] _zz_195_;
wire [1:0] _zz_196_;
wire [31:0] _zz_197_;
wire [1:0] _zz_198_;
wire [1:0] _zz_199_;
wire [31:0] _zz_200_;
wire [32:0] _zz_201_;
wire [19:0] _zz_202_;
wire [11:0] _zz_203_;
wire [11:0] _zz_204_;
wire [0:0] _zz_205_;
wire [0:0] _zz_206_;
wire [0:0] _zz_207_;
wire [0:0] _zz_208_;
wire [0:0] _zz_209_;
wire [0:0] _zz_210_;
wire _zz_211_;
wire _zz_212_;
wire [31:0] _zz_213_;
wire [31:0] _zz_214_;
wire [31:0] _zz_215_;
wire [31:0] _zz_216_;
wire _zz_217_;
wire [0:0] _zz_218_;
wire [0:0] _zz_219_;
wire [0:0] _zz_220_;
wire [0:0] _zz_221_;
wire _zz_222_;
wire [0:0] _zz_223_;
wire [17:0] _zz_224_;
wire [31:0] _zz_225_;
wire _zz_226_;
wire [0:0] _zz_227_;
wire [0:0] _zz_228_;
wire _zz_229_;
wire [0:0] _zz_230_;
wire [13:0] _zz_231_;
wire [31:0] _zz_232_;
wire [31:0] _zz_233_;
wire [31:0] _zz_234_;
wire [31:0] _zz_235_;
wire _zz_236_;
wire [1:0] _zz_237_;
wire [1:0] _zz_238_;
wire _zz_239_;
wire [0:0] _zz_240_;
wire [9:0] _zz_241_;
wire [31:0] _zz_242_;
wire [31:0] _zz_243_;
wire _zz_244_;
wire [0:0] _zz_245_;
wire [0:0] _zz_246_;
wire [0:0] _zz_247_;
wire [2:0] _zz_248_;
wire [4:0] _zz_249_;
wire [4:0] _zz_250_;
wire _zz_251_;
wire [0:0] _zz_252_;
wire [5:0] _zz_253_;
wire [31:0] _zz_254_;
wire [31:0] _zz_255_;
wire [31:0] _zz_256_;
wire [31:0] _zz_257_;
wire [31:0] _zz_258_;
wire [31:0] _zz_259_;
wire [31:0] _zz_260_;
wire _zz_261_;
wire [0:0] _zz_262_;
wire [0:0] _zz_263_;
wire [0:0] _zz_264_;
wire [2:0] _zz_265_;
wire [0:0] _zz_266_;
wire [0:0] _zz_267_;
wire [0:0] _zz_268_;
wire [0:0] _zz_269_;
wire _zz_270_;
wire [0:0] _zz_271_;
wire [3:0] _zz_272_;
wire [31:0] _zz_273_;
wire [31:0] _zz_274_;
wire [31:0] _zz_275_;
wire _zz_276_;
wire [0:0] _zz_277_;
wire [0:0] _zz_278_;
wire [31:0] _zz_279_;
wire [31:0] _zz_280_;
wire [31:0] _zz_281_;
wire [31:0] _zz_282_;
wire [31:0] _zz_283_;
wire [31:0] _zz_284_;
wire [0:0] _zz_285_;
wire [0:0] _zz_286_;
wire [1:0] _zz_287_;
wire [1:0] _zz_288_;
wire _zz_289_;
wire [0:0] _zz_290_;
wire [1:0] _zz_291_;
wire [31:0] _zz_292_;
wire [31:0] _zz_293_;
wire [31:0] _zz_294_;
wire [31:0] _zz_295_;
wire [31:0] _zz_296_;
wire [31:0] _zz_297_;
wire [31:0] _zz_298_;
wire _zz_299_;
wire _zz_300_;
wire [0:0] _zz_301_;
wire [0:0] _zz_302_;
wire [2:0] _zz_303_;
wire [2:0] _zz_304_;
wire _zz_305_;
wire _zz_306_;
wire [31:0] _zz_307_;
wire [31:0] _zz_308_;
wire [31:0] _zz_309_;
wire [31:0] _zz_310_;
wire [31:0] _zz_311_;
wire [31:0] _zz_312_;
wire _zz_313_;
wire _zz_314_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_1_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_2_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_3_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_4_;
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_5_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_6_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_7_;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] decode_SRC1;
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_9_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_10_;
wire [31:0] memory_PC;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_CSR_WRITE_OPCODE;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire [31:0] decode_SRC2;
wire decode_CSR_READ_OPCODE;
wire decode_MEMORY_ENABLE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire [31:0] decode_RS2;
wire decode_DO_EBREAK;
wire decode_SRC_USE_SUB_LESS;
wire [31:0] decode_RS1;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_11_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13_;
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_14_;
wire `AluCtrlEnum_defaultEncoding_type _zz_15_;
wire `AluCtrlEnum_defaultEncoding_type _zz_16_;
wire decode_IS_CSR;
wire [31:0] memory_MEMORY_READ_DATA;
wire decode_SRC_LESS_UNSIGNED;
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_17_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_18_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_19_;
wire execute_DO_EBREAK;
wire decode_IS_EBREAK;
wire _zz_20_;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire [31:0] _zz_21_;
wire [31:0] execute_PC;
wire [31:0] execute_RS1;
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_22_;
wire _zz_23_;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_;
wire _zz_25_;
wire [31:0] _zz_26_;
wire [31:0] _zz_27_;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_28_;
wire [31:0] _zz_29_;
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_30_;
wire [31:0] _zz_31_;
wire [31:0] _zz_32_;
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_33_;
wire [31:0] _zz_34_;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_35_;
wire [31:0] _zz_36_;
wire [31:0] execute_SRC2;
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37_;
wire [31:0] _zz_38_;
wire _zz_39_;
reg _zz_40_;
wire [31:0] _zz_41_;
wire [31:0] _zz_42_;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire _zz_43_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_44_;
wire _zz_45_;
wire _zz_46_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_47_;
wire _zz_48_;
wire _zz_49_;
wire _zz_50_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_51_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_52_;
wire _zz_53_;
wire _zz_54_;
wire _zz_55_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_56_;
wire _zz_57_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_;
wire `AluCtrlEnum_defaultEncoding_type _zz_59_;
reg [31:0] _zz_60_;
wire [31:0] execute_SRC1;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_61_;
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_62_;
wire _zz_63_;
wire _zz_64_;
wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_65_;
reg [31:0] _zz_66_;
wire writeBack_MEMORY_ENABLE;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire [31:0] memory_INSTRUCTION;
wire memory_MEMORY_ENABLE;
wire [31:0] _zz_67_;
wire [1:0] _zz_68_;
wire [31:0] execute_RS2;
wire [31:0] execute_SRC_ADD;
wire [31:0] execute_INSTRUCTION;
wire execute_ALIGNEMENT_FAULT;
wire execute_MEMORY_ENABLE;
reg [31:0] _zz_69_;
wire [31:0] _zz_70_;
wire [31:0] _zz_71_;
wire [31:0] _zz_72_;
wire [31:0] _zz_73_;
wire [31:0] writeBack_PC /* verilator public */ ;
wire [31:0] writeBack_INSTRUCTION /* verilator public */ ;
wire [31:0] decode_PC /* verilator public */ ;
wire [31:0] decode_INSTRUCTION /* verilator public */ ;
reg decode_arbitration_haltItself /* verilator public */ ;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushAll /* verilator public */ ;
wire decode_arbitration_redoIt;
reg decode_arbitration_isValid /* verilator public */ ;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
reg execute_arbitration_flushAll;
wire execute_arbitration_redoIt;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
reg memory_arbitration_flushAll;
wire memory_arbitration_redoIt;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushAll;
wire writeBack_arbitration_redoIt;
reg writeBack_arbitration_isValid /* verilator public */ ;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring /* verilator public */ ;
reg _zz_74_;
reg _zz_75_;
reg _zz_76_;
reg _zz_77_;
reg [31:0] _zz_78_;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
reg _zz_79_;
wire _zz_80_;
wire [31:0] _zz_81_;
reg _zz_82_;
reg _zz_83_;
wire IBusSimplePlugin_jump_pcLoad_valid;
wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
wire [1:0] _zz_84_;
wire IBusSimplePlugin_fetchPc_preOutput_valid;
wire IBusSimplePlugin_fetchPc_preOutput_ready;
wire [31:0] IBusSimplePlugin_fetchPc_preOutput_payload;
wire _zz_85_;
wire IBusSimplePlugin_fetchPc_output_valid;
wire IBusSimplePlugin_fetchPc_output_ready;
wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusSimplePlugin_fetchPc_inc;
reg IBusSimplePlugin_fetchPc_propagatePc;
reg [31:0] IBusSimplePlugin_fetchPc_pc;
reg IBusSimplePlugin_fetchPc_samplePcNext;
reg _zz_86_;
wire IBusSimplePlugin_iBusRsp_stages_0_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_halt;
wire IBusSimplePlugin_iBusRsp_stages_0_inputSample;
wire IBusSimplePlugin_iBusRsp_stages_1_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
reg IBusSimplePlugin_iBusRsp_stages_1_halt;
wire IBusSimplePlugin_iBusRsp_stages_1_inputSample;
wire IBusSimplePlugin_iBusRsp_stages_2_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_2_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_2_halt;
wire IBusSimplePlugin_iBusRsp_stages_2_inputSample;
wire _zz_87_;
wire _zz_88_;
wire _zz_89_;
wire _zz_90_;
wire _zz_91_;
reg _zz_92_;
wire _zz_93_;
reg _zz_94_;
reg [31:0] _zz_95_;
reg IBusSimplePlugin_iBusRsp_readyForError;
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_raw;
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
wire IBusSimplePlugin_injector_decodeInput_valid;
wire IBusSimplePlugin_injector_decodeInput_ready;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
wire IBusSimplePlugin_injector_decodeInput_payload_isRvc;
reg _zz_96_;
reg [31:0] _zz_97_;
reg _zz_98_;
reg [31:0] _zz_99_;
reg _zz_100_;
reg IBusSimplePlugin_injector_nextPcCalc_valids_0;
reg IBusSimplePlugin_injector_nextPcCalc_valids_1;
reg IBusSimplePlugin_injector_nextPcCalc_0;
reg IBusSimplePlugin_injector_nextPcCalc_1;
reg IBusSimplePlugin_injector_nextPcCalc_2;
reg IBusSimplePlugin_injector_nextPcCalc_3;
reg IBusSimplePlugin_injector_decodeRemoved;
reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
wire IBusSimplePlugin_cmd_valid;
wire IBusSimplePlugin_cmd_ready;
wire [31:0] IBusSimplePlugin_cmd_payload_pc;
reg [2:0] IBusSimplePlugin_pendingCmd;
wire [2:0] IBusSimplePlugin_pendingCmdNext;
reg [2:0] IBusSimplePlugin_rspJoin_discardCounter;
wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid;
wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready;
wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
wire iBus_rsp_takeWhen_valid;
wire iBus_rsp_takeWhen_payload_error;
wire [31:0] iBus_rsp_takeWhen_payload_inst;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
wire IBusSimplePlugin_rspJoin_issueDetected;
wire IBusSimplePlugin_rspJoin_join_valid;
wire IBusSimplePlugin_rspJoin_join_ready;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
wire IBusSimplePlugin_rspJoin_join_payload_rsp_error;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
wire IBusSimplePlugin_rspJoin_join_payload_isRvc;
wire _zz_101_;
wire execute_DBusSimplePlugin_cmdSent;
reg [31:0] _zz_102_;
reg [3:0] _zz_103_;
wire [3:0] execute_DBusSimplePlugin_formalMask;
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire _zz_104_;
reg [31:0] _zz_105_;
wire _zz_106_;
reg [31:0] _zz_107_;
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
wire [1:0] CsrPlugin_mtvec_mode;
wire [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire [31:0] CsrPlugin_medeleg;
wire [31:0] CsrPlugin_mideleg;
wire _zz_108_;
wire _zz_109_;
wire _zz_110_;
reg CsrPlugin_interrupt;
reg [3:0] CsrPlugin_interruptCode /* verilator public */ ;
wire [1:0] CsrPlugin_interruptTargetPrivilege;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_done;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException;
wire [1:0] CsrPlugin_targetPrivilege;
wire [3:0] CsrPlugin_trapCause;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
reg [31:0] execute_CsrPlugin_readData;
wire execute_CsrPlugin_writeInstruction;
wire execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
reg [31:0] execute_CsrPlugin_writeData;
wire [11:0] execute_CsrPlugin_csrAddress;
wire [23:0] _zz_111_;
wire _zz_112_;
wire _zz_113_;
wire _zz_114_;
wire _zz_115_;
wire _zz_116_;
wire _zz_117_;
wire `AluCtrlEnum_defaultEncoding_type _zz_118_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_119_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_120_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_121_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_122_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_123_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_124_;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg writeBack_RegFilePlugin_regFileWrite_valid /* verilator public */ ;
wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ;
wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ;
reg _zz_125_;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_126_;
reg [31:0] _zz_127_;
wire _zz_128_;
reg [19:0] _zz_129_;
wire _zz_130_;
reg [19:0] _zz_131_;
reg [31:0] _zz_132_;
wire [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
reg execute_LightShifterPlugin_isActive;
wire execute_LightShifterPlugin_isShift;
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
wire [4:0] execute_LightShifterPlugin_amplitude;
wire [31:0] execute_LightShifterPlugin_shiftInput;
wire execute_LightShifterPlugin_done;
reg [31:0] _zz_133_;
reg _zz_134_;
reg _zz_135_;
wire _zz_136_;
reg _zz_137_;
reg [4:0] _zz_138_;
wire execute_BranchPlugin_eq;
wire [2:0] _zz_139_;
reg _zz_140_;
reg _zz_141_;
wire [31:0] execute_BranchPlugin_branch_src1;
wire _zz_142_;
reg [10:0] _zz_143_;
wire _zz_144_;
reg [19:0] _zz_145_;
wire _zz_146_;
reg [18:0] _zz_147_;
reg [31:0] _zz_148_;
wire [31:0] execute_BranchPlugin_branch_src2;
wire [31:0] execute_BranchPlugin_branchAdder;
reg DebugPlugin_firstCycle;
reg DebugPlugin_secondCycle;
reg DebugPlugin_resetIt;
reg DebugPlugin_haltIt;
reg DebugPlugin_stepIt;
reg DebugPlugin_isPipActive;
reg DebugPlugin_isPipActive_regNext;
wire DebugPlugin_isPipBusy;
reg DebugPlugin_haltedByBreak;
reg [31:0] DebugPlugin_busReadDataReg;
reg _zz_149_;
reg DebugPlugin_resetIt_regNext;
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
reg decode_to_execute_SRC_LESS_UNSIGNED;
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
reg [31:0] decode_to_execute_INSTRUCTION;
reg [31:0] execute_to_memory_INSTRUCTION;
reg [31:0] memory_to_writeBack_INSTRUCTION;
reg decode_to_execute_IS_CSR;
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
reg [31:0] decode_to_execute_RS1;
reg decode_to_execute_SRC_USE_SUB_LESS;
reg decode_to_execute_DO_EBREAK;
reg [31:0] decode_to_execute_RS2;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
reg decode_to_execute_MEMORY_ENABLE;
reg execute_to_memory_MEMORY_ENABLE;
reg memory_to_writeBack_MEMORY_ENABLE;
reg decode_to_execute_CSR_READ_OPCODE;
reg [31:0] decode_to_execute_SRC2;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
reg decode_to_execute_CSR_WRITE_OPCODE;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
reg [31:0] decode_to_execute_PC;
reg [31:0] execute_to_memory_PC;
reg [31:0] memory_to_writeBack_PC;
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
reg [31:0] decode_to_execute_SRC1;
reg execute_to_memory_BRANCH_DO;
reg [31:0] execute_to_memory_BRANCH_CALC;
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
reg decode_to_execute_REGFILE_WRITE_VALID;
reg execute_to_memory_REGFILE_WRITE_VALID;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
reg [2:0] _zz_150_;
`ifndef SYNTHESIS
reg [31:0] _zz_1__string;
reg [31:0] _zz_2__string;
reg [31:0] _zz_3__string;
reg [31:0] _zz_4__string;
reg [31:0] decode_ENV_CTRL_string;
reg [31:0] _zz_5__string;
reg [31:0] _zz_6__string;
reg [31:0] _zz_7__string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_8__string;
reg [71:0] _zz_9__string;
reg [71:0] _zz_10__string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_11__string;
reg [39:0] _zz_12__string;
reg [39:0] _zz_13__string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_14__string;
reg [63:0] _zz_15__string;
reg [63:0] _zz_16__string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_17__string;
reg [31:0] _zz_18__string;
reg [31:0] _zz_19__string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_22__string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_24__string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_30__string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_33__string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_35__string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_37__string;
reg [23:0] _zz_44__string;
reg [31:0] _zz_47__string;
reg [31:0] _zz_51__string;
reg [95:0] _zz_52__string;
reg [71:0] _zz_56__string;
reg [39:0] _zz_58__string;
reg [63:0] _zz_59__string;
reg [31:0] memory_ENV_CTRL_string;
reg [31:0] _zz_61__string;
reg [31:0] execute_ENV_CTRL_string;
reg [31:0] _zz_62__string;
reg [31:0] writeBack_ENV_CTRL_string;
reg [31:0] _zz_65__string;
reg [63:0] _zz_118__string;
reg [39:0] _zz_119__string;
reg [71:0] _zz_120__string;
reg [95:0] _zz_121__string;
reg [31:0] _zz_122__string;
reg [31:0] _zz_123__string;
reg [23:0] _zz_124__string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_ENV_CTRL_string;
reg [31:0] execute_to_memory_ENV_CTRL_string;
reg [31:0] memory_to_writeBack_ENV_CTRL_string;
`endif
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_154_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
assign _zz_155_ = (! execute_arbitration_isStuckByOthers);
assign _zz_156_ = (execute_arbitration_isValid && execute_DO_EBREAK);
assign _zz_157_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0);
assign _zz_158_ = (DebugPlugin_stepIt && _zz_76_);
assign _zz_159_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign _zz_160_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
assign _zz_161_ = (IBusSimplePlugin_fetchPc_preOutput_valid && IBusSimplePlugin_fetchPc_preOutput_ready);
assign _zz_162_ = debug_bus_cmd_payload_address[7 : 2];
assign _zz_163_ = writeBack_INSTRUCTION[13 : 12];
assign _zz_164_ = writeBack_INSTRUCTION[29 : 28];
assign _zz_165_ = execute_INSTRUCTION[13];
assign _zz_166_ = (_zz_84_ & (~ _zz_167_));
assign _zz_167_ = (_zz_84_ - (2'b01));
assign _zz_168_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)};
assign _zz_169_ = {29'd0, _zz_168_};
assign _zz_170_ = (IBusSimplePlugin_pendingCmd + _zz_172_);
assign _zz_171_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready);
assign _zz_172_ = {2'd0, _zz_171_};
assign _zz_173_ = iBus_rsp_valid;
assign _zz_174_ = {2'd0, _zz_173_};
assign _zz_175_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)));
assign _zz_176_ = {2'd0, _zz_175_};
assign _zz_177_ = _zz_111_[4 : 4];
assign _zz_178_ = _zz_111_[8 : 8];
assign _zz_179_ = _zz_111_[9 : 9];
assign _zz_180_ = _zz_111_[10 : 10];
assign _zz_181_ = _zz_111_[14 : 14];
assign _zz_182_ = _zz_111_[15 : 15];
assign _zz_183_ = _zz_111_[16 : 16];
assign _zz_184_ = _zz_111_[19 : 19];
assign _zz_185_ = _zz_111_[20 : 20];
assign _zz_186_ = _zz_111_[23 : 23];
assign _zz_187_ = execute_SRC_LESS;
assign _zz_188_ = (3'b100);
assign _zz_189_ = decode_INSTRUCTION[19 : 15];
assign _zz_190_ = decode_INSTRUCTION[31 : 20];
assign _zz_191_ = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]};
assign _zz_192_ = ($signed(_zz_193_) + $signed(_zz_197_));
assign _zz_193_ = ($signed(_zz_194_) + $signed(_zz_195_));
assign _zz_194_ = execute_SRC1;
assign _zz_195_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_196_ = (execute_SRC_USE_SUB_LESS ? _zz_198_ : _zz_199_);
assign _zz_197_ = {{30{_zz_196_[1]}}, _zz_196_};
assign _zz_198_ = (2'b01);
assign _zz_199_ = (2'b00);
assign _zz_200_ = (_zz_201_ >>> 1);
assign _zz_201_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
assign _zz_202_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_203_ = execute_INSTRUCTION[31 : 20];
assign _zz_204_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_205_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_206_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_207_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_208_ = execute_CsrPlugin_writeData[11 : 11];
assign _zz_209_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_210_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_211_ = 1'b1;
assign _zz_212_ = 1'b1;
assign _zz_213_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
assign _zz_214_ = (32'b00000000000000000010000000000000);
assign _zz_215_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000));
assign _zz_216_ = (32'b00000000000000000001000000000000);
assign _zz_217_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000));
assign _zz_218_ = _zz_113_;
assign _zz_219_ = _zz_115_;
assign _zz_220_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000000000));
assign _zz_221_ = (1'b0);
assign _zz_222_ = (((decode_INSTRUCTION & _zz_225_) == (32'b00000000000000000000000000010000)) != (1'b0));
assign _zz_223_ = (_zz_117_ != (1'b0));
assign _zz_224_ = {(_zz_226_ != (1'b0)),{(_zz_227_ != _zz_228_),{_zz_229_,{_zz_230_,_zz_231_}}}};
assign _zz_225_ = (32'b00000000000000000000000000010000);
assign _zz_226_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000));
assign _zz_227_ = ((decode_INSTRUCTION & (32'b00010000000000000011000001010000)) == (32'b00000000000000000000000001010000));
assign _zz_228_ = (1'b0);
assign _zz_229_ = ({(_zz_232_ == _zz_233_),(_zz_234_ == _zz_235_)} != (2'b00));
assign _zz_230_ = (_zz_114_ != (1'b0));
assign _zz_231_ = {(_zz_236_ != (1'b0)),{(_zz_237_ != _zz_238_),{_zz_239_,{_zz_240_,_zz_241_}}}};
assign _zz_232_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000));
assign _zz_233_ = (32'b00000000000000000001000001010000);
assign _zz_234_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000));
assign _zz_235_ = (32'b00000000000000000010000001010000);
assign _zz_236_ = ((decode_INSTRUCTION & (32'b00000000000100000011000001010000)) == (32'b00000000000000000000000001010000));
assign _zz_237_ = {_zz_117_,_zz_116_};
assign _zz_238_ = (2'b00);
assign _zz_239_ = ({(_zz_242_ == _zz_243_),_zz_116_} != (2'b00));
assign _zz_240_ = ({_zz_244_,{_zz_245_,_zz_246_}} != (3'b000));
assign _zz_241_ = {({_zz_247_,_zz_248_} != (4'b0000)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}};
assign _zz_242_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100));
assign _zz_243_ = (32'b00000000000000000000000000000100);
assign _zz_244_ = ((decode_INSTRUCTION & _zz_254_) == (32'b00000000000000000000000001000000));
assign _zz_245_ = (_zz_255_ == _zz_256_);
assign _zz_246_ = (_zz_257_ == _zz_258_);
assign _zz_247_ = (_zz_259_ == _zz_260_);
assign _zz_248_ = {_zz_261_,{_zz_262_,_zz_263_}};
assign _zz_249_ = {_zz_113_,{_zz_264_,_zz_265_}};
assign _zz_250_ = (5'b00000);
assign _zz_251_ = ({_zz_266_,_zz_267_} != (2'b00));
assign _zz_252_ = (_zz_268_ != _zz_269_);
assign _zz_253_ = {_zz_270_,{_zz_271_,_zz_272_}};
assign _zz_254_ = (32'b00000000000000000000000001000100);
assign _zz_255_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110000));
assign _zz_256_ = (32'b01000000000000000000000000110000);
assign _zz_257_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100));
assign _zz_258_ = (32'b00000000000000000010000000010000);
assign _zz_259_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100));
assign _zz_260_ = (32'b00000000000000000000000000000000);
assign _zz_261_ = ((decode_INSTRUCTION & _zz_273_) == (32'b00000000000000000000000000000000));
assign _zz_262_ = _zz_112_;
assign _zz_263_ = (_zz_274_ == _zz_275_);
assign _zz_264_ = _zz_115_;
assign _zz_265_ = {_zz_276_,{_zz_277_,_zz_278_}};
assign _zz_266_ = (_zz_279_ == _zz_280_);
assign _zz_267_ = (_zz_281_ == _zz_282_);
assign _zz_268_ = (_zz_283_ == _zz_284_);
assign _zz_269_ = (1'b0);
assign _zz_270_ = ({_zz_285_,_zz_286_} != (2'b00));
assign _zz_271_ = (_zz_287_ != _zz_288_);
assign _zz_272_ = {_zz_289_,{_zz_290_,_zz_291_}};
assign _zz_273_ = (32'b00000000000000000000000000011000);
assign _zz_274_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
assign _zz_275_ = (32'b00000000000000000001000000000000);
assign _zz_276_ = ((decode_INSTRUCTION & _zz_292_) == (32'b00000000000000000001000000010000));
assign _zz_277_ = (_zz_293_ == _zz_294_);
assign _zz_278_ = _zz_114_;
assign _zz_279_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000));
assign _zz_280_ = (32'b00000000000000000000000001000000);
assign _zz_281_ = (decode_INSTRUCTION & (32'b00000000000100000011000001000000));
assign _zz_282_ = (32'b00000000000000000000000001000000);
assign _zz_283_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
assign _zz_284_ = (32'b00000000000000000101000000010000);
assign _zz_285_ = (_zz_295_ == _zz_296_);
assign _zz_286_ = (_zz_297_ == _zz_298_);
assign _zz_287_ = {_zz_299_,_zz_300_};
assign _zz_288_ = (2'b00);
assign _zz_289_ = ({_zz_301_,_zz_302_} != (2'b00));
assign _zz_290_ = (_zz_303_ != _zz_304_);
assign _zz_291_ = {_zz_305_,_zz_306_};
assign _zz_292_ = (32'b00000000000000000001000000010000);
assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
assign _zz_294_ = (32'b00000000000000000010000000010000);
assign _zz_295_ = (decode_INSTRUCTION & (32'b01000000000000000011000001010100));
assign _zz_296_ = (32'b01000000000000000001000000010000);
assign _zz_297_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
assign _zz_298_ = (32'b00000000000000000001000000010000);
assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000));
assign _zz_300_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000));
assign _zz_301_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000));
assign _zz_302_ = _zz_113_;
assign _zz_303_ = {_zz_113_,{(_zz_307_ == _zz_308_),(_zz_309_ == _zz_310_)}};
assign _zz_304_ = (3'b000);
assign _zz_305_ = ({(_zz_311_ == _zz_312_),{_zz_313_,_zz_314_}} != (3'b000));
assign _zz_306_ = (_zz_112_ != (1'b0));
assign _zz_307_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000));
assign _zz_308_ = (32'b00000000000000000001000000000000);
assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000));
assign _zz_310_ = (32'b00000000000000000010000000000000);
assign _zz_311_ = (decode_INSTRUCTION & (32'b00000000000000000100000000000100));
assign _zz_312_ = (32'b00000000000000000100000000000000);
assign _zz_313_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100));
assign _zz_314_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000100)) == (32'b00000000000000000001000000000000));
always @ (posedge toplevel_io_mainClk) begin
if(_zz_40_) begin
RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data;
end
end
always @ (posedge toplevel_io_mainClk) begin
if(_zz_211_) begin
_zz_152_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @ (posedge toplevel_io_mainClk) begin
if(_zz_212_) begin
_zz_153_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (
.io_push_valid(iBus_rsp_takeWhen_valid),
.io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready),
.io_push_payload_error(iBus_rsp_takeWhen_payload_error),
.io_push_payload_inst(iBus_rsp_takeWhen_payload_inst),
.io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
.io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready),
.io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error),
.io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst),
.io_flush(_zz_151_),
.io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy),
.toplevel_io_mainClk(toplevel_io_mainClk),
.toplevel_resetCtrl_systemReset(toplevel_resetCtrl_systemReset)
);
`ifndef SYNTHESIS
always @(*) begin
case(_zz_1_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET";
default : _zz_1__string = "????";
endcase
end
always @(*) begin
case(_zz_2_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET";
default : _zz_2__string = "????";
endcase
end
always @(*) begin
case(_zz_3_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET";
default : _zz_3__string = "????";
endcase
end
always @(*) begin
case(_zz_4_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET";
default : _zz_4__string = "????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET";
default : decode_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_5_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET";
default : _zz_5__string = "????";
endcase
end
always @(*) begin
case(_zz_6_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET";
default : _zz_6__string = "????";
endcase
end
always @(*) begin
case(_zz_7_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET";
default : _zz_7__string = "????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_8_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 ";
default : _zz_8__string = "?????????";
endcase
end
always @(*) begin
case(_zz_9_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9__string = "SRA_1 ";
default : _zz_9__string = "?????????";
endcase
end
always @(*) begin
case(_zz_10_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10__string = "SRA_1 ";
default : _zz_10__string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 ";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_11_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_11__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_11__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_11__string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_11__string = "SRC1 ";
default : _zz_11__string = "?????";
endcase
end
always @(*) begin
case(_zz_12_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_12__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_12__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_12__string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_12__string = "SRC1 ";
default : _zz_12__string = "?????";
endcase
end
always @(*) begin
case(_zz_13_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13__string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_13__string = "SRC1 ";
default : _zz_13__string = "?????";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_14_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_14__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_14__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_14__string = "BITWISE ";
default : _zz_14__string = "????????";
endcase
end
always @(*) begin
case(_zz_15_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_15__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_15__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_15__string = "BITWISE ";
default : _zz_15__string = "????????";
endcase
end
always @(*) begin
case(_zz_16_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_16__string = "BITWISE ";
default : _zz_16__string = "????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_17_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_17__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_17__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_17__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_17__string = "JALR";
default : _zz_17__string = "????";
endcase
end
always @(*) begin
case(_zz_18_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR";
default : _zz_18__string = "????";
endcase
end
always @(*) begin
case(_zz_19_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_19__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_19__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_19__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_19__string = "JALR";
default : _zz_19__string = "????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_22_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_22__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_22__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_22__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_22__string = "JALR";
default : _zz_22__string = "????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_24_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 ";
default : _zz_24__string = "?????????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_30_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_30__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_30__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_30__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_30__string = "PC ";
default : _zz_30__string = "???";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_33_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_33__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_33__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_33__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_33__string = "URS1 ";
default : _zz_33__string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_35_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_35__string = "BITWISE ";
default : _zz_35__string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 ";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_37_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37__string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_37__string = "SRC1 ";
default : _zz_37__string = "?????";
endcase
end
always @(*) begin
case(_zz_44_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_44__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_44__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_44__string = "PC ";
default : _zz_44__string = "???";
endcase
end
always @(*) begin
case(_zz_47_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_47__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_47__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_47__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_47__string = "JALR";
default : _zz_47__string = "????";
endcase
end
always @(*) begin
case(_zz_51_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_51__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_51__string = "XRET";
default : _zz_51__string = "????";
endcase
end
always @(*) begin
case(_zz_52_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_52__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_52__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_52__string = "URS1 ";
default : _zz_52__string = "????????????";
endcase
end
always @(*) begin
case(_zz_56_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_56__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_56__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_56__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_56__string = "SRA_1 ";
default : _zz_56__string = "?????????";
endcase
end
always @(*) begin
case(_zz_58_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_58__string = "SRC1 ";
default : _zz_58__string = "?????";
endcase
end
always @(*) begin
case(_zz_59_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_59__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_59__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_59__string = "BITWISE ";
default : _zz_59__string = "????????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET";
default : memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_61_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_61__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_61__string = "XRET";
default : _zz_61__string = "????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET";
default : execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_62_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_62__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_62__string = "XRET";
default : _zz_62__string = "????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET";
default : writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_65_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_65__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_65__string = "XRET";
default : _zz_65__string = "????";
endcase
end
always @(*) begin
case(_zz_118_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_118__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_118__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_118__string = "BITWISE ";
default : _zz_118__string = "????????";
endcase
end
always @(*) begin
case(_zz_119_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_119__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_119__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_119__string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_119__string = "SRC1 ";
default : _zz_119__string = "?????";
endcase
end
always @(*) begin
case(_zz_120_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_120__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_120__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_120__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_120__string = "SRA_1 ";
default : _zz_120__string = "?????????";
endcase
end
always @(*) begin
case(_zz_121_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_121__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_121__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_121__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_121__string = "URS1 ";
default : _zz_121__string = "????????????";
endcase
end
always @(*) begin
case(_zz_122_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_122__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_122__string = "XRET";
default : _zz_122__string = "????";
endcase
end
always @(*) begin
case(_zz_123_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_123__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_123__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_123__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_123__string = "JALR";
default : _zz_123__string = "????";
endcase
end
always @(*) begin
case(_zz_124_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_124__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_124__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_124__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_124__string = "PC ";
default : _zz_124__string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 ";