{"payload":{"header_redesign_enabled":false,"results":[{"id":"245350326","archived":false,"color":"#b2b7f8","followers":73,"has_funding_file":false,"hl_name":"lekgolo167/enxor-logic-analyzer","hl_trunc_description":"FPGA Logic Analyzer and GUI","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":245350326,"name":"enxor-logic-analyzer","owner_id":30761500,"owner_login":"lekgolo167","updated_at":"2022-12-29T03:43:23.322Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":52,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Alekgolo167%252Fenxor-logic-analyzer%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/lekgolo167/enxor-logic-analyzer/star":{"post":"LDcD15oGeg-ioVuKJugXXR6Jk_kAxFhbFbjTt3DmD9LuIhtGDsoDM-9Q0aV9QMMTv9q3Umj0Ln9eL4A4g9m9oQ"},"/lekgolo167/enxor-logic-analyzer/unstar":{"post":"U4mL9zf3hZhbWknzZIn4Or_oTIgmnXATDFCbqohQ_jRcJJedvNzM0piTJxG2f3weZCF7hrWzg4IG_cXSTAzw4A"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"N_cThZcuzekE_LcS7tkUHxJ8QmMC6KCniitqFvlXVJaHk1oDj5ddzGAh3XwRGriBWr53qZi0Z8SvRLRIyV-yXA"}}},"title":"Repository search results"}