From 1258e9927992f3b217914af75a17daf12afe802b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 20:54:42 -0400 Subject: [PATCH] Add comment --- fault/system_verilog_target.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index fc3c915b..bbc030ad 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -282,6 +282,9 @@ def run(self, actions): print(f"Running command: {cmd}") assert not subprocess.call(cmd, cwd=self.directory, shell=True) if self.simulator == "vcs": + # VCS doesn't set the return code when a simulation exits with an + # error, so we check the result of stdout to see if "Error" is + # present result = subprocess.run("./simv", cwd=self.directory, shell=True, capture_output=True) assert not result.returncode, "Running vcs binary failed"