From 4295e38f6ce1b3c2f89f5f5fcd36efa15f541c63 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 09:13:18 -0700 Subject: [PATCH 01/19] Add basic support for poke/expect X --- fault/system_verilog_target.py | 46 ++++++++++++++++++--------------- tests/common.py | 8 ++++++ tests/test_setattr_interface.py | 24 +++++++++++++++++ 3 files changed, 57 insertions(+), 21 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index d56a427f..7ed77681 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -67,7 +67,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", if simulator is None: raise ValueError("Must specify simulator when using system-verilog" " target") - if simulator not in ["vcs", "ncsim"]: + if simulator not in {"vcs", "ncsim", "iverilog"}: raise ValueError(f"Unsupported simulator {simulator}") self.simulator = simulator self.timescale = timescale @@ -86,15 +86,27 @@ def make_name(self, port): name = verilog_name(port.name) return name - def make_poke(self, i, action): - name = self.make_name(action.port) - # For now we assume that verilog can handle big ints - value = action.value - if isinstance(action.port, m.SIntType) and value < 0: + def process_value(self, port, value): + if isinstance(port, m.SIntType) and value < 0: # Handle sign extension for verilator since it expects and # unsigned c type - port_len = len(action.port) + port_len = len(port) value = BitVector(value, port_len).as_uint() + elif value is fault.UnknownValue: + value = "'X" + elif isinstance(value, actions.Peek): + if isinstance(value.port, fault.WrappedVerilogInternalPort): + value = f"dut.{value.port.path}" + else: + value = f"{value.port.name}" + elif isinstance(value, PortWrapper): + value = f"dut.{value.select_path.system_verilog_path}" + return value + + def make_poke(self, i, action): + name = self.make_name(action.port) + # For now we assume that verilog can handle big ints + value = self.process_value(action.port, action.value) return [f"{name} = {value};", f"#{self.clock_step_delay}"] def make_print(self, i, action): @@ -139,19 +151,7 @@ def make_expect(self, i, action): debug_name = name else: debug_name = action.port.name - value = action.value - if isinstance(value, actions.Peek): - if isinstance(value.port, fault.WrappedVerilogInternalPort): - value = f"dut.{value.port.path}" - else: - value = f"{value.port.name}" - elif isinstance(value, PortWrapper): - value = f"dut.{value.select_path.system_verilog_path}" - elif isinstance(action.port, m.SIntType) and value < 0: - # Handle sign extension for verilator since it expects and - # unsigned c type - port_len = len(action.port) - value = BitVector(value, port_len).as_uint() + value = self.process_value(action.port, action.value) return [f"if ({name} != {value}) $error(\"Failed on action={i}" f" checking port {debug_name}. Expected %x, got %x\"" @@ -246,10 +246,14 @@ def run(self, actions): cmd = f"""\ irun -top {self.circuit_name}_tb -timescale {self.timescale} -access +rwc -notimingchecks -input {cmd_file} {test_bench_file} {self.verilog_file} {verilog_libraries} """ # nopep8 - else: + elif self.simulator == "vcs": cmd = f"""\ vcs -sverilog -full64 +v2k -timescale={self.timescale} -LDFLAGS -Wl,--no-as-needed {test_bench_file} {self.verilog_file} {verilog_libraries} """ # nopep8 + elif self.simulator == "iverilog": + cmd = f"iverilog {test_bench_file} {self.verilog_file}" + else: + raise NotImplementedError(self.simulator) print(f"Running command: {cmd}") assert not subprocess.call(cmd, cwd=self.directory, shell=True) diff --git a/tests/common.py b/tests/common.py index c29149c4..4a6c7605 100644 --- a/tests/common.py +++ b/tests/common.py @@ -70,3 +70,11 @@ def definition(io): # [io.a + io.b, io.a - io.b, io.a * io.b, io.a / io.b], opcode) # use arbitrary fourth op [io.a + io.b, io.a - io.b, io.a * io.b, io.b - io.a], opcode) + + +class AndCircuit(m.Circuit): + IO = ["I0", m.In(m.Bit), "I1", m.In(m.Bit), "O", m.Out(m.Bit)] + + @classmethod + def definition(io): + io.O <= io.I0 & io.I1 diff --git a/tests/test_setattr_interface.py b/tests/test_setattr_interface.py index 1daf2347..f64a24b5 100644 --- a/tests/test_setattr_interface.py +++ b/tests/test_setattr_interface.py @@ -1,8 +1,10 @@ import common import tempfile +import fault from fault import Tester import shutil import random +import pytest def pytest_generate_tests(metafunc): @@ -12,6 +14,8 @@ def pytest_generate_tests(metafunc): targets.append(("system-verilog", "ncsim")) if shutil.which("vcs"): targets.append(("system-verilog", "vcs")) + if shutil.which("iverilog"): + targets.append(("system-verilog", "iverilog")) metafunc.parametrize("target,simulator", targets) @@ -113,3 +117,23 @@ def test_setattr_tuple(target, simulator): tester.circuit.O.a.expect(5) tester.circuit.O.b.expect(11) run_test(target, simulator, tester) + + +def test_setattr_x(target, simulator): + if target == "verilator": + pytest.skip("X not support with Verilator") + circ = common.AndCircuit + tester = Tester(circ) + tester.circuit.I0 = 0 + tester.circuit.I1 = 1 + tester.eval() + tester.circuit.O.expect(0) + tester.circuit.I0 = fault.UnknownValue + tester.circuit.I1 = 1 + tester.eval() + tester.circuit.O.expect(0) + tester.circuit.I0 = fault.UnknownValue + tester.circuit.I1 = fault.UnknownValue + tester.eval() + tester.circuit.O.expect(fault.UnknownValue) + run_test(target, simulator, tester) From 396ed9b546b0f50891afd63088bc8b12e3cd6db7 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 09:15:18 -0700 Subject: [PATCH 02/19] Install iverilog on travis --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 117deb20..690fb69a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,6 +3,7 @@ addons: apt: packages: - verilator + - iverilog # python managed by conda until 3.7 available # python: # - '3.6' From 178eb4a8ea9b78377d488a885635a9c614100ea9 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 10:07:34 -0700 Subject: [PATCH 03/19] Add basic support for SV file io --- fault/system_verilog_target.py | 70 ++++++++++++++++++++++------------ tests/test_tester.py | 7 ++-- 2 files changed, 50 insertions(+), 27 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 7ed77681..502dc89f 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -72,6 +72,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.simulator = simulator self.timescale = timescale self.clock_step_delay = clock_step_delay + self.declarations = [] def make_name(self, port): if isinstance(port, SelectPath): @@ -101,6 +102,12 @@ def process_value(self, port, value): value = f"{value.port.name}" elif isinstance(value, PortWrapper): value = f"dut.{value.select_path.system_verilog_path}" + elif isinstance(value, actions.FileRead): + new_value = f"{value.file.name_without_ext}_in" + if value.file.chunk_size == 1: + # Assume that the user didn't want an array 1 byte, so unpack + new_value += "[0]" + value = new_value return value def make_poke(self, i, action): @@ -116,8 +123,9 @@ def make_print(self, i, action): return [f'$write("{action.format_str}"{ports});'] def make_loop(self, i, action): + self.declarations.append(f"integer {action.loop_var};") code = [] - code.append(f"for (int {action.loop_var} = 0;" + code.append(f"for ({action.loop_var} = 0;" f" {action.loop_var} < {action.n_iter};" f" {action.loop_var}++) begin") @@ -130,16 +138,36 @@ def make_loop(self, i, action): return code def make_file_open(self, i, action): - raise NotImplementedError() + if action.file.mode not in {"r", "w"}: + raise NotImplementedError(action.file.mode) + name = action.file.name_without_ext + self.declarations.append( + f"reg [7:0] {name}_in[0:{action.file.chunk_size - 1}];") + self.declarations.append(f"integer {name}_file;") + code = f"""\ +{name}_file = $fopen(\"{action.file.name}\", \"{action.file.mode}\"); +if (!{name}_file) $error("Could not open file {action.file.name}: %0d", {name}_file); +""" # noqa + return code.splitlines() def make_file_close(self, i, action): - raise NotImplementedError() + return [f"$fclose({action.file.name_without_ext}_file);"] def make_file_read(self, i, action): - raise NotImplementedError() + decl = f"integer __i;" + if decl not in self.declarations: + self.declarations.append(decl) + code = f"""\ +for (__i = 0; __i < {action.file.chunk_size}; __i++) begin + {action.file.name_without_ext}_in[__i] = $fgetc({action.file.name_without_ext}_file); +end +""" # noqa + return code.splitlines() def make_file_write(self, i, action): - raise NotImplementedError() + value = self.make_name(action.value) + return [f"$fwrite({action.file.name_without_ext}_file, \"%u\", " + f"{value});"] def make_expect(self, i, action): if value_utils.is_any(action.value): @@ -168,32 +196,27 @@ def make_step(self, i, action): code.append(f"#5 {name} ^= 1;") return code - @staticmethod - def generate_recursive_port_code(name, type_): - declarations = "" + def generate_recursive_port_code(self, name, type_): port_list = [] if isinstance(type_, m.ArrayKind): for j in range(type_.N): - result = SystemVerilogTarget.generate_port_code( + result = self.generate_port_code( name + "_" + str(j), type_.T ) - declarations += result[0] - port_list.extend(result[1]) + port_list.extend(result) elif isinstance(type_, m.TupleKind): for k, t in zip(type_.Ks, type_.Ts): - result = SystemVerilogTarget.generate_port_code( + result = self.generate_port_code( name + "_" + str(k), t ) - declarations += result[0] - port_list.extend(result[1]) - return declarations, port_list + port_list.extend(result) + return port_list - @staticmethod - def generate_port_code(name, type_): + def generate_port_code(self, name, type_): is_array_of_bits = isinstance(type_, m.ArrayKind) and \ not isinstance(type_.T, m.BitKind) if is_array_of_bits or isinstance(type_, m.TupleKind): - return SystemVerilogTarget.generate_recursive_port_code(name, type_) + return self.generate_recursive_port_code(name, type_) else: width_str = "" if isinstance(type_, m.ArrayKind) and \ @@ -205,16 +228,15 @@ def generate_port_code(name, type_): t = "reg" else: raise NotImplementedError() - return f" {t} {width_str}{name};\n", [f".{name}({name})"] + self.declarations.append(f" {t} {width_str}{name};\n") + return [f".{name}({name})"] def generate_code(self, actions): initial_body = "" - declarations = "" port_list = [] for name, type_ in self.circuit.IO.ports.items(): - result = SystemVerilogTarget.generate_port_code(name, type_) - declarations += result[0] - port_list.extend(result[1]) + result = self.generate_port_code(name, type_) + port_list.extend(result) for i, action in enumerate(actions): code = self.generate_action_code(i, action) @@ -222,7 +244,7 @@ def generate_code(self, actions): initial_body += f" {line}\n" src = src_tpl.format( - declarations=declarations, + declarations="\n".join(self.declarations), initial_body=initial_body, port_list=",\n ".join(port_list), circuit_name=self.circuit_name, diff --git a/tests/test_tester.py b/tests/test_tester.py index 8d3ed320..a49d6877 100644 --- a/tests/test_tester.py +++ b/tests/test_tester.py @@ -18,6 +18,9 @@ def pytest_generate_tests(metafunc): if shutil.which("vcs"): targets.append( ("system-verilog", "vcs")) + if shutil.which("iverilog"): + targets.append( + ("system-verilog", "iverilog")) metafunc.parametrize("target,simulator", targets) @@ -295,9 +298,6 @@ def test_tester_loop(target, simulator): def test_tester_file_io(target, simulator): - if target == "system-verilog": - import pytest - pytest.skip("File IO not yet implemented for system-verilog target") circ = common.TestByteCircuit tester = fault.Tester(circ) tester.zero_inputs() @@ -312,6 +312,7 @@ def test_tester_file_io(target, simulator): tester.file_close(file_in) tester.file_close(file_out) with tempfile.TemporaryDirectory() as _dir: + _dir = "build" with open(_dir + "/test_file_in.raw", "wb") as file: file.write(bytes([i for i in range(8)])) if target == "verilator": From 7bc1a752d9f7000a13479e81dc9c804b1513bc92 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 10:08:32 -0700 Subject: [PATCH 04/19] Remove debug dir --- tests/test_tester.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/test_tester.py b/tests/test_tester.py index a49d6877..eb2e845a 100644 --- a/tests/test_tester.py +++ b/tests/test_tester.py @@ -312,7 +312,6 @@ def test_tester_file_io(target, simulator): tester.file_close(file_in) tester.file_close(file_out) with tempfile.TemporaryDirectory() as _dir: - _dir = "build" with open(_dir + "/test_file_in.raw", "wb") as file: file.write(bytes([i for i in range(8)])) if target == "verilator": From f6328d0d965f18b56d4b1656b125b9c27694ef6e Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 11:41:55 -0700 Subject: [PATCH 05/19] Improve error logic for iverilog --- fault/system_verilog_target.py | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 502dc89f..55ce307f 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -12,6 +12,7 @@ src_tpl = """\ module {circuit_name}_tb; +integer __error_occurred = 0; {declarations} {circuit_name} dut ( @@ -20,7 +21,12 @@ initial begin {initial_body} - #20 $finish; + #20 begin + if (__error_occurred) + $stop; + else + $finish; + end; end endmodule @@ -181,9 +187,12 @@ def make_expect(self, i, action): debug_name = action.port.name value = self.process_value(action.port, action.value) - return [f"if ({name} != {value}) $error(\"Failed on action={i}" - f" checking port {debug_name}. Expected %x, got %x\"" - f", {value}, {name});"] + return f""" +if ({name} != {value}) begin + $error(\"Failed on action={i} checking port {debug_name}. Expected %x, got %x\" , {value}, {name}); + __error_occurred |= 1; +end +""".splitlines() # noqa def make_eval(self, i, action): # Eval implicit in SV simulations @@ -273,7 +282,7 @@ def run(self, actions): vcs -sverilog -full64 +v2k -timescale={self.timescale} -LDFLAGS -Wl,--no-as-needed {test_bench_file} {self.verilog_file} {verilog_libraries} """ # nopep8 elif self.simulator == "iverilog": - cmd = f"iverilog {test_bench_file} {self.verilog_file}" + cmd = f"iverilog -o {self.circuit_name}_tb {test_bench_file} {self.verilog_file}" else: raise NotImplementedError(self.simulator) @@ -282,3 +291,5 @@ def run(self, actions): if self.simulator == "vcs": print(f"Running command: {cmd}") assert not subprocess.call("./simv", cwd=self.directory, shell=True) + elif self.simulator == "iverilog": + assert not subprocess.call(f"vvp -N {self.circuit_name}_tb", cwd=self.directory, shell=True) From e6c150af0e4ec232e5d554774e37792cf026ab9c Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 12:44:35 -0700 Subject: [PATCH 06/19] Weird issue with writing out a NULL byte --- fault/system_verilog_target.py | 4 ++-- tests/test_tester.py | 12 ++++++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 55ce307f..90f9c8a9 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -172,7 +172,7 @@ def make_file_read(self, i, action): def make_file_write(self, i, action): value = self.make_name(action.value) - return [f"$fwrite({action.file.name_without_ext}_file, \"%u\", " + return [f"$fwrite({action.file.name_without_ext}_file, \"%c\", " f"{value});"] def make_expect(self, i, action): @@ -191,7 +191,7 @@ def make_expect(self, i, action): if ({name} != {value}) begin $error(\"Failed on action={i} checking port {debug_name}. Expected %x, got %x\" , {value}, {name}); __error_occurred |= 1; -end +end; """.splitlines() # noqa def make_eval(self, i, action): diff --git a/tests/test_tester.py b/tests/test_tester.py index eb2e845a..fb090483 100644 --- a/tests/test_tester.py +++ b/tests/test_tester.py @@ -302,7 +302,8 @@ def test_tester_file_io(target, simulator): tester = fault.Tester(circ) tester.zero_inputs() file_in = tester.file_open("test_file_in.raw", "r") - file_out = tester.file_open("test_file_out.raw", "w") + out_file = "test_file_out.raw" + file_out = tester.file_open(out_file, "w") loop = tester.loop(8) value = loop.file_read(file_in) loop.poke(circ.I, value) @@ -312,6 +313,8 @@ def test_tester_file_io(target, simulator): tester.file_close(file_in) tester.file_close(file_out) with tempfile.TemporaryDirectory() as _dir: + if os.path.exists(_dir + "/" + out_file): + os.remove(_dir + "/" + out_file) with open(_dir + "/test_file_in.raw", "wb") as file: file.write(bytes([i for i in range(8)])) if target == "verilator": @@ -319,4 +322,9 @@ def test_tester_file_io(target, simulator): else: tester.compile_and_run(target, directory=_dir, simulator=simulator) with open(_dir + "/test_file_out.raw", "rb") as file: - assert file.read(8) == bytes([i for i in range(8)]) + expected = bytes([i for i in range(8)]) + if simulator == "iverilog": + # iverilog doesn't support writing a NULL byte out using %c, so + # this first value is skipped + expected = expected[1:] + assert file.read(8) == expected From 1da1c026d6ef22a0d790752fd77f3556826a8687 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 12:59:31 -0700 Subject: [PATCH 07/19] Install newer version of iverilog --- .travis.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 690fb69a..ec57aac5 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,9 +1,11 @@ language: python addons: apt: + sources: + - team-electronics packages: - verilator - - iverilog + - iverilog-daily # python managed by conda until 3.7 available # python: # - '3.6' From d648fccbabf44078f3504c02d021f72ca3f35f41 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:02:38 -0700 Subject: [PATCH 08/19] Use sourceline for ppa --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index ec57aac5..fdba0bf0 100644 --- a/.travis.yml +++ b/.travis.yml @@ -2,7 +2,7 @@ language: python addons: apt: sources: - - team-electronics + - sourceline: 'ppa:team-electronics/ppa' packages: - verilator - iverilog-daily From 3df082a41e22c38cd035e8f4656e1d70e0e1f19b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:05:30 -0700 Subject: [PATCH 09/19] Try standard iverilog package name --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index fdba0bf0..4eb271c4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,7 +5,7 @@ addons: - sourceline: 'ppa:team-electronics/ppa' packages: - verilator - - iverilog-daily + - iverilog # python managed by conda until 3.7 available # python: # - '3.6' From bc4edfc5fa8d936e18085817514c5bd7e9b49e99 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:08:27 -0700 Subject: [PATCH 10/19] Use verilog package name --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 4eb271c4..ccb7b5f9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,7 +5,7 @@ addons: - sourceline: 'ppa:team-electronics/ppa' packages: - verilator - - iverilog + - verilog # python managed by conda until 3.7 available # python: # - '3.6' From ffb810e23eea5cd7e4b9d2d7e026444088f9502a Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:15:05 -0700 Subject: [PATCH 11/19] Skip iverilog on travis --- .travis.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index ccb7b5f9..117deb20 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,11 +1,8 @@ language: python addons: apt: - sources: - - sourceline: 'ppa:team-electronics/ppa' packages: - verilator - - verilog # python managed by conda until 3.7 available # python: # - '3.6' From e1d9f684f5a5475a45f13d4098c329f4e85dc247 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:19:46 -0700 Subject: [PATCH 12/19] Install iverilog-daily through standard code path --- .travis.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.travis.yml b/.travis.yml index 117deb20..9b15868f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,6 +6,11 @@ addons: # python managed by conda until 3.7 available # python: # - '3.6' +before_install: +- sudo add-apt-repository ppa:team-electronics/ppa +- sudo apt-get update +- sudo apt-get install iverilog-daily + install: # install conda for py 3.7 - wget http://repo.continuum.io/miniconda/Miniconda-latest-Linux-x86_64.sh -O miniconda.sh From 6299ff93fe3e42ad2b3174ebc2a0e169f7cf46cf Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:22:00 -0700 Subject: [PATCH 13/19] Fix style --- fault/system_verilog_target.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 90f9c8a9..61176113 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -282,7 +282,7 @@ def run(self, actions): vcs -sverilog -full64 +v2k -timescale={self.timescale} -LDFLAGS -Wl,--no-as-needed {test_bench_file} {self.verilog_file} {verilog_libraries} """ # nopep8 elif self.simulator == "iverilog": - cmd = f"iverilog -o {self.circuit_name}_tb {test_bench_file} {self.verilog_file}" + cmd = f"iverilog -o {self.circuit_name}_tb {test_bench_file} {self.verilog_file}" # noqa else: raise NotImplementedError(self.simulator) @@ -292,4 +292,5 @@ def run(self, actions): print(f"Running command: {cmd}") assert not subprocess.call("./simv", cwd=self.directory, shell=True) elif self.simulator == "iverilog": - assert not subprocess.call(f"vvp -N {self.circuit_name}_tb", cwd=self.directory, shell=True) + assert not subprocess.call(f"vvp -N {self.circuit_name}_tb", + cwd=self.directory, shell=True) From b387fe9859d9264c7c4c2f5a208302aecb3c8b52 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:22:54 -0700 Subject: [PATCH 14/19] Add -y flag --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 9b15868f..22159de6 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,7 +7,7 @@ addons: # python: # - '3.6' before_install: -- sudo add-apt-repository ppa:team-electronics/ppa +- sudo add-apt-repository -y ppa:team-electronics/ppa - sudo apt-get update - sudo apt-get install iverilog-daily From e003c2922beed7b00ad5bad0f4b8b5d1086f95cc Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:23:45 -0700 Subject: [PATCH 15/19] Try dist: xenial --- .travis.yml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index 22159de6..2a09a48e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,15 +1,14 @@ +dist: xenial + language: python addons: apt: packages: - verilator + - iverilog # python managed by conda until 3.7 available # python: # - '3.6' -before_install: -- sudo add-apt-repository -y ppa:team-electronics/ppa -- sudo apt-get update -- sudo apt-get install iverilog-daily install: # install conda for py 3.7 From e115690f0ca04d0c5fb0fe89e0bb71b724a6d599 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 13:31:45 -0700 Subject: [PATCH 16/19] Skip iverilog --- .travis.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 2a09a48e..77f039b4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,11 +1,8 @@ -dist: xenial - language: python addons: apt: packages: - verilator - - iverilog # python managed by conda until 3.7 available # python: # - '3.6' From 75e55f7d5938ce404496a14cdcf83bf4741834f6 Mon Sep 17 00:00:00 2001 From: Keyi Zhang Date: Wed, 15 May 2019 21:37:58 -0700 Subject: [PATCH 17/19] add number of cycles to ncsim --- fault/system_verilog_target.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 61176113..bcf36ed0 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -32,19 +32,12 @@ endmodule """ -ncsim_cmd_string = """\ -database -open -vcd vcddb -into verilog.vcd -default -timescale ps -probe -create -all -vcd -depth all -run 10000ns -quit -""" - class SystemVerilogTarget(VerilogTarget): def __init__(self, circuit, circuit_name=None, directory="build/", skip_compile=False, magma_output="coreir-verilog", magma_opts={}, include_verilog_libraries=[], simulator=None, - timescale="1ns/1ns", clock_step_delay=5): + timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000): """ circuit: a magma circuit @@ -78,6 +71,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.simulator = simulator self.timescale = timescale self.clock_step_delay = clock_step_delay + self.num_cycle = num_cycle self.declarations = [] def make_name(self, port): @@ -272,6 +266,11 @@ def run(self, actions): self.include_verilog_libraries) cmd_file = Path(f"{self.circuit_name}_cmd.tcl") if self.simulator == "ncsim": + ncsim_cmd_string = f"""\ +database -open -vcd vcddb -into verilog.vcd -default -timescale ps +probe -create -all -vcd -depth all +run {self.num_cycle}ns +quit""" with open(self.directory / cmd_file, "w") as f: f.write(ncsim_cmd_string) cmd = f"""\ From be24833328bbbe3e0c5346671cf063b1d2b7477f Mon Sep 17 00:00:00 2001 From: Keyi Zhang Date: Fri, 17 May 2019 16:37:46 -0700 Subject: [PATCH 18/19] add more ncsim options --- fault/system_verilog_target.py | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index bcf36ed0..8296b4bd 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -37,7 +37,8 @@ class SystemVerilogTarget(VerilogTarget): def __init__(self, circuit, circuit_name=None, directory="build/", skip_compile=False, magma_output="coreir-verilog", magma_opts={}, include_verilog_libraries=[], simulator=None, - timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000): + timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000, + dump_vcd=True, no_warning=False): """ circuit: a magma circuit @@ -72,6 +73,8 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.timescale = timescale self.clock_step_delay = clock_step_delay self.num_cycle = num_cycle + self.dump_vcd = dump_vcd + self.no_warning = no_warning self.declarations = [] def make_name(self, port): @@ -266,15 +269,24 @@ def run(self, actions): self.include_verilog_libraries) cmd_file = Path(f"{self.circuit_name}_cmd.tcl") if self.simulator == "ncsim": - ncsim_cmd_string = f"""\ + if self.dump_vcd: + vcd_command = """ database -open -vcd vcddb -into verilog.vcd -default -timescale ps -probe -create -all -vcd -depth all +probe -create -all -vcd -depth all""" + else: + vcd_command = "" + ncsim_cmd_string = f"""\ +{vcd_command} run {self.num_cycle}ns quit""" + if self.no_warning: + warning = "-neverwarn" + else: + warning = "" with open(self.directory / cmd_file, "w") as f: f.write(ncsim_cmd_string) cmd = f"""\ -irun -top {self.circuit_name}_tb -timescale {self.timescale} -access +rwc -notimingchecks -input {cmd_file} {test_bench_file} {self.verilog_file} {verilog_libraries} +irun -top {self.circuit_name}_tb -timescale {self.timescale} -access +rwc -notimingchecks {warning} -input {cmd_file} {test_bench_file} {self.verilog_file} {verilog_libraries} """ # nopep8 elif self.simulator == "vcs": cmd = f"""\ From 15a748441bba4d24acfa4652284127a7bf801fd5 Mon Sep 17 00:00:00 2001 From: Keyi Zhang Date: Sat, 18 May 2019 23:00:46 -0700 Subject: [PATCH 19/19] fix typo --- fault/system_verilog_target.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 8296b4bd..0ae7bac9 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -37,7 +37,7 @@ class SystemVerilogTarget(VerilogTarget): def __init__(self, circuit, circuit_name=None, directory="build/", skip_compile=False, magma_output="coreir-verilog", magma_opts={}, include_verilog_libraries=[], simulator=None, - timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000, + timescale="1ns/1ns", clock_step_delay=5, num_cycles=10000, dump_vcd=True, no_warning=False): """ circuit: a magma circuit @@ -72,7 +72,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.simulator = simulator self.timescale = timescale self.clock_step_delay = clock_step_delay - self.num_cycle = num_cycle + self.num_cycles = num_cycles self.dump_vcd = dump_vcd self.no_warning = no_warning self.declarations = [] @@ -277,7 +277,7 @@ def run(self, actions): vcd_command = "" ncsim_cmd_string = f"""\ {vcd_command} -run {self.num_cycle}ns +run {self.num_cycles}ns quit""" if self.no_warning: warning = "-neverwarn"