From 494c06074d08b7f02cfd9b5eaaff6195751cebce Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 5 Jun 2019 16:28:17 -0700 Subject: [PATCH] Fixup logic --- fault/system_verilog_target.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index fd49fea7..d2c451f6 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -286,8 +286,8 @@ def run(self, actions, power_args={}): if check_timestamp: new_stat_result = os.stat(tb_file) new_times = (new_stat_result.st_atime, new_stat_result.st_mtime) - if new_times[1] <= old_times[1]: - new_times = (new_times[0], old_times[1] + 1) + if old_times[0] <= new_times[0] or new_times[1] <= old_times[1]: + new_times = (old_times[0] + 1, old_times[1] + 1) os.utime(tb_file, times=new_times) verilog_libraries = " ".join(str(x) for x in self.include_verilog_libraries)