From 78d3b1d4ab6cfd1dbc94a963b91ff2426a24665f Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 24 May 2019 15:04:39 -0700 Subject: [PATCH] Wrap expression in parens --- fault/system_verilog_target.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 9550cdce..f16b9e12 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -108,7 +108,7 @@ def process_value(self, port, value): new_value += "[0]" value = new_value elif isinstance(value, expression.Expression): - value = self.compile_expression(port, value) + value = f"({self.compile_expression(port, value)})" return value def compile_expression(self, port, value):