diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
index 9fa8c340..78720782 100644
--- a/fault/system_verilog_target.py
+++ b/fault/system_verilog_target.py
@@ -101,7 +101,7 @@ def make_print(self, i, action):
         ports = ", ".join(f"{self.make_name(port)}" for port in action.ports)
         if ports:
             ports = ", " + ports
-        return [f'$display("{action.format_str}"{ports});']
+        return [f'$write("{action.format_str}"{ports});']
 
     def make_expect(self, i, action):
         if value_utils.is_any(action.value):