From 7d087a6d7b390b493e1f8f380d277e79869bd79d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 May 2019 11:14:38 -0700 Subject: [PATCH 1/2] Fix logic for signed expect --- fault/verilator_target.py | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/fault/verilator_target.py b/fault/verilator_target.py index 558620aa..0497c0fe 100644 --- a/fault/verilator_target.py +++ b/fault/verilator_target.py @@ -112,6 +112,16 @@ def __init__(self, circuit, directory="build/", # works self.verilator_version = float(verilator_version.split()[1]) + def process_signed_values(self, port, value): + if isinstance(value, (int, BitVector)) and value < 0: + # Handle sign extension for verilator since it expects and unsigned + # c type + if isinstance(port, SelectPath): + port = port[-1] + port_len = len(port) + value = BitVector(value, port_len).as_uint() + return value + def make_poke(self, i, action): if self.verilator_version > 3.874: prefix = f"{self.circuit_name}" @@ -169,11 +179,7 @@ def make_poke(self, i, action): value = action.value if isinstance(value, actions.FileRead): value = f"*{value.file.name_without_ext}_in" - if isinstance(action.port, m.SIntType) and value < 0: - # Handle sign extension for verilator since it expects and - # unsigned c type - port_len = len(action.port) - value = BitVector(value, port_len).as_uint() + value = self.process_signed_values(action.port, value) result = [f"top->{name} = {value};"] # Hack to support verilator's semantics, need to set the register # mux values for expected behavior @@ -238,11 +244,7 @@ def make_expect(self, i, action): circuit_name = type(item.instance).name self.debug_includes.add(f"{circuit_name}") value = f"top->{prefix}->" + value.select_path.verilator_path - elif isinstance(action.port, m.SIntType) and value < 0: - # Handle sign extension for verilator since it expects and - # unsigned c type - port_len = len(action.port) - value = BitVector(value, port_len).as_uint() + value = self.process_signed_values(action.port, value) return [f"my_assert(top->{name}, {value}, " f"{i}, \"{debug_name}\");"] From 5405592ef646f28bbae3709fae8503f3bc7c6d1b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 May 2019 08:22:36 -0700 Subject: [PATCH 2/2] Update test for new line in print output --- tests/test_verilog_target.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/test_verilog_target.py b/tests/test_verilog_target.py index 2709e51f..7b6cb5dc 100644 --- a/tests/test_verilog_target.py +++ b/tests/test_verilog_target.py @@ -121,9 +121,9 @@ def test_target_clock(capfd, target, simulator): assert lines[-5] == "0", out assert lines[-4] == "1", out elif simulator == "vcs": + assert lines[-10] == "0", out assert lines[-9] == "0", out - assert lines[-8] == "0", out - assert lines[-7] == "1", out + assert lines[-8] == "1", out else: raise NotImplementedError(f"Unsupported simulator: {simulator}") @@ -148,7 +148,7 @@ def test_print_nested_arrays(capfd, target, simulator): if simulator == "ncsim": actual = "\n".join(out.splitlines()[-9 - 3: -3]) elif simulator == "vcs": - actual = "\n".join(out.splitlines()[-9 - 6: -6]) + actual = "\n".join(out.splitlines()[-9 - 7: -7]) else: raise NotImplementedError(f"Unsupported simulator: {simulator}") assert actual == """\ @@ -186,7 +186,7 @@ def test_print_double_nested_arrays(capfd, target, simulator): if simulator == "ncsim": actual = "\n".join(out.splitlines()[-18 - 3: -3]) elif simulator == "vcs": - actual = "\n".join(out.splitlines()[-18 - 6: -6]) + actual = "\n".join(out.splitlines()[-18 - 7: -7]) else: raise NotImplementedError(f"Unsupported simulator: {simulator}") assert actual == """\