diff --git a/jtag/compile.py b/jtag/compile.py
index f24854b..85772a4 100644
--- a/jtag/compile.py
+++ b/jtag/compile.py
@@ -601,10 +601,12 @@ def compile(file):
         regs_str += f"reg {width}{r};\n"
 
     case_str = ""
-    case_str += "case (state)\n"
-    for case, transitions in case_map.items():
-        case_str += "    "
-        case_str += f"{case}: "
+    # case_str += "case (state)\n"
+    for i, (case, transitions) in enumerate(case_map.items()):
+        # case_str += "    "
+        if i > 0:
+            case_str += "end else "
+        case_str += f"if (state == {case}) begin\n    "
         for transition in transitions:
             if transition != transitions[0]:
                 case_str += " else "
@@ -628,8 +630,9 @@ def compile(file):
 
             case_str += f"    end"
         case_str += "\n"
-    case_str += "endcase"
-    case_str = "   " + "\n    ".join(line for line in case_str.splitlines())
+    case_str += "end"
+    # case_str += "endcase"
+    case_str = "    " + "\n    ".join(line for line in case_str.splitlines())
 
     # Assumes first state is first key
 
@@ -656,7 +659,7 @@ def compile(file):
     end
 end
 always @(*) begin
-  {case_str}
+{case_str}
 end
 endmodule
     """
diff --git a/jtag/fsm.blif b/jtag/fsm.blif
index 5a200ba..4bfd9b3 100644
--- a/jtag/fsm.blif
+++ b/jtag/fsm.blif
@@ -7,34 +7,34 @@
 .names $true
 1
 .names $undef
+.gate SB_LUT4 I0=curr_state[1] I1=curr_state[2] I2=$false I3=$false O=$abc$2616$new_n19_
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
+.param LUT_INIT 0100
 .gate SB_LUT4 I0=tms I1=curr_state[0] I2=curr_state[1] I3=curr_state[2] O=next_state[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
 .param LUT_INIT 1100111100001010
-.gate SB_LUT4 I0=curr_state[0] I1=tms I2=curr_state[3] I3=$abc$773$new_n27_ O=next_state[3]
+.gate SB_LUT4 I0=curr_state[0] I1=tms I2=curr_state[3] I3=$abc$2616$new_n19_ O=next_state[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
 .param LUT_INIT 0011011111110000
-.gate SB_LUT4 I0=curr_state[1] I1=curr_state[2] I2=$false I3=$false O=$abc$773$new_n27_
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
-.param LUT_INIT 0100
-.gate SB_LUT4 I0=curr_state[0] I1=curr_state[3] I2=curr_state[1] I3=tms O=$abc$773$new_n29_
+.gate SB_LUT4 I0=curr_state[3] I1=curr_state[1] I2=curr_state[2] I3=tms O=$abc$2616$new_n24_
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
-.param LUT_INIT 1000111101110001
-.gate SB_LUT4 I0=tms I1=$abc$773$new_n29_ I2=curr_state[2] I3=$false O=next_state[1]
+.param LUT_INIT 1011001100001111
+.gate SB_LUT4 I0=tms I1=$abc$2616$new_n24_ I2=curr_state[0] I3=$false O=next_state[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
-.param LUT_INIT 11000101
-.gate SB_LUT4 I0=curr_state[3] I1=curr_state[1] I2=curr_state[2] I3=tms O=$abc$773$new_n31_
+.param LUT_INIT 11001010
+.gate SB_LUT4 I0=curr_state[0] I1=curr_state[3] I2=curr_state[1] I3=tms O=$abc$2616$new_n26_
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
-.param LUT_INIT 1011001100001111
-.gate SB_LUT4 I0=tms I1=$abc$773$new_n31_ I2=curr_state[0] I3=$false O=next_state[0]
+.param LUT_INIT 1000111101110001
+.gate SB_LUT4 I0=tms I1=$abc$2616$new_n26_ I2=curr_state[2] I3=$false O=next_state[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
-.param LUT_INIT 11001010
+.param LUT_INIT 11000101
 .gate SB_DFFS C=CLK D=next_state[0] Q=curr_state[0] S=RESET
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "fsm.v:10|/usr/local/bin/../share/yosys/ice40/cells_map.v:18"
diff --git a/jtag/fsm.txt b/jtag/fsm.txt
index ccd3613..551e52c 100644
--- a/jtag/fsm.txt
+++ b/jtag/fsm.txt
@@ -2280,20 +2280,20 @@
 000000000000000000
 .io_tile 0 4
 000000000000000000
+000100000000000000
 000000000000000000
+000000000000000001
+000000011000000000
 000000000000000000
+001000000000000000
 000000000000000000
 000000000000000000
+000100000000000000
+000000000000010010
+000000000000010000
 000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
+000000000000000001
+000000000000000010
 000000000000000000
 .logic_tile 1 4
 000000000000000000000000000000000000000000000000000000
@@ -2857,39 +2857,39 @@
 000000000000000000
 000000000000000000
 .io_tile 0 5
+000000000000000010
+000100000000000000
+000000011000000000
+000000001000000001
+000000000000010010
+000000000000110000
+001010000000000000
+000010010000000000
 000000000000000000
 000000000000000000
+000000000000000010
+000000000000110000
 000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
+000000000000000001
+000000000000000010
 000000000000000000
 .logic_tile 1 5
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
+000000000000001000000010011001101000101110100000000000
+000000000000000001000110000101111011001100110000000000
+101000000000001001100110001101011001110111000000000000
+001000000000001011000010011001111011010111000000000000
+000000000000000001100110000101100000000000000000000000
+000000000000000000000000001101100000000001000000000000
+000000000000000001100000010001000001000010010100000000
+000000000000000000000010001001001011000001011100000000
+000000000000001000000000000000000000000000000000000000
+000000000000001001000000000000000000000000000000000000
+000000000000000000000000000101000001000001010100000000
+000000000000000000000000001001001000000010011100000000
+000000000000000000000000001001111010101101000100000000
+000000000000000000000000001001011011101110001100000000
+010000000000000000000000001001101001010100110100000000
+010000000000000000000000000001111001011100111100000000
 .logic_tile 2 5
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
@@ -3435,25 +3435,25 @@
 000000000000000000
 000000000000000000
 .io_tile 0 6
+000000000000000010
+000100000000000000
 000000000000000000
+000000000000000001
+000000000000110010
+000000000000110000
+001100000000000000
 000000000000000000
 000000000000000000
+001000000000000000
 000000000000000000
 000000000000000000
 000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
+000000000000000001
+000001010000000000
 000000000000000000
 .logic_tile 1 6
 000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
+000000001100000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
@@ -4013,16 +4013,16 @@
 000000000000000000
 000000000000000000
 .io_tile 0 7
+010000000000000000
+001000000000000000
 000000000000000000
+000000000000000001
 000000000000000000
 000000000000000000
+001000000000000000
 000000000000000000
 000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
-000000000000000000
+000100000000000000
 000000000000000000
 000000000000000000
 000000000000000000
@@ -4055,8 +4055,8 @@
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000
+000010100000010000000000000000000000000000000000000000
+000001000000100000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
@@ -11510,20 +11510,20 @@
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 .io_tile 33 19
-000000000000000010
-000100000000000000
 000000000000000000
-000000000000000001
-000000000000110010
-000000000000010000
-001100000000000000
 000000000000000000
 000000000000000000
 000000000000000000
-100000000000000000
 000000000000000000
-000000011000000000
-000000000000000001
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
 000000000000000000
 000000000000000000
 .io_tile 0 20
@@ -12071,37 +12071,37 @@
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 .logic_tile 32 20
-000000000000000000000110000101101111101110100000000000
-000000000000000000000000001101111000001100110000000000
-101000000000001001100000011001101101110111000000000000
-001000000000000001000010001101011000010111000000000000
-000000000000001001100110011001100000000000000000000000
-000000000000000001000010000001000000000001000000000000
-000000000000001111100000010101000000000001010100000010
-000000000000000001000010001111001001000010011100000000
-000000000000000000000000010101000001000010010100000000
-000000000000000101000010101011001110000001011100000000
-000000000000000000000000000101011111101101000100000000
-000000000000000000000000001111101010101110001100000000
-000000000000000000000000010111001011010100110100000000
-000000000000000000000010101101111001011100111100000000
-010000000000000001100000000000000000000000000000000000
-110000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
 .io_tile 33 20
-000000000000000010
-000100000000000000
 000000000000000000
-000000000000000001
-000000000000010010
-000000000000110000
-001110000000011000
-000010010000000000
 000000000000000000
 000000000000000000
 000000000000000000
 000000000000000000
 000000000000000000
-000000000000000001
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
 000000000000000000
 000000000000000000
 .io_tile 0 21
@@ -12667,20 +12667,20 @@
 000000000000000000000000000000000000000000000000000000
 .io_tile 33 21
 000000000000000000
-000100000000000000
 000000000000000000
-000000000000000001
 000000000000000000
 000000000000000000
-001000000000000000
 000000000000000000
 000000000000000000
-000100000000000000
-000000000000110010
-000000000000010000
 000000000000000000
-000001010000000001
-000000000000000010
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
 000000000000000000
 .io_tile 0 22
 000000000000000000
@@ -13228,7 +13228,7 @@
 000000000000000000000000000000000000000000000000000000
 .logic_tile 32 22
 000000000000000000000000000000000000000000000000000000
-000010000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
@@ -13244,13 +13244,13 @@
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 .io_tile 33 22
-000010000000000010
-000000110000000000
 000000000000000000
-000000000000000001
-000000000000000010
-000000000000010000
-001000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
+000000000000000000
 000000000000000000
 000000000000000000
 000000000000000000
@@ -14968,7 +14968,7 @@
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
-000000000000000000010000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
 000000000000000000000000000000000000000000000000000000
@@ -19584,48 +19584,48 @@
 000000000000000000
 000000000000000000
 000000000000000000
-.sym 127484 $abc$773$new_n29_
-.sym 127485 $abc$773$new_n31_
-.sym 127486 $abc$773$new_n27_
-.sym 127487 curr_state[0]
-.sym 127488 curr_state[1]
-.sym 127489 curr_state[2]
-.sym 127490 curr_state[3]
-.sym 131948 RESET$2
-.sym 132103 tms$2
-.sym 132207 curr_state[0]
-.sym 132208 curr_state[3]
-.sym 132209 curr_state[1]
-.sym 132210 tms$2
-.sym 132213 curr_state[3]
-.sym 132214 curr_state[1]
-.sym 132215 curr_state[2]
-.sym 132216 tms$2
-.sym 132219 curr_state[1]
-.sym 132220 curr_state[2]
-.sym 132221 $false
-.sym 132222 $false
-.sym 132225 tms$2
-.sym 132226 $abc$773$new_n31_
-.sym 132227 curr_state[0]
-.sym 132228 $false
-.sym 132231 tms$2
-.sym 132232 $abc$773$new_n29_
-.sym 132233 curr_state[2]
-.sym 132234 $false
-.sym 132237 tms$2
-.sym 132238 curr_state[0]
-.sym 132239 curr_state[1]
-.sym 132240 curr_state[2]
-.sym 132243 curr_state[0]
-.sym 132244 tms$2
-.sym 132245 curr_state[3]
-.sym 132246 $abc$773$new_n27_
-.sym 132253 $true
-.sym 132254 CLK$2
-.sym 132255 RESET$2
-.sym 132256 CLK$2
-.sym 134771 curr_state[2]
-.sym 134801 curr_state[3]
-.sym 134834 curr_state[1]
-.sym 134861 curr_state[0]
+.sym 376 CLK$2
+.sym 383 curr_state[0]
+.sym 405 $abc$2616$new_n26_
+.sym 406 $abc$2616$new_n24_
+.sym 407 $abc$2616$new_n19_
+.sym 408 curr_state[1]
+.sym 410 curr_state[0]
+.sym 411 curr_state[2]
+.sym 412 curr_state[3]
+.sym 492 curr_state[2]
+.sym 497 curr_state[1]
+.sym 606 curr_state[3]
+.sym 609 RESET$2
+.sym 718 tms$2
+.sym 4414 curr_state[0]
+.sym 4415 curr_state[3]
+.sym 4416 curr_state[1]
+.sym 4417 tms$2
+.sym 4420 curr_state[3]
+.sym 4421 curr_state[1]
+.sym 4422 curr_state[2]
+.sym 4423 tms$2
+.sym 4426 curr_state[1]
+.sym 4427 curr_state[2]
+.sym 4428 $false
+.sym 4429 $false
+.sym 4432 tms$2
+.sym 4433 $abc$2616$new_n26_
+.sym 4434 curr_state[2]
+.sym 4435 $false
+.sym 4444 tms$2
+.sym 4445 $abc$2616$new_n24_
+.sym 4446 curr_state[0]
+.sym 4447 $false
+.sym 4450 tms$2
+.sym 4451 curr_state[0]
+.sym 4452 curr_state[1]
+.sym 4453 curr_state[2]
+.sym 4456 curr_state[0]
+.sym 4457 tms$2
+.sym 4458 curr_state[3]
+.sym 4459 $abc$2616$new_n19_
+.sym 4460 $true
+.sym 4461 CLK$2
+.sym 4462 RESET$2
diff --git a/jtag/fsm.v b/jtag/fsm.v
index 66c413f..436754d 100644
--- a/jtag/fsm.v
+++ b/jtag/fsm.v
@@ -16,88 +16,103 @@ always @(posedge CLK or posedge RESET) begin
     end
 end
 always @(*) begin
-     case (state)
-        15: if ((tms == 0)) begin
+    if (state == 15) begin
+        if ((tms == 0)) begin
             next_state = 12;
         end else begin
             next_state = 15;
         end
-        12: if ((tms == 1)) begin
+    end else if (state == 12) begin
+        if ((tms == 1)) begin
             next_state = 7;
         end else begin
             next_state = 12;
         end
-        7: if ((tms == 1)) begin
+    end else if (state == 7) begin
+        if ((tms == 1)) begin
             next_state = 4;
         end else begin
             next_state = 6;
         end
-        4: if ((tms == 1)) begin
+    end else if (state == 4) begin
+        if ((tms == 1)) begin
             next_state = 15;
         end else begin
             next_state = 14;
         end
-        6: if ((tms == 1)) begin
+    end else if (state == 6) begin
+        if ((tms == 1)) begin
             next_state = 1;
         end else begin
             next_state = 2;
         end
-        2: if ((tms == 1)) begin
+    end else if (state == 2) begin
+        if ((tms == 1)) begin
             next_state = 1;
         end else begin
             next_state = 2;
         end
-        1: if ((tms == 0)) begin
+    end else if (state == 1) begin
+        if ((tms == 0)) begin
             next_state = 3;
         end else begin
             next_state = 5;
         end
-        5: if ((tms == 1)) begin
+    end else if (state == 5) begin
+        if ((tms == 1)) begin
             next_state = 7;
         end else begin
             next_state = 12;
         end
-        3: if ((tms == 0)) begin
+    end else if (state == 3) begin
+        if ((tms == 0)) begin
             next_state = 3;
         end else begin
             next_state = 0;
         end
-        0: if ((tms == 0)) begin
+    end else if (state == 0) begin
+        if ((tms == 0)) begin
             next_state = 2;
         end else begin
             next_state = 5;
         end
-        14: if ((tms == 1)) begin
+    end else if (state == 14) begin
+        if ((tms == 1)) begin
             next_state = 9;
         end else begin
             next_state = 10;
         end
-        10: if ((tms == 1)) begin
+    end else if (state == 10) begin
+        if ((tms == 1)) begin
             next_state = 9;
         end else begin
             next_state = 10;
         end
-        9: if ((tms == 0)) begin
+    end else if (state == 9) begin
+        if ((tms == 0)) begin
             next_state = 11;
         end else begin
             next_state = 13;
         end
-        13: if ((tms == 1)) begin
+    end else if (state == 13) begin
+        if ((tms == 1)) begin
             next_state = 7;
         end else begin
             next_state = 12;
         end
-        11: if ((tms == 0)) begin
+    end else if (state == 11) begin
+        if ((tms == 0)) begin
             next_state = 11;
         end else begin
             next_state = 8;
         end
-        8: if ((tms == 0)) begin
+    end else if (state == 8) begin
+        if ((tms == 0)) begin
             next_state = 10;
         end else begin
             next_state = 13;
         end
-    endcase
+    end
 end
 endmodule
     
\ No newline at end of file
diff --git a/sdram/fsm.py b/sdram/fsm.py
index e55e6d0..c02b089 100644
--- a/sdram/fsm.py
+++ b/sdram/fsm.py
@@ -95,7 +95,7 @@ def refresh(self):
         refresh_cnt, rd_enable, wr_enable = yield REF_PRE, CMD_PALL
         refresh_cnt, rd_enable, wr_enable = yield REF_NOP1, CMD_NOP
         refresh_cnt, rd_enable, wr_enable = yield REF_REF, CMD_REF
-        for _ in range(8, -1, -1):
+        for _ in range(7, -1, -1):
             refresh_cnt, rd_enable, wr_enable = yield REF_NOP2, CMD_NOP
         yield from self.idle()