From 57179ce98687e7f1f97a680732ca17de780e362b Mon Sep 17 00:00:00 2001
From: Lenny Truong <leonardtruong@fb.com>
Date: Thu, 19 Dec 2019 09:43:21 -0800
Subject: [PATCH] Add ability to include inline verilog

---
 include/verilogAST.hpp | 9 +++++++++
 tests/basic.cpp        | 8 ++++++++
 2 files changed, 17 insertions(+)

diff --git a/include/verilogAST.hpp b/include/verilogAST.hpp
index e52819e..b6de785 100644
--- a/include/verilogAST.hpp
+++ b/include/verilogAST.hpp
@@ -319,6 +319,15 @@ class BlockComment : public StructuralStatement, public BehavioralStatement {
   ~BlockComment(){};
 };
 
+class InlineVerilog : public StructuralStatement, public BehavioralStatement {
+ public:
+  std::string value;
+
+  InlineVerilog(std::string value) : value(value){};
+  std::string toString() { return value; };
+  ~InlineVerilog(){};
+};
+
 typedef std::vector<
     std::pair<std::unique_ptr<Identifier>, std::unique_ptr<Expression>>>
     Parameters;
diff --git a/tests/basic.cpp b/tests/basic.cpp
index 4830450..7accbca 100644
--- a/tests/basic.cpp
+++ b/tests/basic.cpp
@@ -395,6 +395,14 @@ TEST(BasicTests, Comment) {
   EXPECT_EQ(block_comment.toString(),
             "/*\nTest comment\non multiple lines\n*/");
 }
+TEST(BasicTests, InlineVerilog) {
+  vAST::InlineVerilog inline_verilog(
+      "logic [1:0] x;\n"
+      "assign x = 2'b10;\n");
+  EXPECT_EQ(inline_verilog.toString(),
+            "logic [1:0] x;\n"
+            "assign x = 2'b10;\n");
+}
 
 }  // namespace