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general-cores
Verilog VHDL SystemVerilog Python C Lua Other
branch: master

This branch is even with lnls-dig:master

modules/genrams/*: change to appease Vivado 2014.4

1: Vivado 2014.4 seems to have a buggy READ (L: inout LINE;
VALUE: out BIT; GOOD: out BOOLEAN) procedure. Instead,
we can use the procedure READ (L: inout LINE; VALUE: out BIT)
which does the correct thing.

2: Vivado 2014.4 does not support the same RAM inference
code style.

3: Vivado 2014.4 seems to have a problem returning "large"
RAM variables to DPRAM modules, as we did before. Now,
we check if the file before calling the memory load function.
latest commit cc53ef7f6c
@lerwys authored

README

OHWR general-cores VHDL library
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TEST RELEASE - NOT READY FOR USE!

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This is a fork of the original project
general-cores hosted at 
http://www.ohwr.org/projects/general-cores

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