From 4beed175b6d89016320eda0881f6dc6f18fafbca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= Date: Sun, 23 Jun 2013 14:16:55 -0400 Subject: [PATCH] wishbone/xwb_lm32: add user-defined reset vector as a generic parameter --- modules/wishbone/wb_lm32/gen_lmcores.py | 9 +- .../wb_lm32/generated/lm32_allprofiles.v | 11902 ++++++++-------- .../wishbone/wb_lm32/generated/xwb_lm32.vhd | 45 +- modules/wishbone/wb_lm32/src/lm32_top.v | 6 +- modules/wishbone/wishbone_pkg.vhd | 3 +- .../lm32_testsys/lm32_test_system.vhd | 7 +- testbench/wishbone/lm32_testsys/sw/main.ram | 217 +- .../lm32_testsys/sw/target/lm32/ram.ld | 2 +- testbench/wishbone/lm32_testsys/wave.do | 6 +- 9 files changed, 6135 insertions(+), 6062 deletions(-) diff --git a/modules/wishbone/wb_lm32/gen_lmcores.py b/modules/wishbone/wb_lm32/gen_lmcores.py index fc52481..bc1e062 100755 --- a/modules/wishbone/wb_lm32/gen_lmcores.py +++ b/modules/wishbone/wb_lm32/gen_lmcores.py @@ -122,7 +122,9 @@ def parse_profiles(): return list(p) def gen_vhdl_component(f, profile_name): - f.write("component lm32_top_"+profile_name+" is port (\n"); + f.write("component lm32_top_"+profile_name+" is \n") + f.write("generic ( eba_reset: std_logic_vector(31 downto 0) );\n"); + f.write("port (\n"); f.write(""" clk_i : in std_logic; rst_i : in std_logic; @@ -174,7 +176,8 @@ def gen_vhdl_wrapper(prof): use ieee.numeric_std.all; use work.wishbone_pkg.all; entity xwb_lm32 is -generic(g_profile: string); +generic(g_profile: string; +g_reset_vector: std_logic_vector(31 downto 0) := x"00000000"); port( clk_sys_i : in std_logic; rst_n_i : in std_logic; @@ -259,6 +262,8 @@ def gen_vhdl_wrapper(prof): f.write("gen_profile_"+p[0]+": if (g_profile = \"" + p[0]+"\") generate\n"); f.write("U_Wrapped_LM32: lm32_top_"+p[0]+"\n"); f.write(""" +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, diff --git a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v index dadde6b..ba65c59 100644 --- a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v +++ b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v @@ -53,6 +53,8 @@ + + @@ -78,13 +80,20 @@ - - - - + + + + + + + + + + - + + @@ -222,24 +231,25 @@ - + + - - + + + + - - @@ -342,24 +352,34 @@ - - + + + + + + + + + + - + - + + + @@ -371,6 +391,8 @@ + + @@ -378,27 +400,28 @@ - - + - - + + + + + - - - - - - - - + + + + + + + @@ -557,7 +580,7 @@ -module lm32_top_full ( +module lm32_top_full_debug ( clk_i, rst_i, @@ -619,6 +642,7 @@ module lm32_top_full ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -714,14 +738,15 @@ wire [ (2-1):0] D_BTE_O; - - - - - - - +wire [ 7:0] jtag_reg_d; +wire [ 7:0] jtag_reg_q; +wire jtag_update; +wire [2:0] jtag_reg_addr_d; +wire [2:0] jtag_reg_addr_q; +wire jtck; +wire jrstn; + @@ -800,7 +825,10 @@ endfunction -lm32_cpu_full cpu ( +lm32_cpu_full_debug + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), @@ -821,12 +849,13 @@ lm32_cpu_full cpu ( - - - - - + + .jtag_clk (jtck), + .jtag_update (jtag_update), + .jtag_reg_q (jtag_reg_q), + .jtag_reg_addr_q (jtag_reg_addr_q), + @@ -855,9 +884,10 @@ lm32_cpu_full cpu ( - - + .jtag_reg_d (jtag_reg_d), + .jtag_reg_addr_d (jtag_reg_addr_d), + @@ -892,20 +922,21 @@ lm32_cpu_full cpu ( .D_BTE_O (D_BTE_O) ); - - + + +jtag_cores jtag_cores ( - - - - - - - - + .reg_d (jtag_reg_d), + .reg_addr_d (jtag_reg_addr_d), - + .reg_update (jtag_update), + .reg_q (jtag_reg_q), + .reg_addr_q (jtag_reg_addr_q), + .jtck (jtck), + .jrstn (jrstn) + ); + endmodule @@ -1277,7 +1308,7 @@ endmodule -module lm32_mc_arithmetic_full ( +module lm32_mc_arithmetic_full_debug ( clk_i, rst_i, @@ -1943,7 +1974,7 @@ endmodule -module lm32_cpu_full ( +module lm32_cpu_full_debug ( clk_i, @@ -1964,12 +1995,13 @@ module lm32_cpu_full ( - - - - - + + jtag_clk, + jtag_update, + jtag_reg_q, + jtag_reg_addr_q, + @@ -1998,9 +2030,10 @@ module lm32_cpu_full ( - - + jtag_reg_d, + jtag_reg_addr_d, + @@ -2041,8 +2074,9 @@ module lm32_cpu_full ( parameter eba_reset = 32'h00000000; - +parameter deba_reset = 32'h10000000; + @@ -2078,11 +2112,11 @@ parameter dcache_limit = 32'h7fffffff; - - -parameter watchpoints = 0; +parameter watchpoints = 32'h4; + + @@ -2124,11 +2158,12 @@ input [ (32-1):0] interrupt; - - - - +input jtag_clk; +input jtag_update; +input [ 7:0] jtag_reg_q; +input [2:0] jtag_reg_addr_q; + @@ -2168,11 +2203,12 @@ input D_RTY_I; - - - - +output [ 7:0] jtag_reg_d; +wire [ 7:0] jtag_reg_d; +output [2:0] jtag_reg_addr_d; +wire [2:0] jtag_reg_addr_d; + @@ -2355,14 +2391,15 @@ wire [ (5-1):0] write_idx_d; reg [ (5-1):0] write_idx_x; reg [ (5-1):0] write_idx_m; reg [ (5-1):0] write_idx_w; -wire [ (4 -1):0] csr_d; -reg [ (4 -1):0] csr_x; +wire [ (5-1):0] csr_d; +reg [ (5-1):0] csr_x; wire [ (3-1):0] condition_d; reg [ (3-1):0] condition_x; - - +wire break_d; +reg break_x; + wire scall_d; reg scall_x; @@ -2375,14 +2412,16 @@ wire eret_q_x; - - - - + +wire bret_d; +reg bret_x; +wire bret_q_x; + + wire csr_write_enable_d; reg csr_write_enable_x; @@ -2587,25 +2626,32 @@ wire stall_wb_load; - - - - - - - - + +wire [ (32-1):0] jtx_csr_read_data; +wire [ (32-1):0] jrx_csr_read_data; + - - +wire jtag_csr_write_enable; +wire [ (32-1):0] jtag_csr_write_data; +wire [ (5-1):0] jtag_csr; +wire jtag_read_enable; +wire [ 7:0] jtag_read_data; +wire jtag_write_enable; +wire [ 7:0] jtag_write_data; +wire [ (32-1):0] jtag_address; +wire jtag_access_complete; - + +wire jtag_break; + + + @@ -2638,8 +2684,9 @@ wire kill_w; reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba; - +reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba; + reg [ (3-1):0] eid_x; @@ -2649,36 +2696,41 @@ reg [ (3-1):0] eid_x; - - - + + +wire dc_ss; + +wire dc_re; +wire bp_match; +wire wp_match; +wire exception_x; +reg exception_m; +wire debug_exception_x; +reg debug_exception_m; +reg debug_exception_w; +wire debug_exception_q_w; +wire non_debug_exception_x; +reg non_debug_exception_m; +reg non_debug_exception_w; +wire non_debug_exception_q_w; - - - - - - -wire exception_x; -reg exception_m; -reg exception_w; -wire exception_q_w; - + - - +wire reset_exception; + + @@ -2686,9 +2738,10 @@ wire interrupt_exception; - - +wire breakpoint_exception; +wire watchpoint_exception; + @@ -2772,7 +2825,7 @@ endfunction -lm32_instruction_unit_full #( +lm32_instruction_unit_full_debug #( .eba_reset (eba_reset), .associativity (icache_associativity), .sets (icache_sets), @@ -2832,11 +2885,12 @@ lm32_instruction_unit_full #( - - - - + .jtag_read_enable (jtag_read_enable), + .jtag_write_enable (jtag_write_enable), + .jtag_write_data (jtag_write_data), + .jtag_address (jtag_address), + @@ -2872,9 +2926,10 @@ lm32_instruction_unit_full #( - - + .jtag_read_data (jtag_read_data), + .jtag_access_complete (jtag_access_complete), + @@ -2890,7 +2945,7 @@ lm32_instruction_unit_full #( ); -lm32_decoder_full decoder ( +lm32_decoder_full_debug decoder ( .instruction (instruction_d), @@ -2971,14 +3026,16 @@ lm32_decoder_full decoder ( .branch_reg (branch_reg_d), .condition (condition_d), - + .break_opcode (break_d), + .scall (scall_d), .eret (eret_d), - + .bret (bret_d), + @@ -2988,7 +3045,7 @@ lm32_decoder_full decoder ( ); -lm32_load_store_unit_full #( +lm32_load_store_unit_full_debug #( .associativity (dcache_associativity), .sets (dcache_sets), .bytes_per_line (dcache_bytes_per_line), @@ -3124,7 +3181,7 @@ lm32_multiplier multiplier ( -lm32_mc_arithmetic_full mc_arithmetic ( +lm32_mc_arithmetic_full_debug mc_arithmetic ( .clk_i (clk_i), .rst_i (rst_i), @@ -3163,7 +3220,7 @@ lm32_mc_arithmetic_full mc_arithmetic ( -lm32_interrupt_full interrupt_unit ( +lm32_interrupt_full_debug interrupt_unit ( .clk_i (clk_i), .rst_i (rst_i), @@ -3172,17 +3229,18 @@ lm32_interrupt_full interrupt_unit ( .stall_x (stall_x), - - - - .exception (exception_q_w), + .non_debug_exception (non_debug_exception_q_w), + .debug_exception (debug_exception_q_w), + + .eret_q_x (eret_q_x), - + .bret_q_x (bret_q_x), + .csr (csr_x), .csr_write_data (operand_1_x), @@ -3197,95 +3255,117 @@ lm32_interrupt_full interrupt_unit ( - + +lm32_jtag_full_debug jtag ( - - + .clk_i (clk_i), + .rst_i (rst_i), - - - - + .jtag_clk (jtag_clk), + .jtag_update (jtag_update), + .jtag_reg_q (jtag_reg_q), + .jtag_reg_addr_q (jtag_reg_addr_q), + + + .csr (csr_x), + .csr_write_data (operand_1_x), + .csr_write_enable (csr_write_enable_q_x), + .stall_x (stall_x), - - - - + + + .jtag_read_data (jtag_read_data), + .jtag_access_complete (jtag_access_complete), - - + + + .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), - + + + .jtx_csr_read_data (jtx_csr_read_data), + .jrx_csr_read_data (jrx_csr_read_data), - - + + + .jtag_csr_write_enable (jtag_csr_write_enable), + .jtag_csr_write_data (jtag_csr_write_data), + .jtag_csr (jtag_csr), + .jtag_read_enable (jtag_read_enable), + .jtag_write_enable (jtag_write_enable), + .jtag_write_data (jtag_write_data), + .jtag_address (jtag_address), - - - - - - - + + + .jtag_break (jtag_break), + .jtag_reset (reset_exception), - - - - - - + .jtag_reg_d (jtag_reg_d), + .jtag_reg_addr_d (jtag_reg_addr_d) + ); + - - - - + +lm32_debug_full_debug #( + .breakpoints (breakpoints), + .watchpoints (watchpoints) + ) hw_debug ( - - - - - - - - - - - - - + .clk_i (clk_i), + .rst_i (rst_i), + .pc_x (pc_x), + .load_x (load_x), + .store_x (store_x), + .load_store_address_x (adder_result_x), + .csr_write_enable_x (csr_write_enable_q_x), + .csr_write_data (operand_1_x), + .csr_x (csr_x), + + .jtag_csr_write_enable (jtag_csr_write_enable), + .jtag_csr_write_data (jtag_csr_write_data), + .jtag_csr (jtag_csr), - - - - - - - + + + .eret_q_x (eret_q_x), + .bret_q_x (bret_q_x), + .stall_x (stall_x), + .exception_x (exception_x), + .q_x (q_x), + + + .dcache_refill_request (dcache_refill_request), + - - - - - + + .dc_ss (dc_ss), + + + .dc_re (dc_re), + .bp_match (bp_match), + .wp_match (wp_match) + ); + @@ -3785,21 +3865,25 @@ assign kill_w = 1'b0 - - - - - - - - +assign breakpoint_exception = ( ( (break_x == 1'b1) + || (bp_match == 1'b1) + ) + && (valid_x == 1'b1) + ) + + || (jtag_break == 1'b1) + + + ; + - +assign watchpoint_exception = wp_match == 1'b1; + @@ -3826,38 +3910,17 @@ assign system_call_exception = ( (scall_x == 1'b1) ); - - - - - - - - - - +assign debug_exception_x = (breakpoint_exception == 1'b1) + || (watchpoint_exception == 1'b1) + ; - - +assign non_debug_exception_x = (system_call_exception == 1'b1) + + || (reset_exception == 1'b1) - - - - - - - - - - - - - - -assign exception_x = (system_call_exception == 1'b1) || (instruction_bus_error_exception == 1'b1) @@ -3873,8 +3936,9 @@ assign exception_x = (system_call_exception == 1'b1) || ( (interrupt_exception == 1'b1) - + && (dc_ss == 1'b0) + @@ -3886,27 +3950,55 @@ assign exception_x = (system_call_exception == 1'b1) ; + +assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1); + + + + + + + + + + + + + + + + + + + + + always @(*) begin + + + + if (reset_exception == 1'b1) + eid_x = 3'h0; + else - - - - - - - + - - - + if (data_bus_error_exception == 1'b1) + eid_x = 3'h4; + else + + if (breakpoint_exception == 1'b1) + eid_x = 3'd1; + else + @@ -3919,10 +4011,11 @@ begin - - - + if (watchpoint_exception == 1'b1) + eid_x = 3'd3; + else + @@ -3935,8 +4028,9 @@ begin if ( (interrupt_exception == 1'b1) - + && (dc_ss == 1'b0) + ) eid_x = 3'h6; @@ -3973,18 +4067,19 @@ assign stall_d = (stall_x == 1'b1) && (kill_d == 1'b0) ) - - - - - - - - - - - + || ( ( (break_d == 1'b1) + || (bret_d == 1'b1) + ) + && ( (load_q_x == 1'b1) + || (store_q_x == 1'b1) + || (load_q_m == 1'b1) + || (store_q_m == 1'b1) + || (D_CYC_O == 1'b1) + ) + && (kill_d == 1'b0) + ) + || ( (csr_write_enable_d == 1'b1) && (load_q_x == 1'b1) @@ -4090,21 +4185,24 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0); assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1); assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1); - +assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1); + assign load_q_x = (load_x == 1'b1) && (q_x == 1'b1) - + && (bp_match == 1'b0) + ; assign store_q_x = (store_x == 1'b1) && (q_x == 1'b1) - + && (bp_match == 1'b0) + ; @@ -4115,12 +4213,12 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0); assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1); assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1); - - - -assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1)); +assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1)); +assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1)); + + assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0); @@ -4136,19 +4234,12 @@ assign cfg = { breakpoints[3:0], interrupts[5:0], - - - 1'b0, + 1'b1, - - - 1'b0, - - @@ -4157,11 +4248,18 @@ assign cfg = { + + 1'b1, + - 1'b0, + + + 1'b1, + + @@ -4243,16 +4341,17 @@ assign cfg2 = { assign iflush = ( (csr_write_enable_d == 1'b1) - && (csr_d == 4 'h3) + && (csr_d == 5'h3) && (stall_d == 1'b0) && (kill_d == 1'b0) && (valid_d == 1'b1)) - - - + || + ( (jtag_csr_write_enable == 1'b1) + && (jtag_csr == 5'h3)) + ; @@ -4260,20 +4359,21 @@ assign iflush = ( (csr_write_enable_d == 1'b1) assign dflush_x = ( (csr_write_enable_q_x == 1'b1) - && (csr_x == 4 'h4)) + && (csr_x == 5'h4)) - - - + || + ( (jtag_csr_write_enable == 1'b1) + && (jtag_csr == 5'h4)) + ; -assign csr_d = read_idx_0_d[ (4 -1):0]; +assign csr_d = read_idx_0_d[ (5-1):0]; always @(*) @@ -4281,27 +4381,29 @@ begin case (csr_x) - 4 'h0, - 4 'h1, - 4 'h2: csr_read_data_x = interrupt_csr_read_data_x; + 5'h0, + 5'h1, + 5'h2: csr_read_data_x = interrupt_csr_read_data_x; - 4 'h6: csr_read_data_x = cfg; - 4 'h7: csr_read_data_x = {eba, 8'h00}; + 5'h6: csr_read_data_x = cfg; + 5'h7: csr_read_data_x = {eba, 8'h00}; - + 5'h9: csr_read_data_x = {deba, 8'h00}; + - - + 5'he: csr_read_data_x = jtx_csr_read_data; + 5'hf: csr_read_data_x = jrx_csr_read_data; + - 4 'ha: csr_read_data_x = cfg2; + 5'ha: csr_read_data_x = cfg2; default: csr_read_data_x = { 32{1'bx}}; endcase @@ -4318,33 +4420,37 @@ begin eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; else begin - if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0)) + if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0)) eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - - + if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7)) + eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + end end - - - - - - - - - - - - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + else + begin + if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0)) + deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9)) + deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + end +end + @@ -4525,7 +4631,7 @@ begin m_bypass_enable_x <= 1'b0; write_enable_x <= 1'b0; write_idx_x <= { 5{1'b0}}; - csr_x <= { 4 {1'b0}}; + csr_x <= { 5{1'b0}}; load_x <= 1'b0; store_x <= 1'b0; size_x <= { 2{1'b0}}; @@ -4548,14 +4654,16 @@ begin branch_predict_taken_x <= 1'b0; condition_x <= 3'b000; - + break_x <= 1'b0; + scall_x <= 1'b0; eret_x <= 1'b0; - + bret_x <= 1'b0; + @@ -4594,9 +4702,10 @@ begin - - + debug_exception_m <= 1'b0; + non_debug_exception_m <= 1'b0; + operand_w <= { 32{1'b0}}; w_result_sel_load_w <= 1'b0; @@ -4608,12 +4717,12 @@ begin write_idx_w <= { 5{1'b0}}; write_enable_w <= 1'b0; - - - - exception_w <= 1'b0; + debug_exception_w <= 1'b0; + non_debug_exception_w <= 1'b0; + + @@ -4693,8 +4802,9 @@ begin condition_x <= condition_d; csr_write_enable_x <= csr_write_enable_d; - + break_x <= break_d; + scall_x <= scall_d; @@ -4704,8 +4814,9 @@ begin eret_x <= eret_d; - + bret_x <= bret_d; + write_enable_x <= write_enable_d; end @@ -4752,40 +4863,40 @@ begin + - - - - - - - - - if (exception_x == 1'b1) + if (non_debug_exception_x == 1'b1) write_idx_m <= 5'd30; + else if (debug_exception_x == 1'b1) + write_idx_m <= 5'd31; else write_idx_m <= write_idx_x; + + + + + condition_met_m <= condition_met_x; - - - - - - - - - - - branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x; + if (exception_x == 1'b1) + if ((dc_re == 1'b1) + || ((debug_exception_x == 1'b1) + && (non_debug_exception_x == 1'b0))) + branch_target_m <= {deba, eid_x, {3{1'b0}}}; + else + branch_target_m <= {eba, eid_x, {3{1'b0}}}; + else + branch_target_m <= branch_target_x; + + @@ -4805,9 +4916,10 @@ begin write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x; - - + debug_exception_m <= debug_exception_x; + non_debug_exception_m <= non_debug_exception_x; + end @@ -4822,8 +4934,9 @@ begin data_bus_error_exception_m <= (data_bus_error_exception == 1'b1) - + && (reset_exception == 1'b0) + ; @@ -4855,12 +4968,12 @@ begin write_enable_w <= write_enable_m; - - - - exception_w <= exception_m; + debug_exception_w <= debug_exception_m; + non_debug_exception_w <= non_debug_exception_m; + + @@ -5406,7 +5519,7 @@ endmodule -module lm32_load_store_unit_full ( +module lm32_load_store_unit_full_debug ( clk_i, rst_i, @@ -5784,7 +5897,7 @@ endfunction -lm32_dcache_full #( +lm32_dcache_full_debug #( .associativity (associativity), .sets (sets), .bytes_per_line (bytes_per_line), @@ -6736,7 +6849,7 @@ endmodule -module lm32_decoder_full ( +module lm32_decoder_full_debug ( instruction, @@ -6817,14 +6930,16 @@ module lm32_decoder_full ( bi_conditional, bi_unconditional, - + break_opcode, + scall, eret, - + bret, + @@ -6960,18 +7075,20 @@ wire bi_conditional; output bi_unconditional; wire bi_unconditional; - - +output break_opcode; +wire break_opcode; + output scall; wire scall; output eret; wire eret; - - +output bret; +wire bret; + @@ -7426,14 +7543,16 @@ assign branch = bra | call; assign branch_reg = op_call | op_b; assign condition = instruction[28:26]; - +assign break_opcode = op_raise & ~instruction[2]; + assign scall = op_raise & instruction[2]; assign eret = op_b & (instruction[25:21] == 5'd30); - +assign bret = op_b & (instruction[25:21] == 5'd31); + @@ -7865,7 +7984,7 @@ endmodule -module lm32_icache_full ( +module lm32_icache_full_debug ( clk_i, rst_i, @@ -8711,7 +8830,7 @@ endmodule -module lm32_dcache_full ( +module lm32_dcache_full_debug ( clk_i, rst_i, @@ -9567,184 +9686,175 @@ endmodule - - - - - - + + + + + + + + + + + + +module lm32_debug_full_debug ( - - - - - - - - - - - - - + clk_i, + rst_i, + pc_x, + load_x, + store_x, + load_store_address_x, + csr_write_enable_x, + csr_write_data, + csr_x, + + jtag_csr_write_enable, + jtag_csr_write_data, + jtag_csr, - - - - - + + + + eret_q_x, + bret_q_x, + stall_x, + exception_x, + q_x, + + + dcache_refill_request, - + + + + dc_ss, - - - - - + dc_re, + bp_match, + wp_match + ); - - +parameter breakpoints = 0; +parameter watchpoints = 0; - - +input clk_i; +input rst_i; - - - - - - - +input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; +input load_x; +input store_x; +input [ (32-1):0] load_store_address_x; +input csr_write_enable_x; +input [ (32-1):0] csr_write_data; +input [ (5-1):0] csr_x; + + +input jtag_csr_write_enable; +input [ (32-1):0] jtag_csr_write_data; +input [ (5-1):0] jtag_csr; - - - + + +input eret_q_x; +input bret_q_x; +input stall_x; +input exception_x; +input q_x; + + +input dcache_refill_request; - - - - - + - + +output dc_ss; +reg dc_ss; - - - - - - - - +output dc_re; +reg dc_re; +output bp_match; +wire bp_match; +output wp_match; +wire wp_match; - +genvar i; - - - +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1]; +reg bp_e[0:breakpoints-1]; +wire [0:breakpoints-1]bp_match_n; - - - +reg [ 1:0] wpc_c[0:watchpoints-1]; +reg [ (32-1):0] wp[0:watchpoints-1]; +wire [0:watchpoints-1]wp_match_n; - - - +wire debug_csr_write_enable; +wire [ (32-1):0] debug_csr_write_data; +wire [ (5-1):0] debug_csr; - + - +reg [ 2:0] state; + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -9753,132 +9863,228 @@ endmodule - - - - - - - - - - - - - - - - - - - - - + +function integer clogb2; +input [31:0] value; +begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; +end +endfunction - - - - - - - - - - - - - - - +function integer clogb2_v1; +input [31:0] value; +reg [31:0] i; +reg [31:0] temp; +begin + temp = 0; + i = 0; + for (i = 0; temp < value; i = i + 1) + temp = 1< 0) +assign bp_match = (|bp_match_n) || (state == 3'b011); + else +assign bp_match = state == 3'b011; + + + + + + +endgenerate - - + +generate + for (i = 0; i < watchpoints; i = i + 1) + begin : wp_comb +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); + end +endgenerate +generate + if (watchpoints > 0) +assign wp_match = |wp_match_n; + else +assign wp_match = 1'b0; +endgenerate - - - - - - - - - - - - - - - - - - - - - - - - + + + +assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1); +assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data; +assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x; - - - + + + - + + + + + + + +generate + for (i = 0; i < breakpoints; i = i + 1) + begin : bp_seq +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}}; + bp_e[i] <= 1'b0; + end + else + begin + if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i)) + begin + bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]; + bp_e[i] <= debug_csr_write_data[0]; + end + end +end + end +endgenerate + + +generate + for (i = 0; i < watchpoints; i = i + 1) + begin : wp_seq +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + wp[i] <= { 32{1'bx}}; + wpc_c[i] <= 2'b00; + end + else + begin + if (debug_csr_write_enable == 1'b1) + begin + if (debug_csr == 5'h8) + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; + if (debug_csr == 5'h18 + i) + wp[i] <= debug_csr_write_data; + end + end +end + end +endgenerate + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + dc_re <= 1'b0; + else + begin + if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) + dc_re <= debug_csr_write_data[1]; + end +end + + + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + state <= 3'b000; + dc_ss <= 1'b0; + end + else + begin + if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) + begin + dc_ss <= debug_csr_write_data[0]; + if (debug_csr_write_data[0] == 1'b0) + state <= 3'b000; + else + state <= 3'b001; + end + case (state) + 3'b001: + begin - - + if ( ( (eret_q_x == 1'b1) + || (bret_q_x == 1'b1) + ) + && (stall_x == 1'b0) + ) + state <= 3'b010; + end + 3'b010: + begin - - - + if ((q_x == 1'b1) && (stall_x == 1'b0)) + state <= 3'b011; + end + 3'b011: + begin - - - - + - - - - + if (dcache_refill_request == 1'b1) + state <= 3'b010; + else + + if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0)) + begin + dc_ss <= 1'b0; + state <= 3'b100; + end + end + 3'b100: + begin + + + if (dcache_refill_request == 1'b1) + state <= 3'b010; + else + + state <= 3'b000; + end + endcase + end +end + +endmodule + @@ -10251,7 +10457,7 @@ endmodule -module lm32_instruction_unit_full ( +module lm32_instruction_unit_full_debug ( clk_i, rst_i, @@ -10304,11 +10510,12 @@ module lm32_instruction_unit_full ( - - - - + jtag_read_enable, + jtag_write_enable, + jtag_write_data, + jtag_address, + @@ -10344,9 +10551,10 @@ module lm32_instruction_unit_full ( - - + jtag_read_data, + jtag_access_complete, + @@ -10438,11 +10646,12 @@ input i_rty_i; - - - - +input jtag_read_enable; +input jtag_write_enable; +input [ 7:0] jtag_write_data; +input [ (32-1):0] jtag_address; + @@ -10483,11 +10692,11 @@ wire icache_refilling; output [ (32-1):0] i_dat_o; - - -wire [ (32-1):0] i_dat_o; +reg [ (32-1):0] i_dat_o; + + output [ (32-1):0] i_adr_o; reg [ (32-1):0] i_adr_o; @@ -10495,21 +10704,21 @@ output i_cyc_o; reg i_cyc_o; output [ (4-1):0] i_sel_o; - - -wire [ (4-1):0] i_sel_o; +reg [ (4-1):0] i_sel_o; + + output i_stb_o; reg i_stb_o; output i_we_o; - - -wire i_we_o; +reg i_we_o; + + output [ (3-1):0] i_cti_o; reg [ (3-1):0] i_cti_o; @@ -10521,11 +10730,12 @@ wire [ (2-1):0] i_bte_o; - - - - +output [ 7:0] jtag_read_data; +reg [ 7:0] jtag_read_data; +output jtag_access_complete; +wire jtag_access_complete; + @@ -10591,8 +10801,9 @@ reg bus_error_f; - +reg jtag_access; + @@ -10710,7 +10921,7 @@ endfunction -lm32_icache_full #( +lm32_icache_full_debug #( .associativity (associativity), .sets (sets), .bytes_per_line (bytes_per_line), @@ -10833,11 +11044,11 @@ assign instruction_f = icache_data_f; - -assign i_dat_o = 32'd0; -assign i_we_o = 1'b0; -assign i_sel_o = 4'b1111; + + + + assign i_bte_o = 2'b00; @@ -10954,17 +11165,18 @@ end - - - - - - - - - - +assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1); +always @(*) +begin + case (jtag_address[1:0]) + 2'b00: jtag_read_data = i_dat_i[ 31:24]; + 2'b01: jtag_read_data = i_dat_i[ 23:16]; + 2'b10: jtag_read_data = i_dat_i[ 15:8]; + 2'b11: jtag_read_data = i_dat_i[ 7:0]; + endcase +end + @@ -10989,10 +11201,11 @@ begin - - - + i_we_o <= 1'b0; + i_sel_o <= 4'b1111; + jtag_access <= 1'b0; + end else @@ -11005,15 +11218,16 @@ begin if ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) begin - - - - - - - - + if (jtag_access == 1'b1) + begin + i_cyc_o <= 1'b0; + i_stb_o <= 1'b0; + i_we_o <= 1'b0; + jtag_access <= 1'b0; + end + else + begin if (last_word == 1'b1) @@ -11046,9 +11260,10 @@ begin if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0)) begin - - - + + + i_sel_o <= 4'b1111; + i_adr_o <= {first_address, 2'b00}; i_cyc_o <= 1'b1; @@ -11062,26 +11277,27 @@ begin end - - - - - - - - - - - - - - - - - - - + else + begin + if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1)) + begin + case (jtag_address[1:0]) + 2'b00: i_sel_o <= 4'b1000; + 2'b01: i_sel_o <= 4'b0100; + 2'b10: i_sel_o <= 4'b0010; + 2'b11: i_sel_o <= 4'b0001; + endcase + i_adr_o <= jtag_address; + i_dat_o <= {4{jtag_write_data}}; + i_cyc_o <= 1'b1; + i_stb_o <= 1'b1; + i_we_o <= jtag_write_enable; + i_cti_o <= 3'b111; + jtag_access <= 1'b1; + end + end + @@ -11556,443 +11772,523 @@ endmodule - - - + - - - - - - - - + + - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +module lm32_jtag_full_debug ( - - - - - - + clk_i, + rst_i, + jtag_clk, + jtag_update, + jtag_reg_q, + jtag_reg_addr_q, + + + csr, + csr_write_enable, + csr_write_data, + stall_x, - - - - + + + jtag_read_data, + jtag_access_complete, - - + + + exception_q_w, - + + + jtx_csr_read_data, + jrx_csr_read_data, - - + + + jtag_csr_write_enable, + jtag_csr_write_data, + jtag_csr, + jtag_read_enable, + jtag_write_enable, + jtag_write_data, + jtag_address, - - - - - - - + + + jtag_break, + jtag_reset, - - - - - + jtag_reg_d, + jtag_reg_addr_d + ); - - +input clk_i; +input rst_i; - - - - +input jtag_clk; +input jtag_update; +input [ 7:0] jtag_reg_q; +input [2:0] jtag_reg_addr_q; + + +input [ (5-1):0] csr; +input csr_write_enable; +input [ (32-1):0] csr_write_data; +input stall_x; - - - - + + +input [ 7:0] jtag_read_data; +input jtag_access_complete; - - + + +input exception_q_w; - - - - - - + +output [ (32-1):0] jtx_csr_read_data; +wire [ (32-1):0] jtx_csr_read_data; +output [ (32-1):0] jrx_csr_read_data; +wire [ (32-1):0] jrx_csr_read_data; - - - - - - - - - - - - - - + + +output jtag_csr_write_enable; +reg jtag_csr_write_enable; +output [ (32-1):0] jtag_csr_write_data; +wire [ (32-1):0] jtag_csr_write_data; +output [ (5-1):0] jtag_csr; +wire [ (5-1):0] jtag_csr; +output jtag_read_enable; +reg jtag_read_enable; +output jtag_write_enable; +reg jtag_write_enable; +output [ 7:0] jtag_write_data; +wire [ 7:0] jtag_write_data; +output [ (32-1):0] jtag_address; +wire [ (32-1):0] jtag_address; - - - - - - - + +output jtag_break; +reg jtag_break; +output jtag_reset; +reg jtag_reset; + + +output [ 7:0] jtag_reg_d; +reg [ 7:0] jtag_reg_d; +output [2:0] jtag_reg_addr_d; +wire [2:0] jtag_reg_addr_d; - - - - +reg rx_update; +reg rx_update_r; +reg rx_update_r_r; +reg rx_update_r_r_r; - +wire [ 7:0] rx_byte; +wire [2:0] rx_addr; + + +reg [ 7:0] uart_tx_byte; +reg uart_tx_valid; +reg [ 7:0] uart_rx_byte; +reg uart_rx_valid; + - - - - - +reg [ 3:0] command; + - +reg [ 7:0] jtag_byte_0; +reg [ 7:0] jtag_byte_1; +reg [ 7:0] jtag_byte_2; +reg [ 7:0] jtag_byte_3; +reg [ 7:0] jtag_byte_4; +reg processing; - - - - - - - +reg [ 3:0] state; + + +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; +assign jtag_csr = jtag_byte_4[ (5-1):0]; +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; +assign jtag_write_data = jtag_byte_4; - - - - - - - + + +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; + + + + +assign jtag_reg_addr_d[2] = processing; - - - - + + +assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00}; +assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte}; + - - +assign rx_byte = jtag_reg_q; +assign rx_addr = jtag_reg_addr_q; - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + rx_update <= 1'b0; + rx_update_r <= 1'b0; + rx_update_r_r <= 1'b0; + rx_update_r_r_r <= 1'b0; + end + else + begin + rx_update <= jtag_update; + rx_update_r <= rx_update; + rx_update_r_r <= rx_update_r; + rx_update_r_r_r <= rx_update_r_r; + end +end - - - - - - - - - - - - - - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + state <= 4'h0; + command <= 4'b0000; + jtag_reg_d <= 8'h00; + + processing <= 1'b0; + jtag_csr_write_enable <= 1'b0; + jtag_read_enable <= 1'b0; + jtag_write_enable <= 1'b0; + - + - - - - - + jtag_break <= 1'b0; + jtag_reset <= 1'b0; - - - - + + + uart_tx_byte <= 8'h00; + uart_tx_valid <= 1'b0; + uart_rx_byte <= 8'h00; + uart_rx_valid <= 1'b0; - - - - - - - - - - - - - - - - - + end + else + begin + + + if ((csr_write_enable == 1'b1) && (stall_x == 1'b0)) + begin + case (csr) + 5'he: + begin - - - - - + uart_tx_byte <= csr_write_data[ 7:0]; + uart_tx_valid <= 1'b1; + end + 5'hf: + begin - - - - - + uart_rx_valid <= 1'b0; + end + endcase + end + + + - - - - - + if (exception_q_w == 1'b1) + begin + jtag_break <= 1'b0; + jtag_reset <= 1'b0; + end + - - - - - + case (state) + 4'h0: + begin - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + command <= rx_byte[7:4]; + case (rx_addr) + - - - - - - - + 3'b000: + begin + case (rx_byte[7:4]) + - + 4'b0001: + state <= 4'h1; + 4'b0011: + begin + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; + state <= 4'h6; + end + 4'b0010: + state <= 4'h1; + 4'b0100: + begin + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; + state <= 5; + end + 4'b0101: + state <= 4'h1; + - - + 4'b0110: + begin + + + uart_rx_valid <= 1'b0; + uart_tx_valid <= 1'b0; + - - - - - - - - - - - + jtag_break <= 1'b1; + end + 4'b0111: + begin + + + uart_rx_valid <= 1'b0; + uart_tx_valid <= 1'b0; + - - - - - + jtag_reset <= 1'b1; + end + endcase + end - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + 3'b001: + begin + uart_rx_byte <= rx_byte; + uart_rx_valid <= 1'b1; + end + 3'b010: + begin + jtag_reg_d <= uart_tx_byte; + uart_tx_valid <= 1'b0; + end + + default: + ; + endcase + end + end + 4'h1: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_0 <= rx_byte; + state <= 4'h2; + end + end + 4'h2: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_1 <= rx_byte; + state <= 4'h3; + end + end + 4'h3: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_2 <= rx_byte; + state <= 4'h4; + end + end + 4'h4: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_3 <= rx_byte; + if (command == 4'b0001) + state <= 4'h6; + else + state <= 4'h5; + end + end + 4'h5: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_4 <= rx_byte; + state <= 4'h6; + end + end + 4'h6: + begin + case (command) + 4'b0001, + 4'b0011: + begin + jtag_read_enable <= 1'b1; + processing <= 1'b1; + state <= 4'h7; + end + 4'b0010, + 4'b0100: + begin + jtag_write_enable <= 1'b1; + processing <= 1'b1; + state <= 4'h7; + end + 4'b0101: + begin + jtag_csr_write_enable <= 1'b1; + processing <= 1'b1; + state <= 4'h8; + end + endcase + end + 4'h7: + begin + if (jtag_access_complete == 1'b1) + begin + jtag_read_enable <= 1'b0; + jtag_reg_d <= jtag_read_data; + jtag_write_enable <= 1'b0; + processing <= 1'b0; + state <= 4'h0; + end + end + 4'h8: + begin + jtag_csr_write_enable <= 1'b0; + processing <= 1'b0; + state <= 4'h0; + end + + endcase + end +end + +endmodule + @@ -12347,7 +12643,7 @@ endmodule -module lm32_interrupt_full ( +module lm32_interrupt_full_debug ( clk_i, rst_i, @@ -12356,17 +12652,18 @@ module lm32_interrupt_full ( stall_x, - - - - exception, + non_debug_exception, + debug_exception, + + eret_q_x, - + bret_q_x, + csr, csr_write_data, @@ -12395,20 +12692,21 @@ input [interrupts-1:0] interrupt; input stall_x; - - - -input exception; +input non_debug_exception; +input debug_exception; + + input eret_q_x; - +input bret_q_x; + -input [ (4 -1):0] csr; +input [ (5-1):0] csr; input [ (32-1):0] csr_write_data; input csr_write_enable; @@ -12435,8 +12733,9 @@ wire [interrupts-1:0] interrupt_n_exception; reg ie; reg eie; - +reg bie; + reg [interrupts-1:0] ip; reg [interrupts-1:0] im; @@ -12461,19 +12760,19 @@ generate always @(*) begin case (csr) - 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + 5'h0: csr_read_data = {{ 32-3{1'b0}}, - - - 1'b0, + bie, + + eie, ie }; - 4 'h2: csr_read_data = ip; - 4 'h1: csr_read_data = im; + 5'h2: csr_read_data = ip; + 5'h1: csr_read_data = im; default: csr_read_data = { 32{1'bx}}; endcase end @@ -12484,18 +12783,18 @@ end always @(*) begin case (csr) - 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + 5'h0: csr_read_data = {{ 32-3{1'b0}}, - - - 1'b0, + bie, + + eie, ie }; - 4 'h2: csr_read_data = ip; + 5'h2: csr_read_data = ip; default: csr_read_data = { 32{1'bx}}; endcase end @@ -12524,8 +12823,9 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; - + bie <= 1'b0; + im <= {interrupts{1'b0}}; ip <= {interrupts{1'b0}}; @@ -12537,13 +12837,21 @@ always @(posedge clk_i ) ip <= asserted; - - + + if (non_debug_exception == 1'b1) + begin - - - + eie <= ie; + ie <= 1'b0; + end + else if (debug_exception == 1'b1) + begin + bie <= ie; + ie <= 1'b0; + end + + @@ -12551,14 +12859,6 @@ always @(posedge clk_i ) - if (exception == 1'b1) - begin - - eie <= ie; - ie <= 1'b0; - end - - else if (stall_x == 1'b0) begin @@ -12576,26 +12876,28 @@ always @(posedge clk_i ) - - - + else if (bret_q_x == 1'b1) + + ie <= bie; + else if (csr_write_enable == 1'b1) begin - if (csr == 4 'h0) + if (csr == 5'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; - + bie <= csr_write_data[2]; + end - if (csr == 4 'h1) + if (csr == 5'h1) im <= csr_write_data[interrupts-1:0]; - if (csr == 4 'h2) + if (csr == 5'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -12612,8 +12914,9 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; - + bie <= 1'b0; + ip <= {interrupts{1'b0}}; eie_delay <= 0; @@ -12623,13 +12926,21 @@ always @(posedge clk_i ) ip <= asserted; - - + + if (non_debug_exception == 1'b1) + begin - - - + eie <= ie; + ie <= 1'b0; + end + else if (debug_exception == 1'b1) + begin + bie <= ie; + ie <= 1'b0; + end + + @@ -12637,14 +12948,6 @@ always @(posedge clk_i ) - if (exception == 1'b1) - begin - - eie <= ie; - ie <= 1'b0; - end - - else if (stall_x == 1'b0) begin @@ -12660,24 +12963,26 @@ always @(posedge clk_i ) end - - - + else if (bret_q_x == 1'b1) + + ie <= bie; + else if (csr_write_enable == 1'b1) begin - if (csr == 4 'h0) + if (csr == 5'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; - + bie <= csr_write_data[2]; + end - if (csr == 4 'h2) + if (csr == 5'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -12744,8 +13049,6 @@ endmodule - - @@ -12771,20 +13074,13 @@ endmodule - - - - - - - - - + + + + - - - + @@ -12922,25 +13218,24 @@ endmodule - - - + + - - - + + + @@ -13043,47 +13338,27 @@ endmodule - - - - - - - - - - - - - - - - - + + - - + - + - - - - @@ -13092,8 +13367,6 @@ endmodule - - @@ -13101,19 +13374,28 @@ endmodule + + - + + - + + + + + + + + - @@ -13271,7 +13553,7 @@ endmodule -module lm32_top_full_debug ( +module lm32_top_full ( clk_i, rst_i, @@ -13333,6 +13615,7 @@ module lm32_top_full_debug ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -13428,15 +13711,14 @@ wire [ (2-1):0] D_BTE_O; - -wire [ 7:0] jtag_reg_d; -wire [ 7:0] jtag_reg_q; -wire jtag_update; -wire [2:0] jtag_reg_addr_d; -wire [2:0] jtag_reg_addr_q; -wire jtck; -wire jrstn; + + + + + + + @@ -13515,7 +13797,10 @@ endfunction -lm32_cpu_full_debug cpu ( +lm32_cpu_full + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), @@ -13536,13 +13821,12 @@ lm32_cpu_full_debug cpu ( - - .jtag_clk (jtck), - .jtag_update (jtag_update), - .jtag_reg_q (jtag_reg_q), - .jtag_reg_addr_q (jtag_reg_addr_q), - + + + + + @@ -13571,10 +13855,9 @@ lm32_cpu_full_debug cpu ( + + - .jtag_reg_d (jtag_reg_d), - .jtag_reg_addr_d (jtag_reg_addr_d), - @@ -13609,21 +13892,20 @@ lm32_cpu_full_debug cpu ( .D_BTE_O (D_BTE_O) ); - - + -jtag_cores jtag_cores ( + - .reg_d (jtag_reg_d), - .reg_addr_d (jtag_reg_addr_d), + + - .reg_update (jtag_update), - .reg_q (jtag_reg_q), - .reg_addr_q (jtag_reg_addr_q), - .jtck (jtck), - .jrstn (jrstn) - ); - + + + + + + + endmodule @@ -13995,7 +14277,7 @@ endmodule -module lm32_mc_arithmetic_full_debug ( +module lm32_mc_arithmetic_full ( clk_i, rst_i, @@ -14661,7 +14943,7 @@ endmodule -module lm32_cpu_full_debug ( +module lm32_cpu_full ( clk_i, @@ -14682,13 +14964,12 @@ module lm32_cpu_full_debug ( - - jtag_clk, - jtag_update, - jtag_reg_q, - jtag_reg_addr_q, - + + + + + @@ -14717,10 +14998,9 @@ module lm32_cpu_full_debug ( + + - jtag_reg_d, - jtag_reg_addr_d, - @@ -14761,9 +15041,8 @@ module lm32_cpu_full_debug ( parameter eba_reset = 32'h00000000; + -parameter deba_reset = 32'h10000000; - @@ -14799,11 +15078,11 @@ parameter dcache_limit = 32'h7fffffff; + -parameter watchpoints = 32'h4; - - +parameter watchpoints = 0; + @@ -14845,12 +15124,11 @@ input [ (32-1):0] interrupt; + + + + -input jtag_clk; -input jtag_update; -input [ 7:0] jtag_reg_q; -input [2:0] jtag_reg_addr_q; - @@ -14890,12 +15168,11 @@ input D_RTY_I; + + + + -output [ 7:0] jtag_reg_d; -wire [ 7:0] jtag_reg_d; -output [2:0] jtag_reg_addr_d; -wire [2:0] jtag_reg_addr_d; - @@ -15078,15 +15355,14 @@ wire [ (5-1):0] write_idx_d; reg [ (5-1):0] write_idx_x; reg [ (5-1):0] write_idx_m; reg [ (5-1):0] write_idx_w; -wire [ (5-1):0] csr_d; -reg [ (5-1):0] csr_x; +wire [ (4 -1):0] csr_d; +reg [ (4 -1):0] csr_x; wire [ (3-1):0] condition_d; reg [ (3-1):0] condition_x; + + -wire break_d; -reg break_x; - wire scall_d; reg scall_x; @@ -15099,16 +15375,14 @@ wire eret_q_x; - -wire bret_d; -reg bret_x; -wire bret_q_x; - + + + + - wire csr_write_enable_d; reg csr_write_enable_x; @@ -15313,32 +15587,25 @@ wire stall_wb_load; - - - -wire [ (32-1):0] jtx_csr_read_data; -wire [ (32-1):0] jrx_csr_read_data; + + + + + + + - -wire jtag_csr_write_enable; -wire [ (32-1):0] jtag_csr_write_data; -wire [ (5-1):0] jtag_csr; -wire jtag_read_enable; -wire [ 7:0] jtag_read_data; -wire jtag_write_enable; -wire [ 7:0] jtag_write_data; -wire [ (32-1):0] jtag_address; -wire jtag_access_complete; - - -wire jtag_break; + + + + @@ -15371,9 +15638,8 @@ wire kill_w; reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba; + -reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba; - reg [ (3-1):0] eid_x; @@ -15383,41 +15649,36 @@ reg [ (3-1):0] eid_x; - - - -wire dc_ss; + -wire dc_re; -wire bp_match; -wire wp_match; -wire exception_x; -reg exception_m; -wire debug_exception_x; -reg debug_exception_m; -reg debug_exception_w; -wire debug_exception_q_w; -wire non_debug_exception_x; -reg non_debug_exception_m; -reg non_debug_exception_w; -wire non_debug_exception_q_w; + + + + + + + + +wire exception_x; +reg exception_m; +reg exception_w; +wire exception_q_w; + - - -wire reset_exception; + + - @@ -15425,10 +15686,9 @@ wire interrupt_exception; + + -wire breakpoint_exception; -wire watchpoint_exception; - @@ -15512,7 +15772,7 @@ endfunction -lm32_instruction_unit_full_debug #( +lm32_instruction_unit_full #( .eba_reset (eba_reset), .associativity (icache_associativity), .sets (icache_sets), @@ -15572,12 +15832,11 @@ lm32_instruction_unit_full_debug #( + + + + - .jtag_read_enable (jtag_read_enable), - .jtag_write_enable (jtag_write_enable), - .jtag_write_data (jtag_write_data), - .jtag_address (jtag_address), - @@ -15613,10 +15872,9 @@ lm32_instruction_unit_full_debug #( + + - .jtag_read_data (jtag_read_data), - .jtag_access_complete (jtag_access_complete), - @@ -15632,7 +15890,7 @@ lm32_instruction_unit_full_debug #( ); -lm32_decoder_full_debug decoder ( +lm32_decoder_full decoder ( .instruction (instruction_d), @@ -15713,16 +15971,14 @@ lm32_decoder_full_debug decoder ( .branch_reg (branch_reg_d), .condition (condition_d), + - .break_opcode (break_d), - .scall (scall_d), .eret (eret_d), + - .bret (bret_d), - @@ -15732,7 +15988,7 @@ lm32_decoder_full_debug decoder ( ); -lm32_load_store_unit_full_debug #( +lm32_load_store_unit_full #( .associativity (dcache_associativity), .sets (dcache_sets), .bytes_per_line (dcache_bytes_per_line), @@ -15868,7 +16124,7 @@ lm32_multiplier multiplier ( -lm32_mc_arithmetic_full_debug mc_arithmetic ( +lm32_mc_arithmetic_full mc_arithmetic ( .clk_i (clk_i), .rst_i (rst_i), @@ -15907,7 +16163,7 @@ lm32_mc_arithmetic_full_debug mc_arithmetic ( -lm32_interrupt_full_debug interrupt_unit ( +lm32_interrupt_full interrupt_unit ( .clk_i (clk_i), .rst_i (rst_i), @@ -15916,18 +16172,17 @@ lm32_interrupt_full_debug interrupt_unit ( .stall_x (stall_x), + + - .non_debug_exception (non_debug_exception_q_w), - .debug_exception (debug_exception_q_w), - - + .exception (exception_q_w), + .eret_q_x (eret_q_x), + - .bret_q_x (bret_q_x), - .csr (csr_x), .csr_write_data (operand_1_x), @@ -15942,117 +16197,95 @@ lm32_interrupt_full_debug interrupt_unit ( - -lm32_jtag_full_debug jtag ( + - .clk_i (clk_i), - .rst_i (rst_i), + + - .jtag_clk (jtag_clk), - .jtag_update (jtag_update), - .jtag_reg_q (jtag_reg_q), - .jtag_reg_addr_q (jtag_reg_addr_q), + + + + - - - .csr (csr_x), - .csr_write_data (operand_1_x), - .csr_write_enable (csr_write_enable_q_x), - .stall_x (stall_x), + + + + - - - .jtag_read_data (jtag_read_data), - .jtag_access_complete (jtag_access_complete), + + - - - .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), + - - - .jtx_csr_read_data (jtx_csr_read_data), - .jrx_csr_read_data (jrx_csr_read_data), + + - - - .jtag_csr_write_enable (jtag_csr_write_enable), - .jtag_csr_write_data (jtag_csr_write_data), - .jtag_csr (jtag_csr), - .jtag_read_enable (jtag_read_enable), - .jtag_write_enable (jtag_write_enable), - .jtag_write_data (jtag_write_data), - .jtag_address (jtag_address), + + + + + + + - - - .jtag_break (jtag_break), - .jtag_reset (reset_exception), + + - .jtag_reg_d (jtag_reg_d), - .jtag_reg_addr_d (jtag_reg_addr_d) - ); - - - - - - -lm32_debug_full_debug #( - .breakpoints (breakpoints), - .watchpoints (watchpoints) - ) hw_debug ( + + - .clk_i (clk_i), - .rst_i (rst_i), - .pc_x (pc_x), - .load_x (load_x), - .store_x (store_x), - .load_store_address_x (adder_result_x), - .csr_write_enable_x (csr_write_enable_q_x), - .csr_write_data (operand_1_x), - .csr_x (csr_x), - - .jtag_csr_write_enable (jtag_csr_write_enable), - .jtag_csr_write_data (jtag_csr_write_data), - .jtag_csr (jtag_csr), - - - .eret_q_x (eret_q_x), - .bret_q_x (bret_q_x), - .stall_x (stall_x), - .exception_x (exception_x), - .q_x (q_x), - .dcache_refill_request (dcache_refill_request), + + + + + + + + + + + + + + + + + + + + + + + + - - - .dc_ss (dc_ss), + + + + + + + - .dc_re (dc_re), - .bp_match (bp_match), - .wp_match (wp_match) - ); - @@ -16552,25 +16785,21 @@ assign kill_w = 1'b0 - -assign breakpoint_exception = ( ( (break_x == 1'b1) - || (bp_match == 1'b1) - ) - && (valid_x == 1'b1) - ) - - - || (jtag_break == 1'b1) + + + + + + + + - ; - + -assign watchpoint_exception = wp_match == 1'b1; - @@ -16597,17 +16826,38 @@ assign system_call_exception = ( (scall_x == 1'b1) ); + + + -assign debug_exception_x = (breakpoint_exception == 1'b1) - || (watchpoint_exception == 1'b1) - ; + + + -assign non_debug_exception_x = (system_call_exception == 1'b1) - + + + - || (reset_exception == 1'b1) + + + + + + + + + + + + + + + + + +assign exception_x = (system_call_exception == 1'b1) || (instruction_bus_error_exception == 1'b1) @@ -16623,9 +16873,8 @@ assign non_debug_exception_x = (system_call_exception == 1'b1) || ( (interrupt_exception == 1'b1) + - && (dc_ss == 1'b0) - @@ -16637,55 +16886,27 @@ assign non_debug_exception_x = (system_call_exception == 1'b1) ; - -assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1); - - - - - - - - - - - - - - - - - - - - - always @(*) begin - - - - if (reset_exception == 1'b1) - eid_x = 3'h0; - else + + + - - - if (data_bus_error_exception == 1'b1) - eid_x = 3'h4; - else + + + + + + + - if (breakpoint_exception == 1'b1) - eid_x = 3'd1; - else - @@ -16698,11 +16919,10 @@ begin + + + - if (watchpoint_exception == 1'b1) - eid_x = 3'd3; - else - @@ -16715,9 +16935,8 @@ begin if ( (interrupt_exception == 1'b1) + - && (dc_ss == 1'b0) - ) eid_x = 3'h6; @@ -16754,19 +16973,18 @@ assign stall_d = (stall_x == 1'b1) && (kill_d == 1'b0) ) + + + + + + + + + + + - || ( ( (break_d == 1'b1) - || (bret_d == 1'b1) - ) - && ( (load_q_x == 1'b1) - || (store_q_x == 1'b1) - || (load_q_m == 1'b1) - || (store_q_m == 1'b1) - || (D_CYC_O == 1'b1) - ) - && (kill_d == 1'b0) - ) - || ( (csr_write_enable_d == 1'b1) && (load_q_x == 1'b1) @@ -16872,24 +17090,21 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0); assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1); assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1); + -assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1); - assign load_q_x = (load_x == 1'b1) && (q_x == 1'b1) + - && (bp_match == 1'b0) - ; assign store_q_x = (store_x == 1'b1) && (q_x == 1'b1) + - && (bp_match == 1'b0) - ; @@ -16900,13 +17115,13 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0); assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1); assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1); - -assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1)); -assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1)); - + +assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1)); + + assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0); assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1); @@ -16921,12 +17136,12 @@ assign cfg = { breakpoints[3:0], interrupts[5:0], - - 1'b1, - + 1'b0, + + @@ -16935,19 +17150,19 @@ assign cfg = { - - 1'b1, - - - - 1'b1, + 1'b0, + + + 1'b0, + + 1'b1, @@ -17028,17 +17243,16 @@ assign cfg2 = { assign iflush = ( (csr_write_enable_d == 1'b1) - && (csr_d == 5'h3) + && (csr_d == 4 'h3) && (stall_d == 1'b0) && (kill_d == 1'b0) && (valid_d == 1'b1)) + + + - || - ( (jtag_csr_write_enable == 1'b1) - && (jtag_csr == 5'h3)) - ; @@ -17046,21 +17260,20 @@ assign iflush = ( (csr_write_enable_d == 1'b1) assign dflush_x = ( (csr_write_enable_q_x == 1'b1) - && (csr_x == 5'h4)) + && (csr_x == 4 'h4)) + + + - || - ( (jtag_csr_write_enable == 1'b1) - && (jtag_csr == 5'h4)) - ; -assign csr_d = read_idx_0_d[ (5-1):0]; +assign csr_d = read_idx_0_d[ (4 -1):0]; always @(*) @@ -17068,29 +17281,27 @@ begin case (csr_x) - 5'h0, - 5'h1, - 5'h2: csr_read_data_x = interrupt_csr_read_data_x; + 4 'h0, + 4 'h1, + 4 'h2: csr_read_data_x = interrupt_csr_read_data_x; - 5'h6: csr_read_data_x = cfg; - 5'h7: csr_read_data_x = {eba, 8'h00}; + 4 'h6: csr_read_data_x = cfg; + 4 'h7: csr_read_data_x = {eba, 8'h00}; + - 5'h9: csr_read_data_x = {deba, 8'h00}; - + + - 5'he: csr_read_data_x = jtx_csr_read_data; - 5'hf: csr_read_data_x = jrx_csr_read_data; - - 5'ha: csr_read_data_x = cfg2; + 4 'ha: csr_read_data_x = cfg2; default: csr_read_data_x = { 32{1'bx}}; endcase @@ -17107,37 +17318,33 @@ begin eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; else begin - if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0)) + if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0)) eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + - if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7)) - eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - end end + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - else - begin - if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0)) - deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - - - if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9)) - deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + + + + + + + + + + - end -end - @@ -17318,7 +17525,7 @@ begin m_bypass_enable_x <= 1'b0; write_enable_x <= 1'b0; write_idx_x <= { 5{1'b0}}; - csr_x <= { 5{1'b0}}; + csr_x <= { 4 {1'b0}}; load_x <= 1'b0; store_x <= 1'b0; size_x <= { 2{1'b0}}; @@ -17341,16 +17548,14 @@ begin branch_predict_taken_x <= 1'b0; condition_x <= 3'b000; + - break_x <= 1'b0; - scall_x <= 1'b0; eret_x <= 1'b0; + - bret_x <= 1'b0; - @@ -17389,10 +17594,9 @@ begin + + - debug_exception_m <= 1'b0; - non_debug_exception_m <= 1'b0; - operand_w <= { 32{1'b0}}; w_result_sel_load_w <= 1'b0; @@ -17404,13 +17608,13 @@ begin write_idx_w <= { 5{1'b0}}; write_enable_w <= 1'b0; - - debug_exception_w <= 1'b0; - non_debug_exception_w <= 1'b0; - + + exception_w <= 1'b0; + + memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; @@ -17489,9 +17693,8 @@ begin condition_x <= condition_d; csr_write_enable_x <= csr_write_enable_d; + - break_x <= break_d; - scall_x <= scall_d; @@ -17501,9 +17704,8 @@ begin eret_x <= eret_d; + - bret_x <= bret_d; - write_enable_x <= write_enable_d; end @@ -17550,40 +17752,40 @@ begin - - if (non_debug_exception_x == 1'b1) - write_idx_m <= 5'd30; - else if (debug_exception_x == 1'b1) - write_idx_m <= 5'd31; - else - write_idx_m <= write_idx_x; - - + + + + if (exception_x == 1'b1) + write_idx_m <= 5'd30; + else + write_idx_m <= write_idx_x; + + condition_met_m <= condition_met_x; + + + + + + + + + - if (exception_x == 1'b1) - if ((dc_re == 1'b1) - || ((debug_exception_x == 1'b1) - && (non_debug_exception_x == 1'b0))) - branch_target_m <= {deba, eid_x, {3{1'b0}}}; - else - branch_target_m <= {eba, eid_x, {3{1'b0}}}; - else - branch_target_m <= branch_target_x; - - + branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x; + @@ -17603,10 +17805,9 @@ begin write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x; + + - debug_exception_m <= debug_exception_x; - non_debug_exception_m <= non_debug_exception_x; - end @@ -17621,9 +17822,8 @@ begin data_bus_error_exception_m <= (data_bus_error_exception == 1'b1) + - && (reset_exception == 1'b0) - ; @@ -17655,13 +17855,13 @@ begin write_enable_w <= write_enable_m; - - debug_exception_w <= debug_exception_m; - non_debug_exception_w <= non_debug_exception_m; - + + exception_w <= exception_m; + + if ( (stall_m == 1'b0) @@ -18206,7 +18406,7 @@ endmodule -module lm32_load_store_unit_full_debug ( +module lm32_load_store_unit_full ( clk_i, rst_i, @@ -18584,7 +18784,7 @@ endfunction -lm32_dcache_full_debug #( +lm32_dcache_full #( .associativity (associativity), .sets (sets), .bytes_per_line (bytes_per_line), @@ -19536,7 +19736,7 @@ endmodule -module lm32_decoder_full_debug ( +module lm32_decoder_full ( instruction, @@ -19617,16 +19817,14 @@ module lm32_decoder_full_debug ( bi_conditional, bi_unconditional, + - break_opcode, - scall, eret, + - bret, - @@ -19762,20 +19960,18 @@ wire bi_conditional; output bi_unconditional; wire bi_unconditional; - -output break_opcode; -wire break_opcode; + + output scall; wire scall; output eret; wire eret; - -output bret; -wire bret; + + @@ -20230,16 +20426,14 @@ assign branch = bra | call; assign branch_reg = op_call | op_b; assign condition = instruction[28:26]; + -assign break_opcode = op_raise & ~instruction[2]; - assign scall = op_raise & instruction[2]; assign eret = op_b & (instruction[25:21] == 5'd30); + -assign bret = op_b & (instruction[25:21] == 5'd31); - @@ -20671,7 +20865,7 @@ endmodule -module lm32_icache_full_debug ( +module lm32_icache_full ( clk_i, rst_i, @@ -21517,7 +21711,7 @@ endmodule -module lm32_dcache_full_debug ( +module lm32_dcache_full ( clk_i, rst_i, @@ -22373,163 +22567,135 @@ endmodule + + + + + + - - - - - - - - - - - - -module lm32_debug_full_debug ( - clk_i, - rst_i, - pc_x, - load_x, - store_x, - load_store_address_x, - csr_write_enable_x, - csr_write_data, - csr_x, - - - jtag_csr_write_enable, - jtag_csr_write_data, - jtag_csr, + + + + + + + + + + + + - - - eret_q_x, - bret_q_x, - stall_x, - exception_x, - q_x, - - - dcache_refill_request, - + + + + + - - - dc_ss, - - dc_re, - bp_match, - wp_match - ); + + + + + + + -parameter breakpoints = 0; -parameter watchpoints = 0; + + -input clk_i; -input rst_i; -input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; -input load_x; -input store_x; -input [ (32-1):0] load_store_address_x; -input csr_write_enable_x; -input [ (32-1):0] csr_write_data; -input [ (5-1):0] csr_x; - + + -input jtag_csr_write_enable; -input [ (32-1):0] jtag_csr_write_data; -input [ (5-1):0] jtag_csr; + + + + + + + + + + - - -input eret_q_x; -input bret_q_x; -input stall_x; -input exception_x; -input q_x; - - -input dcache_refill_request; - + + + + + + - -output dc_ss; -reg dc_ss; + + -output dc_re; -reg dc_re; -output bp_match; -wire bp_match; -output wp_match; -wire wp_match; - - - + + + + + + -genvar i; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1]; -reg bp_e[0:breakpoints-1]; -wire [0:breakpoints-1]bp_match_n; + -reg [ 1:0] wpc_c[0:watchpoints-1]; -reg [ (32-1):0] wp[0:watchpoints-1]; -wire [0:watchpoints-1]wp_match_n; -wire debug_csr_write_enable; -wire [ (32-1):0] debug_csr_write_data; -wire [ (5-1):0] debug_csr; - + + + + + + -reg [ 2:0] state; + + + + - - + @@ -22537,15 +22703,48 @@ reg [ 2:0] state; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -22554,224 +22753,132 @@ reg [ 2:0] state; + + + - -function integer clogb2; -input [31:0] value; -begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; -end -endfunction + + + + + + + + + + + + + + + -function integer clogb2_v1; -input [31:0] value; -reg [31:0] i; -reg [31:0] temp; -begin - temp = 0; - i = 0; - for (i = 0; temp < value; i = i + 1) - temp = 1< 0) -assign bp_match = (|bp_match_n) || (state == 3'b011); - else -assign bp_match = state == 3'b011; - - - - + -endgenerate + + + + + + + - -generate - for (i = 0; i < watchpoints; i = i + 1) - begin : wp_comb -assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); - end -endgenerate -generate - if (watchpoints > 0) -assign wp_match = |wp_match_n; - else -assign wp_match = 1'b0; -endgenerate - - + + - -assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1); -assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data; -assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x; + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - -generate - for (i = 0; i < breakpoints; i = i + 1) - begin : bp_seq -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}}; - bp_e[i] <= 1'b0; - end - else - begin - if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i)) - begin - bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]; - bp_e[i] <= debug_csr_write_data[0]; - end - end -end - end -endgenerate - - -generate - for (i = 0; i < watchpoints; i = i + 1) - begin : wp_seq -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - wp[i] <= { 32{1'bx}}; - wpc_c[i] <= 2'b00; - end - else - begin - if (debug_csr_write_enable == 1'b1) - begin - if (debug_csr == 5'h8) - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; - if (debug_csr == 5'h18 + i) - wp[i] <= debug_csr_write_data; - end - end -end - end -endgenerate - - -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - dc_re <= 1'b0; - else - begin - if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) - dc_re <= debug_csr_write_data[1]; - end -end - - - + + + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - state <= 3'b000; - dc_ss <= 1'b0; - end - else - begin - if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) - begin - dc_ss <= debug_csr_write_data[0]; - if (debug_csr_write_data[0] == 1'b0) - state <= 3'b000; - else - state <= 3'b001; - end - case (state) - 3'b001: - begin + - if ( ( (eret_q_x == 1'b1) - || (bret_q_x == 1'b1) - ) - && (stall_x == 1'b0) - ) - state <= 3'b010; - end - 3'b010: - begin + + - if ((q_x == 1'b1) && (stall_x == 1'b0)) - state <= 3'b011; - end - 3'b011: - begin + + + - - - if (dcache_refill_request == 1'b1) - state <= 3'b010; - else + + + + + + + + - if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0)) - begin - dc_ss <= 1'b0; - state <= 3'b100; - end - end - 3'b100: - begin - - - if (dcache_refill_request == 1'b1) - state <= 3'b010; - else - - state <= 3'b000; - end - endcase - end -end - -endmodule - @@ -23144,7 +23251,7 @@ endmodule -module lm32_instruction_unit_full_debug ( +module lm32_instruction_unit_full ( clk_i, rst_i, @@ -23197,12 +23304,11 @@ module lm32_instruction_unit_full_debug ( + + + + - jtag_read_enable, - jtag_write_enable, - jtag_write_data, - jtag_address, - @@ -23238,10 +23344,9 @@ module lm32_instruction_unit_full_debug ( + + - jtag_read_data, - jtag_access_complete, - @@ -23333,12 +23438,11 @@ input i_rty_i; + + + + -input jtag_read_enable; -input jtag_write_enable; -input [ 7:0] jtag_write_data; -input [ (32-1):0] jtag_address; - @@ -23379,11 +23483,11 @@ wire icache_refilling; output [ (32-1):0] i_dat_o; + -reg [ (32-1):0] i_dat_o; - - +wire [ (32-1):0] i_dat_o; + output [ (32-1):0] i_adr_o; reg [ (32-1):0] i_adr_o; @@ -23391,21 +23495,21 @@ output i_cyc_o; reg i_cyc_o; output [ (4-1):0] i_sel_o; + -reg [ (4-1):0] i_sel_o; - - +wire [ (4-1):0] i_sel_o; + output i_stb_o; reg i_stb_o; output i_we_o; + -reg i_we_o; - - +wire i_we_o; + output [ (3-1):0] i_cti_o; reg [ (3-1):0] i_cti_o; @@ -23417,12 +23521,11 @@ wire [ (2-1):0] i_bte_o; + + + + -output [ 7:0] jtag_read_data; -reg [ 7:0] jtag_read_data; -output jtag_access_complete; -wire jtag_access_complete; - @@ -23488,9 +23591,8 @@ reg bus_error_f; + -reg jtag_access; - @@ -23608,7 +23710,7 @@ endfunction -lm32_icache_full_debug #( +lm32_icache_full #( .associativity (associativity), .sets (sets), .bytes_per_line (bytes_per_line), @@ -23731,11 +23833,11 @@ assign instruction_f = icache_data_f; - - - - +assign i_dat_o = 32'd0; +assign i_we_o = 1'b0; +assign i_sel_o = 4'b1111; + assign i_bte_o = 2'b00; @@ -23852,18 +23954,17 @@ end - -assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1); -always @(*) -begin - case (jtag_address[1:0]) - 2'b00: jtag_read_data = i_dat_i[ 31:24]; - 2'b01: jtag_read_data = i_dat_i[ 23:16]; - 2'b10: jtag_read_data = i_dat_i[ 15:8]; - 2'b11: jtag_read_data = i_dat_i[ 7:0]; - endcase -end + + + + + + + + + + @@ -23888,11 +23989,10 @@ begin + + + - i_we_o <= 1'b0; - i_sel_o <= 4'b1111; - jtag_access <= 1'b0; - end else @@ -23905,16 +24005,15 @@ begin if ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) begin + + + + + + + + - if (jtag_access == 1'b1) - begin - i_cyc_o <= 1'b0; - i_stb_o <= 1'b0; - i_we_o <= 1'b0; - jtag_access <= 1'b0; - end - else - begin if (last_word == 1'b1) @@ -23947,10 +24046,9 @@ begin if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0)) begin - - - i_sel_o <= 4'b1111; - + + + i_adr_o <= {first_address, 2'b00}; i_cyc_o <= 1'b1; @@ -23964,27 +24062,26 @@ begin end + + + + + + + + + + + + + + + + + + + - else - begin - if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1)) - begin - case (jtag_address[1:0]) - 2'b00: i_sel_o <= 4'b1000; - 2'b01: i_sel_o <= 4'b0100; - 2'b10: i_sel_o <= 4'b0010; - 2'b11: i_sel_o <= 4'b0001; - endcase - i_adr_o <= jtag_address; - i_dat_o <= {4{jtag_write_data}}; - i_cyc_o <= 1'b1; - i_stb_o <= 1'b1; - i_we_o <= jtag_write_enable; - i_cti_o <= 3'b111; - jtag_access <= 1'b1; - end - end - @@ -24459,523 +24556,443 @@ endmodule + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + - - + + + + + + + + + + - - - - - - - - - - -module lm32_jtag_full_debug ( - clk_i, - rst_i, - jtag_clk, - jtag_update, - jtag_reg_q, - jtag_reg_addr_q, - - - csr, - csr_write_enable, - csr_write_data, - stall_x, + + + + + + + + + + - - - jtag_read_data, - jtag_access_complete, + + - - - exception_q_w, - - - jtx_csr_read_data, - jrx_csr_read_data, + + + - - - jtag_csr_write_enable, - jtag_csr_write_data, - jtag_csr, - jtag_read_enable, - jtag_write_enable, - jtag_write_data, - jtag_address, + + + + + + + - - - jtag_break, - jtag_reset, + + - jtag_reg_d, - jtag_reg_addr_d - ); - + + + -input clk_i; -input rst_i; -input jtag_clk; -input jtag_update; -input [ 7:0] jtag_reg_q; -input [2:0] jtag_reg_addr_q; + + - + + + + -input [ (5-1):0] csr; -input csr_write_enable; -input [ (32-1):0] csr_write_data; -input stall_x; + + + + - - -input [ 7:0] jtag_read_data; -input jtag_access_complete; + + - - -input exception_q_w; + - - -output [ (32-1):0] jtx_csr_read_data; -wire [ (32-1):0] jtx_csr_read_data; -output [ (32-1):0] jrx_csr_read_data; -wire [ (32-1):0] jrx_csr_read_data; + + + + - - -output jtag_csr_write_enable; -reg jtag_csr_write_enable; -output [ (32-1):0] jtag_csr_write_data; -wire [ (32-1):0] jtag_csr_write_data; -output [ (5-1):0] jtag_csr; -wire [ (5-1):0] jtag_csr; -output jtag_read_enable; -reg jtag_read_enable; -output jtag_write_enable; -reg jtag_write_enable; -output [ 7:0] jtag_write_data; -wire [ 7:0] jtag_write_data; -output [ (32-1):0] jtag_address; -wire [ (32-1):0] jtag_address; + + + + + + + + + + + + + + - - -output jtag_break; -reg jtag_break; -output jtag_reset; -reg jtag_reset; + + + + -output [ 7:0] jtag_reg_d; -reg [ 7:0] jtag_reg_d; -output [2:0] jtag_reg_addr_d; -wire [2:0] jtag_reg_addr_d; + + + + -reg rx_update; -reg rx_update_r; -reg rx_update_r_r; -reg rx_update_r_r_r; - + + + + -wire [ 7:0] rx_byte; -wire [2:0] rx_addr; + - -reg [ 7:0] uart_tx_byte; -reg uart_tx_valid; -reg [ 7:0] uart_rx_byte; -reg uart_rx_valid; - + + + + + -reg [ 3:0] command; - -reg [ 7:0] jtag_byte_0; -reg [ 7:0] jtag_byte_1; -reg [ 7:0] jtag_byte_2; -reg [ 7:0] jtag_byte_3; -reg [ 7:0] jtag_byte_4; -reg processing; + + + + + + + -reg [ 3:0] state; - + - -assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; -assign jtag_csr = jtag_byte_4[ (5-1):0]; -assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; -assign jtag_write_data = jtag_byte_4; + + + + - - -assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; - - - + + - + -assign jtag_reg_addr_d[2] = processing; + - - -assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00}; -assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte}; - + + + -assign rx_byte = jtag_reg_q; -assign rx_addr = jtag_reg_addr_q; + + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - rx_update <= 1'b0; - rx_update_r <= 1'b0; - rx_update_r_r <= 1'b0; - rx_update_r_r_r <= 1'b0; - end - else - begin - rx_update <= jtag_update; - rx_update_r <= rx_update; - rx_update_r_r <= rx_update_r; - rx_update_r_r_r <= rx_update_r_r; - end -end + + + + + + + + + + + + + + + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - state <= 4'h0; - command <= 4'b0000; - jtag_reg_d <= 8'h00; - - processing <= 1'b0; - jtag_csr_write_enable <= 1'b0; - jtag_read_enable <= 1'b0; - jtag_write_enable <= 1'b0; - - + - jtag_break <= 1'b0; - jtag_reset <= 1'b0; + + + + + + + + + - - - uart_tx_byte <= 8'h00; - uart_tx_valid <= 1'b0; - uart_rx_byte <= 8'h00; - uart_rx_valid <= 1'b0; + + - end - else - begin - - - if ((csr_write_enable == 1'b1) && (stall_x == 1'b0)) - begin - case (csr) - 5'he: - begin + + + + + + + + + + + + + + + - uart_tx_byte <= csr_write_data[ 7:0]; - uart_tx_valid <= 1'b1; - end - 5'hf: - begin + + + + + - uart_rx_valid <= 1'b0; - end - endcase - end - - - + + + + + + + + + + - if (exception_q_w == 1'b1) - begin - jtag_break <= 1'b0; - jtag_reset <= 1'b0; - end - - case (state) - 4'h0: - begin + + + - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - command <= rx_byte[7:4]; - case (rx_addr) - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - 3'b000: - begin - case (rx_byte[7:4]) - + + + + + + + - 4'b0001: - state <= 4'h1; - 4'b0011: - begin - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; - state <= 4'h6; - end - 4'b0010: - state <= 4'h1; - 4'b0100: - begin - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; - state <= 5; - end - 4'b0101: - state <= 4'h1; - + - 4'b0110: - begin - - - uart_rx_valid <= 1'b0; - uart_tx_valid <= 1'b0; - + + - jtag_break <= 1'b1; - end - 4'b0111: - begin - - - uart_rx_valid <= 1'b0; - uart_tx_valid <= 1'b0; - + + + + + + + + + + + - jtag_reset <= 1'b1; - end - endcase - end + + + + + - - + + - 3'b001: - begin - uart_rx_byte <= rx_byte; - uart_rx_valid <= 1'b1; - end - 3'b010: - begin - jtag_reg_d <= uart_tx_byte; - uart_tx_valid <= 1'b0; - end - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - default: - ; - endcase - end - end - 4'h1: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_0 <= rx_byte; - state <= 4'h2; - end - end - 4'h2: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_1 <= rx_byte; - state <= 4'h3; - end - end - 4'h3: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_2 <= rx_byte; - state <= 4'h4; - end - end - 4'h4: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_3 <= rx_byte; - if (command == 4'b0001) - state <= 4'h6; - else - state <= 4'h5; - end - end - 4'h5: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_4 <= rx_byte; - state <= 4'h6; - end - end - 4'h6: - begin - case (command) - 4'b0001, - 4'b0011: - begin - jtag_read_enable <= 1'b1; - processing <= 1'b1; - state <= 4'h7; - end - 4'b0010, - 4'b0100: - begin - jtag_write_enable <= 1'b1; - processing <= 1'b1; - state <= 4'h7; - end - 4'b0101: - begin - jtag_csr_write_enable <= 1'b1; - processing <= 1'b1; - state <= 4'h8; - end - endcase - end - 4'h7: - begin - if (jtag_access_complete == 1'b1) - begin - jtag_read_enable <= 1'b0; - jtag_reg_d <= jtag_read_data; - jtag_write_enable <= 1'b0; - processing <= 1'b0; - state <= 4'h0; - end - end - 4'h8: - begin - jtag_csr_write_enable <= 1'b0; - processing <= 1'b0; - state <= 4'h0; - end - - endcase - end -end - -endmodule - @@ -25330,7 +25347,7 @@ endmodule -module lm32_interrupt_full_debug ( +module lm32_interrupt_full ( clk_i, rst_i, @@ -25339,18 +25356,17 @@ module lm32_interrupt_full_debug ( stall_x, - - non_debug_exception, - debug_exception, - + + + exception, + eret_q_x, + - bret_q_x, - csr, csr_write_data, @@ -25379,21 +25395,20 @@ input [interrupts-1:0] interrupt; input stall_x; + + -input non_debug_exception; -input debug_exception; - - +input exception; + input eret_q_x; + -input bret_q_x; - -input [ (5-1):0] csr; +input [ (4 -1):0] csr; input [ (32-1):0] csr_write_data; input csr_write_enable; @@ -25420,9 +25435,8 @@ wire [interrupts-1:0] interrupt_n_exception; reg ie; reg eie; + -reg bie; - reg [interrupts-1:0] ip; reg [interrupts-1:0] im; @@ -25447,19 +25461,19 @@ generate always @(*) begin case (csr) - 5'h0: csr_read_data = {{ 32-3{1'b0}}, + 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + - bie, - - + 1'b0, + eie, ie }; - 5'h2: csr_read_data = ip; - 5'h1: csr_read_data = im; + 4 'h2: csr_read_data = ip; + 4 'h1: csr_read_data = im; default: csr_read_data = { 32{1'bx}}; endcase end @@ -25470,18 +25484,18 @@ end always @(*) begin case (csr) - 5'h0: csr_read_data = {{ 32-3{1'b0}}, + 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + - bie, - - + 1'b0, + eie, ie }; - 5'h2: csr_read_data = ip; + 4 'h2: csr_read_data = ip; default: csr_read_data = { 32{1'bx}}; endcase end @@ -25510,9 +25524,8 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; + - bie <= 1'b0; - im <= {interrupts{1'b0}}; ip <= {interrupts{1'b0}}; @@ -25524,21 +25537,13 @@ always @(posedge clk_i ) ip <= asserted; - - if (non_debug_exception == 1'b1) - begin + + - eie <= ie; - ie <= 1'b0; - end - else if (debug_exception == 1'b1) - begin + + + - bie <= ie; - ie <= 1'b0; - end - - @@ -25546,6 +25551,14 @@ always @(posedge clk_i ) + if (exception == 1'b1) + begin + + eie <= ie; + ie <= 1'b0; + end + + else if (stall_x == 1'b0) begin @@ -25563,28 +25576,26 @@ always @(posedge clk_i ) - - else if (bret_q_x == 1'b1) - ie <= bie; - + + + else if (csr_write_enable == 1'b1) begin - if (csr == 5'h0) + if (csr == 4 'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; + - bie <= csr_write_data[2]; - end - if (csr == 5'h1) + if (csr == 4 'h1) im <= csr_write_data[interrupts-1:0]; - if (csr == 5'h2) + if (csr == 4 'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -25601,9 +25612,8 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; + - bie <= 1'b0; - ip <= {interrupts{1'b0}}; eie_delay <= 0; @@ -25613,21 +25623,13 @@ always @(posedge clk_i ) ip <= asserted; - - if (non_debug_exception == 1'b1) - begin + + - eie <= ie; - ie <= 1'b0; - end - else if (debug_exception == 1'b1) - begin + + + - bie <= ie; - ie <= 1'b0; - end - - @@ -25635,6 +25637,14 @@ always @(posedge clk_i ) + if (exception == 1'b1) + begin + + eie <= ie; + ie <= 1'b0; + end + + else if (stall_x == 1'b0) begin @@ -25650,26 +25660,24 @@ always @(posedge clk_i ) end - - else if (bret_q_x == 1'b1) - ie <= bie; - + + + else if (csr_write_enable == 1'b1) begin - if (csr == 5'h0) + if (csr == 4 'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; + - bie <= csr_write_data[2]; - end - if (csr == 5'h2) + if (csr == 4 'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -25726,6 +25734,10 @@ endmodule + + + + @@ -25751,13 +25763,20 @@ endmodule - - - - + + - + + + + + + + + + + @@ -25857,18 +25876,16 @@ endmodule - - - - + + + - @@ -25897,24 +25914,25 @@ endmodule - + + - - + + + + - - @@ -26015,24 +26033,34 @@ endmodule - - + + + + + + + + + + - + - + + + @@ -26044,6 +26072,8 @@ endmodule + + @@ -26051,28 +26081,29 @@ endmodule - - + - - + + + + + + + + + + + - - - - - - - - + @@ -26133,14 +26164,14 @@ endmodule - - + + + - @@ -26230,7 +26261,7 @@ endmodule -module lm32_top_medium ( +module lm32_top_medium_debug ( clk_i, rst_i, @@ -26292,6 +26323,7 @@ module lm32_top_medium ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -26387,14 +26419,15 @@ wire [ (2-1):0] D_BTE_O; - - - - - - - +wire [ 7:0] jtag_reg_d; +wire [ 7:0] jtag_reg_q; +wire jtag_update; +wire [2:0] jtag_reg_addr_d; +wire [2:0] jtag_reg_addr_q; +wire jtck; +wire jrstn; + @@ -26473,7 +26506,10 @@ endfunction -lm32_cpu_medium cpu ( +lm32_cpu_medium_debug + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), @@ -26494,12 +26530,13 @@ lm32_cpu_medium cpu ( - - - - - + + .jtag_clk (jtck), + .jtag_update (jtag_update), + .jtag_reg_q (jtag_reg_q), + .jtag_reg_addr_q (jtag_reg_addr_q), + @@ -26528,9 +26565,10 @@ lm32_cpu_medium cpu ( - - + .jtag_reg_d (jtag_reg_d), + .jtag_reg_addr_d (jtag_reg_addr_d), + @@ -26565,20 +26603,21 @@ lm32_cpu_medium cpu ( .D_BTE_O (D_BTE_O) ); - - + + +jtag_cores jtag_cores ( - - - - - - - - + .reg_d (jtag_reg_d), + .reg_addr_d (jtag_reg_addr_d), - + .reg_update (jtag_update), + .reg_q (jtag_reg_q), + .reg_addr_q (jtag_reg_addr_q), + .jtck (jtck), + .jrstn (jrstn) + ); + endmodule @@ -26950,7 +26989,7 @@ endmodule -module lm32_mc_arithmetic_medium ( +module lm32_mc_arithmetic_medium_debug ( clk_i, rst_i, @@ -27606,7 +27645,7 @@ endmodule -module lm32_cpu_medium ( +module lm32_cpu_medium_debug ( clk_i, @@ -27627,12 +27666,13 @@ module lm32_cpu_medium ( - - - - - + + jtag_clk, + jtag_update, + jtag_reg_q, + jtag_reg_addr_q, + @@ -27661,9 +27701,10 @@ module lm32_cpu_medium ( - - + jtag_reg_d, + jtag_reg_addr_d, + @@ -27704,24 +27745,25 @@ module lm32_cpu_medium ( parameter eba_reset = 32'h00000000; - +parameter deba_reset = 32'h10000000; + - - - - - - -parameter icache_associativity = 1; -parameter icache_sets = 512; -parameter icache_bytes_per_line = 16; -parameter icache_base_address = 0; -parameter icache_limit = 0; +parameter icache_associativity = 1; +parameter icache_sets = 256; +parameter icache_bytes_per_line = 16; +parameter icache_base_address = 32'h0; +parameter icache_limit = 32'h7fffffff; + + + + + + @@ -27741,11 +27783,11 @@ parameter dcache_limit = 0; - - -parameter watchpoints = 0; +parameter watchpoints = 32'h4; + + @@ -27787,11 +27829,12 @@ input [ (32-1):0] interrupt; - - - - +input jtag_clk; +input jtag_update; +input [ 7:0] jtag_reg_q; +input [2:0] jtag_reg_addr_q; + @@ -27831,11 +27874,12 @@ input D_RTY_I; - - - - +output [ 7:0] jtag_reg_d; +wire [ 7:0] jtag_reg_d; +output [2:0] jtag_reg_addr_d; +wire [2:0] jtag_reg_addr_d; + @@ -27899,8 +27943,9 @@ wire [ (2-1):0] D_BTE_O; - +reg valid_a; + reg valid_f; reg valid_d; @@ -27926,8 +27971,8 @@ reg [ 1:0] size_x; wire branch_d; wire branch_predict_d; wire branch_predict_taken_d; -wire [ ((32-2)+2-1):2] branch_predict_address_d; -wire [ ((32-2)+2-1):2] branch_target_d; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d; wire bi_unconditional; wire bi_conditional; reg branch_x; @@ -27939,9 +27984,9 @@ reg branch_predict_taken_m; wire branch_mispredict_taken_m; wire branch_flushX_m; wire branch_reg_d; -wire [ ((32-2)+2-1):2] branch_offset_d; -reg [ ((32-2)+2-1):2] branch_target_x; -reg [ ((32-2)+2-1):2] branch_target_m; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m; wire [ 0:0] d_result_sel_0_d; wire [ 1:0] d_result_sel_1_d; @@ -28016,14 +28061,15 @@ wire [ (5-1):0] write_idx_d; reg [ (5-1):0] write_idx_x; reg [ (5-1):0] write_idx_m; reg [ (5-1):0] write_idx_w; -wire [ (4 -1):0] csr_d; -reg [ (4 -1):0] csr_x; +wire [ (5-1):0] csr_d; +reg [ (5-1):0] csr_x; wire [ (3-1):0] condition_d; reg [ (3-1):0] condition_x; - - +wire break_d; +reg break_x; + wire scall_d; reg scall_x; @@ -28036,14 +28082,16 @@ wire eret_q_x; - - - - + +wire bret_d; +reg bret_x; +wire bret_q_x; + + wire csr_write_enable_d; reg csr_write_enable_x; @@ -28194,11 +28242,11 @@ wire [ (32-1):0] cfg2; reg [ (32-1):0] csr_read_data_x; -wire [ ((32-2)+2-1):2] pc_f; -wire [ ((32-2)+2-1):2] pc_d; -wire [ ((32-2)+2-1):2] pc_x; -wire [ ((32-2)+2-1):2] pc_m; -wire [ ((32-2)+2-1):2] pc_w; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w; @@ -28212,12 +28260,13 @@ wire [ (32-1):0] instruction_f; wire [ (32-1):0] instruction_d; - - - - - +wire iflush; +wire icache_stall_request; +wire icache_restart_request; +wire icache_refill_request; +wire icache_refilling; + @@ -28243,25 +28292,32 @@ wire stall_wb_load; - - - - - - - - + +wire [ (32-1):0] jtx_csr_read_data; +wire [ (32-1):0] jrx_csr_read_data; + - - +wire jtag_csr_write_enable; +wire [ (32-1):0] jtag_csr_write_data; +wire [ (5-1):0] jtag_csr; +wire jtag_read_enable; +wire [ 7:0] jtag_read_data; +wire jtag_write_enable; +wire [ 7:0] jtag_write_data; +wire [ (32-1):0] jtag_address; +wire jtag_access_complete; - + + +wire jtag_break; + + @@ -28291,10 +28347,11 @@ wire kill_x; wire kill_m; wire kill_w; -reg [ (32-2)+2-1:8] eba; +reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba; - +reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba; + reg [ (3-1):0] eid_x; @@ -28304,36 +28361,41 @@ reg [ (3-1):0] eid_x; - - - + + +wire dc_ss; + +wire dc_re; +wire bp_match; +wire wp_match; +wire exception_x; +reg exception_m; +wire debug_exception_x; +reg debug_exception_m; +reg debug_exception_w; +wire debug_exception_q_w; +wire non_debug_exception_x; +reg non_debug_exception_m; +reg non_debug_exception_w; +wire non_debug_exception_q_w; - - - - - - -wire exception_x; -reg exception_m; -reg exception_w; -wire exception_q_w; - + - - +wire reset_exception; + + @@ -28341,9 +28403,10 @@ wire interrupt_exception; - - +wire breakpoint_exception; +wire watchpoint_exception; + @@ -28424,7 +28487,7 @@ endfunction -lm32_instruction_unit_medium #( +lm32_instruction_unit_medium_debug #( .eba_reset (eba_reset), .associativity (icache_associativity), .sets (icache_sets), @@ -28456,8 +28519,9 @@ lm32_instruction_unit_medium #( .branch_mispredict_taken_m (branch_mispredict_taken_m), .branch_target_m (branch_target_m), - + .iflush (iflush), + @@ -28481,11 +28545,12 @@ lm32_instruction_unit_medium #( - - - - + .jtag_read_enable (jtag_read_enable), + .jtag_write_enable (jtag_write_enable), + .jtag_write_data (jtag_write_data), + .jtag_address (jtag_address), + @@ -28495,11 +28560,12 @@ lm32_instruction_unit_medium #( .pc_m (pc_m), .pc_w (pc_w), - - - - + .icache_stall_request (icache_stall_request), + .icache_restart_request (icache_restart_request), + .icache_refill_request (icache_refill_request), + .icache_refilling (icache_refilling), + @@ -28520,9 +28586,10 @@ lm32_instruction_unit_medium #( - - + .jtag_read_data (jtag_read_data), + .jtag_access_complete (jtag_access_complete), + @@ -28537,7 +28604,7 @@ lm32_instruction_unit_medium #( ); -lm32_decoder_medium decoder ( +lm32_decoder_medium_debug decoder ( .instruction (instruction_d), @@ -28616,14 +28683,16 @@ lm32_decoder_medium decoder ( .branch_reg (branch_reg_d), .condition (condition_d), - + .break_opcode (break_d), + .scall (scall_d), .eret (eret_d), - + .bret (bret_d), + @@ -28633,7 +28702,7 @@ lm32_decoder_medium decoder ( ); -lm32_load_store_unit_medium #( +lm32_load_store_unit_medium_debug #( .associativity (dcache_associativity), .sets (dcache_sets), .bytes_per_line (dcache_bytes_per_line), @@ -28799,7 +28868,7 @@ lm32_multiplier multiplier ( -lm32_interrupt_medium interrupt_unit ( +lm32_interrupt_medium_debug interrupt_unit ( .clk_i (clk_i), .rst_i (rst_i), @@ -28808,17 +28877,18 @@ lm32_interrupt_medium interrupt_unit ( .stall_x (stall_x), - - - - .exception (exception_q_w), + .non_debug_exception (non_debug_exception_q_w), + .debug_exception (debug_exception_q_w), + + .eret_q_x (eret_q_x), - + .bret_q_x (bret_q_x), + .csr (csr_x), .csr_write_data (operand_1_x), @@ -28833,95 +28903,116 @@ lm32_interrupt_medium interrupt_unit ( - + +lm32_jtag_medium_debug jtag ( - - + .clk_i (clk_i), + .rst_i (rst_i), - - - - + .jtag_clk (jtag_clk), + .jtag_update (jtag_update), + .jtag_reg_q (jtag_reg_q), + .jtag_reg_addr_q (jtag_reg_addr_q), + + + .csr (csr_x), + .csr_write_data (operand_1_x), + .csr_write_enable (csr_write_enable_q_x), + .stall_x (stall_x), - - - - + + + .jtag_read_data (jtag_read_data), + .jtag_access_complete (jtag_access_complete), - - + + + .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), - + + + .jtx_csr_read_data (jtx_csr_read_data), + .jrx_csr_read_data (jrx_csr_read_data), - - + + + .jtag_csr_write_enable (jtag_csr_write_enable), + .jtag_csr_write_data (jtag_csr_write_data), + .jtag_csr (jtag_csr), + .jtag_read_enable (jtag_read_enable), + .jtag_write_enable (jtag_write_enable), + .jtag_write_data (jtag_write_data), + .jtag_address (jtag_address), - - - - - - - + + + .jtag_break (jtag_break), + .jtag_reset (reset_exception), - - - - - - + .jtag_reg_d (jtag_reg_d), + .jtag_reg_addr_d (jtag_reg_addr_d) + ); + - - - - + +lm32_debug_medium_debug #( + .breakpoints (breakpoints), + .watchpoints (watchpoints) + ) hw_debug ( - - - - - - - - - - - - - + .clk_i (clk_i), + .rst_i (rst_i), + .pc_x (pc_x), + .load_x (load_x), + .store_x (store_x), + .load_store_address_x (adder_result_x), + .csr_write_enable_x (csr_write_enable_q_x), + .csr_write_data (operand_1_x), + .csr_x (csr_x), + + .jtag_csr_write_enable (jtag_csr_write_enable), + .jtag_csr_write_data (jtag_csr_write_data), + .jtag_csr (jtag_csr), - - - - - - + + + + .eret_q_x (eret_q_x), + .bret_q_x (bret_q_x), + .stall_x (stall_x), + .exception_x (exception_x), + .q_x (q_x), + - - - - - + + .dc_ss (dc_ss), + + + .dc_re (dc_re), + .bp_match (bp_match), + .wp_match (wp_match) + ); + @@ -29366,8 +29457,9 @@ assign kill_f = ( (valid_d == 1'b1) - + || (icache_refill_request == 1'b1) + @@ -29380,8 +29472,9 @@ assign kill_d = (branch_taken_m == 1'b1) - + || (icache_refill_request == 1'b1) + @@ -29410,21 +29503,25 @@ assign kill_w = 1'b0 - - - - - - - - +assign breakpoint_exception = ( ( (break_x == 1'b1) + || (bp_match == 1'b1) + ) + && (valid_x == 1'b1) + ) + + || (jtag_break == 1'b1) + + + ; + - +assign watchpoint_exception = wp_match == 1'b1; + @@ -29448,38 +29545,17 @@ assign system_call_exception = ( (scall_x == 1'b1) ); - - - - - - - - - - +assign debug_exception_x = (breakpoint_exception == 1'b1) + || (watchpoint_exception == 1'b1) + ; - - +assign non_debug_exception_x = (system_call_exception == 1'b1) + + || (reset_exception == 1'b1) - - - - - - - - - - - - - - -assign exception_x = (system_call_exception == 1'b1) @@ -29493,8 +29569,9 @@ assign exception_x = (system_call_exception == 1'b1) || ( (interrupt_exception == 1'b1) - + && (dc_ss == 1'b0) + @@ -29505,27 +29582,54 @@ assign exception_x = (system_call_exception == 1'b1) ; + +assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1); + + + + + + + + + + + + + + + + + + + + + always @(*) begin + + + + if (reset_exception == 1'b1) + eid_x = 3'h0; + else - - - - + - - - + if (breakpoint_exception == 1'b1) + eid_x = 3'd1; + else + @@ -29537,10 +29641,11 @@ begin - - - + if (watchpoint_exception == 1'b1) + eid_x = 3'd3; + else + @@ -29552,8 +29657,9 @@ begin if ( (interrupt_exception == 1'b1) - + && (dc_ss == 1'b0) + ) eid_x = 3'h6; @@ -29589,18 +29695,19 @@ assign stall_d = (stall_x == 1'b1) && (kill_d == 1'b0) ) - - - - - - - - - - - + || ( ( (break_d == 1'b1) + || (bret_d == 1'b1) + ) + && ( (load_q_x == 1'b1) + || (store_q_x == 1'b1) + || (load_q_m == 1'b1) + || (store_q_m == 1'b1) + || (D_CYC_O == 1'b1) + ) + && (kill_d == 1'b0) + ) + || ( (csr_write_enable_d == 1'b1) && (load_q_x == 1'b1) @@ -29662,16 +29769,14 @@ assign stall_m = (stall_wb_load == 1'b1) - - - - - - || (I_CYC_O == 1'b1) + || (icache_stall_request == 1'b1) + || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1))) - + + + @@ -29704,21 +29809,24 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0); assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1); assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1); - +assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1); + assign load_q_x = (load_x == 1'b1) && (q_x == 1'b1) - + && (bp_match == 1'b0) + ; assign store_q_x = (store_x == 1'b1) && (q_x == 1'b1) - + && (bp_match == 1'b0) + ; @@ -29729,12 +29837,12 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0); assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1); assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1); - - - -assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1)); +assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1)); +assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1)); + + assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0); @@ -29750,19 +29858,12 @@ assign cfg = { breakpoints[3:0], interrupts[5:0], - - - 1'b0, + 1'b1, - - - 1'b0, - - @@ -29771,18 +29872,25 @@ assign cfg = { - - - 1'b0, + 1'b1, + + + + 1'b1, + - 1'b0, + + + 1'b1, + + @@ -29855,19 +29963,22 @@ assign cfg2 = { - - - - - - - - - +assign iflush = ( (csr_write_enable_d == 1'b1) + && (csr_d == 5'h3) + && (stall_d == 1'b0) + && (kill_d == 1'b0) + && (valid_d == 1'b1)) - + + || + ( (jtag_csr_write_enable == 1'b1) + && (jtag_csr == 5'h3)) + + + ; + @@ -29883,7 +29994,7 @@ assign cfg2 = { -assign csr_d = read_idx_0_d[ (4 -1):0]; +assign csr_d = read_idx_0_d[ (5-1):0]; always @(*) @@ -29891,27 +30002,29 @@ begin case (csr_x) - 4 'h0, - 4 'h1, - 4 'h2: csr_read_data_x = interrupt_csr_read_data_x; + 5'h0, + 5'h1, + 5'h2: csr_read_data_x = interrupt_csr_read_data_x; - 4 'h6: csr_read_data_x = cfg; - 4 'h7: csr_read_data_x = {eba, 8'h00}; + 5'h6: csr_read_data_x = cfg; + 5'h7: csr_read_data_x = {eba, 8'h00}; - + 5'h9: csr_read_data_x = {deba, 8'h00}; + - - + 5'he: csr_read_data_x = jtx_csr_read_data; + 5'hf: csr_read_data_x = jrx_csr_read_data; + - 4 'ha: csr_read_data_x = cfg2; + 5'ha: csr_read_data_x = cfg2; default: csr_read_data_x = { 32{1'bx}}; endcase @@ -29925,36 +30038,40 @@ end always @(posedge clk_i ) begin if (rst_i == 1'b1) - eba <= eba_reset[ (32-2)+2-1:8]; + eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; else begin - if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0)) - eba <= operand_1_x[ (32-2)+2-1:8]; + if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0)) + eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - - + if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7)) + eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + end end - - - - - - - - - - - - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + else + begin + if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0)) + deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9)) + deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + end +end + @@ -29991,7 +30108,8 @@ end - + + @@ -30006,19 +30124,20 @@ end - - - - - - - +always @(*) +begin + if (icache_refill_request == 1'b1) + valid_a = 1'b0; + else if (icache_restart_request == 1'b1) + valid_a = 1'b1; + else + valid_a = !icache_refilling; +end - - - + + @@ -30030,7 +30149,6 @@ end - always @(posedge clk_i ) @@ -30047,11 +30165,11 @@ begin begin if ((kill_f == 1'b1) || (stall_a == 1'b0)) - - - valid_f <= 1'b1; + valid_f <= valid_a; + + else if (stall_f == 1'b0) valid_f <= 1'b0; @@ -30096,7 +30214,7 @@ begin operand_0_x <= { 32{1'b0}}; operand_1_x <= { 32{1'b0}}; store_operand_x <= { 32{1'b0}}; - branch_target_x <= { (32-2){1'b0}}; + branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; x_result_sel_csr_x <= 1'b0; @@ -30132,7 +30250,7 @@ begin m_bypass_enable_x <= 1'b0; write_enable_x <= 1'b0; write_idx_x <= { 5{1'b0}}; - csr_x <= { 4 {1'b0}}; + csr_x <= { 5{1'b0}}; load_x <= 1'b0; store_x <= 1'b0; size_x <= { 2{1'b0}}; @@ -30155,14 +30273,16 @@ begin branch_predict_taken_x <= 1'b0; condition_x <= 3'b000; - + break_x <= 1'b0; + scall_x <= 1'b0; eret_x <= 1'b0; - + bret_x <= 1'b0; + @@ -30171,7 +30291,7 @@ begin csr_write_enable_x <= 1'b0; operand_m <= { 32{1'b0}}; - branch_target_m <= { (32-2){1'b0}}; + branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; m_result_sel_compare_m <= 1'b0; @@ -30199,9 +30319,10 @@ begin - - + debug_exception_m <= 1'b0; + non_debug_exception_m <= 1'b0; + operand_w <= { 32{1'b0}}; w_result_sel_load_w <= 1'b0; @@ -30213,12 +30334,12 @@ begin write_idx_w <= { 5{1'b0}}; write_enable_w <= 1'b0; - - - - exception_w <= 1'b0; + debug_exception_w <= 1'b0; + non_debug_exception_w <= 1'b0; + + @@ -30238,7 +30359,7 @@ begin operand_0_x <= d_result_0; operand_1_x <= d_result_1; store_operand_x <= bypass_data_1; - branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d; + branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d; x_result_sel_csr_x <= x_result_sel_csr_d; @@ -30296,8 +30417,9 @@ begin condition_x <= condition_d; csr_write_enable_x <= csr_write_enable_d; - + break_x <= break_d; + scall_x <= scall_d; @@ -30306,8 +30428,9 @@ begin eret_x <= eret_d; - + bret_x <= bret_d; + write_enable_x <= write_enable_d; end @@ -30354,40 +30477,40 @@ begin + - - - - - - - - - if (exception_x == 1'b1) + if (non_debug_exception_x == 1'b1) write_idx_m <= 5'd30; + else if (debug_exception_x == 1'b1) + write_idx_m <= 5'd31; else write_idx_m <= write_idx_x; + + + + + condition_met_m <= condition_met_x; - - - - - - - - - - - branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x; + if (exception_x == 1'b1) + if ((dc_re == 1'b1) + || ((debug_exception_x == 1'b1) + && (non_debug_exception_x == 1'b0))) + branch_target_m <= {deba, eid_x, {3{1'b0}}}; + else + branch_target_m <= {eba, eid_x, {3{1'b0}}}; + else + branch_target_m <= branch_target_x; + + @@ -30406,9 +30529,10 @@ begin write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x; - - + debug_exception_m <= debug_exception_x; + non_debug_exception_m <= non_debug_exception_x; + end @@ -30454,12 +30578,12 @@ begin write_enable_w <= write_enable_m; - - - - exception_w <= exception_m; + debug_exception_w <= debug_exception_m; + non_debug_exception_w <= non_debug_exception_m; + + @@ -31004,7 +31128,7 @@ endmodule -module lm32_load_store_unit_medium ( +module lm32_load_store_unit_medium_debug ( clk_i, rst_i, @@ -32316,7 +32440,7 @@ endmodule -module lm32_decoder_medium ( +module lm32_decoder_medium_debug ( instruction, @@ -32395,14 +32519,16 @@ module lm32_decoder_medium ( bi_conditional, bi_unconditional, - + break_opcode, + scall, eret, - + bret, + @@ -32486,8 +32612,8 @@ output [ (5-1):0] write_idx; wire [ (5-1):0] write_idx; output [ (32-1):0] immediate; wire [ (32-1):0] immediate; -output [ ((32-2)+2-1):2] branch_offset; -wire [ ((32-2)+2-1):2] branch_offset; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset; output load; wire load; output store; @@ -32536,18 +32662,20 @@ wire bi_conditional; output bi_unconditional; wire bi_unconditional; - - +output break_opcode; +wire break_opcode; + output scall; wire scall; output eret; wire eret; - - +output bret; +wire bret; + @@ -32990,14 +33118,16 @@ assign branch = bra | call; assign branch_reg = op_call | op_b; assign condition = instruction[28:26]; - +assign break_opcode = op_raise & ~instruction[2]; + assign scall = op_raise & instruction[2]; assign eret = op_b & (instruction[25:21] == 5'd30); - +assign bret = op_b & (instruction[25:21] == 5'd31); + @@ -33023,8 +33153,8 @@ assign immediate = select_high_immediate == 1'b1 : extended_immediate; assign branch_offset = select_call_immediate == 1'b1 - ? (call_immediate[ (32-2)-1:0]) - : (branch_immediate[ (32-2)-1:0]); + ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]) + : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]); endmodule @@ -33386,426 +33516,499 @@ endmodule - - - - - - - - - - - - - - - - - - - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - + + + + - - - - - + - - - - - - - - - + + + + - - + - - + - - - - - - + - - + - - - - - - - - - - - - - +module lm32_icache_medium_debug ( - + clk_i, + rst_i, + stall_a, + stall_f, + address_a, + address_f, + read_enable_f, + refill_ready, + refill_data, + iflush, + + valid_d, + branch_predict_taken_d, + + stall_request, + restart_request, + refill_request, + refill_address, + refilling, + inst + ); - - - - - - - - - - - - - - - - +parameter associativity = 1; +parameter sets = 512; +parameter bytes_per_line = 16; +parameter base_address = 0; +parameter limit = 0; - - - - +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; +localparam addr_set_width = clogb2(sets)-1; +localparam addr_offset_lsb = 2; +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); +localparam addr_set_lsb = (addr_offset_msb+1); +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); +localparam addr_tag_lsb = (addr_set_msb+1); +localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1; +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); - +input clk_i; +input rst_i; - +input stall_a; +input stall_f; +input valid_d; +input branch_predict_taken_d; + +input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a; +input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f; +input read_enable_f; +input refill_ready; +input [ (32-1):0] refill_data; +input iflush; + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +output stall_request; +wire stall_request; +output restart_request; +reg restart_request; +output refill_request; +wire refill_request; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address; +output refilling; +reg refilling; +output [ (32-1):0] inst; +wire [ (32-1):0] inst; +wire enable; +wire [0:associativity-1] way_mem_we; +wire [ (32-1):0] way_data[0:associativity-1]; +wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1]; +wire [0:associativity-1] way_valid; +wire [0:associativity-1] way_match; +wire miss; - - - - +wire [ (addr_set_width-1):0] tmem_read_address; +wire [ (addr_set_width-1):0] tmem_write_address; +wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address; +wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address; +wire [ ((addr_tag_width+1)-1):0] tmem_write_data; +reg [ 3:0] state; +wire flushing; +wire check; +wire refill; +reg [associativity-1:0] refill_way_select; +reg [ addr_offset_msb:addr_offset_lsb] refill_offset; +wire last_refill; +reg [ (addr_set_width-1):0] flush_set; +genvar i; - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +function integer clogb2; +input [31:0] value; +begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; +end +endfunction +function integer clogb2_v1; +input [31:0] value; +reg [31:0] i; +reg [31:0] temp; +begin + temp = 0; + i = 0; + for (i = 0; temp < value; i = i + 1) + temp = 1< 4) +assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}; + else +assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb]; +endgenerate - - +assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb]; + + +assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb]; +assign tmem_write_address = flushing + ? flush_set + : refill_address[ addr_set_msb:addr_set_lsb]; + + +generate + if (bytes_per_line > 4) +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; + else +assign last_refill = 1'b1; +endgenerate + + +assign enable = (stall_a == 1'b0); + + +generate + if (associativity == 1) + begin : we_1 +assign way_mem_we[0] = (refill_ready == 1'b1); + end + else + begin : we_2 +assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1); +assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1); + end +endgenerate + + +assign tmem_write_data[ 0] = last_refill & !flushing; +assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb]; + + +assign flushing = |state[1:0]; +assign check = state[2]; +assign refill = state[3]; + +assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d); +assign stall_request = (check == 1'b0); +assign refill_request = (refill == 1'b1); + + + + + + +generate + if (associativity >= 2) + begin : way_select +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; + else + begin + if (miss == 1'b1) + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; + end +end + end +endgenerate + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + refilling <= 1'b0; + else + refilling <= refill; +end + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + state <= 4'b0001; + flush_set <= { addr_set_width{1'b1}}; + refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}}; + restart_request <= 1'b0; + end + else + begin + case (state) + + 4'b0001: + begin + if (flush_set == { addr_set_width{1'b0}}) + state <= 4'b0100; + flush_set <= flush_set - 1'b1; + end + - - - - + 4'b0010: + begin + if (flush_set == { addr_set_width{1'b0}}) + + - + + + state <= 4'b0100; + + flush_set <= flush_set - 1'b1; + end - - - + 4'b0100: + begin + if (stall_a == 1'b0) + restart_request <= 1'b0; + if (iflush == 1'b1) + begin + refill_address <= address_f; + state <= 4'b0010; + end + else if (miss == 1'b1) + begin + refill_address <= address_f; + state <= 4'b1000; + end + end + + 4'b1000: + begin + if (refill_ready == 1'b1) + begin + if (last_refill == 1'b1) + begin + restart_request <= 1'b1; + state <= 4'b0100; + end + end + end - - + endcase + end +end - +generate + if (bytes_per_line > 4) + begin - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + refill_offset <= {addr_offset_width{1'b0}}; + else + begin + case (state) + + + 4'b0100: + begin + if (iflush == 1'b1) + refill_offset <= {addr_offset_width{1'b0}}; + else if (miss == 1'b1) + refill_offset <= {addr_offset_width{1'b0}}; + end + + 4'b1000: + begin + if (refill_ready == 1'b1) + refill_offset <= refill_offset + 1'b1; + end + endcase + end +end + end +endgenerate + +endmodule + @@ -34989,135 +35192,160 @@ endmodule - - - - - - + + + + - - - - - - - - - - - - - - - - - - - + + + + + + + +module lm32_debug_medium_debug ( + clk_i, + rst_i, + pc_x, + load_x, + store_x, + load_store_address_x, + csr_write_enable_x, + csr_write_data, + csr_x, + + + jtag_csr_write_enable, + jtag_csr_write_data, + jtag_csr, - + + eret_q_x, + bret_q_x, + stall_x, + exception_x, + q_x, + + + - - - - + + + dc_ss, + + + dc_re, + bp_match, + wp_match + ); - - +parameter breakpoints = 0; +parameter watchpoints = 0; - - +input clk_i; +input rst_i; - - - - - - - +input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; +input load_x; +input store_x; +input [ (32-1):0] load_store_address_x; +input csr_write_enable_x; +input [ (32-1):0] csr_write_data; +input [ (5-1):0] csr_x; + + +input jtag_csr_write_enable; +input [ (32-1):0] jtag_csr_write_data; +input [ (5-1):0] jtag_csr; + + + +input eret_q_x; +input bret_q_x; +input stall_x; +input exception_x; +input q_x; + - - + - - - - - - - + +output dc_ss; +reg dc_ss; - - - - - - - - +output dc_re; +reg dc_re; +output bp_match; +wire bp_match; +output wp_match; +wire wp_match; - +genvar i; - - - +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1]; +reg bp_e[0:breakpoints-1]; +wire [0:breakpoints-1]bp_match_n; - - - +reg [ 1:0] wpc_c[0:watchpoints-1]; +reg [ (32-1):0] wp[0:watchpoints-1]; +wire [0:watchpoints-1]wp_match_n; + +wire debug_csr_write_enable; +wire [ (32-1):0] debug_csr_write_data; +wire [ (5-1):0] debug_csr; + + - - - + +reg [ 2:0] state; - + - @@ -35125,48 +35353,15 @@ endmodule - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -35175,132 +35370,223 @@ endmodule - - - - - - - - - - - - - - - - - - + +function integer clogb2; +input [31:0] value; +begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; +end +endfunction +function integer clogb2_v1; +input [31:0] value; +reg [31:0] i; +reg [31:0] temp; +begin + temp = 0; + i = 0; + for (i = 0; temp < value; i = i + 1) + temp = 1< 0) +assign bp_match = (|bp_match_n) || (state == 3'b011); + else +assign bp_match = state == 3'b011; + + - - - - - - - + + + +endgenerate - - + +generate + for (i = 0; i < watchpoints; i = i + 1) + begin : wp_comb +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); + end +endgenerate +generate + if (watchpoints > 0) +assign wp_match = |wp_match_n; + else +assign wp_match = 1'b0; +endgenerate - - - - - - - + + + +assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1); +assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data; +assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x; + + + + + + + + + + + + +generate + for (i = 0; i < breakpoints; i = i + 1) + begin : bp_seq +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}}; + bp_e[i] <= 1'b0; + end + else + begin + if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i)) + begin + bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]; + bp_e[i] <= debug_csr_write_data[0]; + end + end +end + end +endgenerate + + +generate + for (i = 0; i < watchpoints; i = i + 1) + begin : wp_seq +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + wp[i] <= { 32{1'bx}}; + wpc_c[i] <= 2'b00; + end + else + begin + if (debug_csr_write_enable == 1'b1) + begin + if (debug_csr == 5'h8) + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; + if (debug_csr == 5'h18 + i) + wp[i] <= debug_csr_write_data; + end + end +end + end +endgenerate + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + dc_re <= 1'b0; + else + begin + if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) + dc_re <= debug_csr_write_data[1]; + end +end + + + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + state <= 3'b000; + dc_ss <= 1'b0; + end + else + begin + if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) + begin + dc_ss <= debug_csr_write_data[0]; + if (debug_csr_write_data[0] == 1'b0) + state <= 3'b000; + else + state <= 3'b001; + end + case (state) + 3'b001: + begin - - - - - - - - - + if ( ( (eret_q_x == 1'b1) + || (bret_q_x == 1'b1) + ) + && (stall_x == 1'b0) + ) + state <= 3'b010; + end + 3'b010: + begin - - - - - + if ((q_x == 1'b1) && (stall_x == 1'b0)) + state <= 3'b011; + end + 3'b011: + begin - + - - - - - - - - + + if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0)) + begin + dc_ss <= 1'b0; + state <= 3'b100; + end + end + 3'b100: + begin - + - - - - - - + state <= 3'b000; + end + endcase + end +end + +endmodule + @@ -35673,7 +35959,7 @@ endmodule -module lm32_instruction_unit_medium ( +module lm32_instruction_unit_medium_debug ( clk_i, rst_i, @@ -35698,8 +35984,9 @@ module lm32_instruction_unit_medium ( branch_mispredict_taken_m, branch_target_m, - + iflush, + @@ -35723,11 +36010,12 @@ module lm32_instruction_unit_medium ( - - - - + jtag_read_enable, + jtag_write_enable, + jtag_write_data, + jtag_address, + @@ -35737,11 +36025,12 @@ module lm32_instruction_unit_medium ( pc_m, pc_w, - - - - + icache_stall_request, + icache_restart_request, + icache_refill_request, + icache_refilling, + @@ -35762,9 +36051,10 @@ module lm32_instruction_unit_medium ( - - + jtag_read_data, + jtag_access_complete, + @@ -35812,7 +36102,7 @@ input valid_d; input kill_f; input branch_predict_taken_d; -input [ ((32-2)+2-1):2] branch_predict_address_d; +input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d; @@ -35822,11 +36112,12 @@ input [ ((32-2)+2-1):2] branch_predict_address_d; input exception_m; input branch_taken_m; input branch_mispredict_taken_m; -input [ ((32-2)+2-1):2] branch_target_m; +input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m; - +input iflush; + @@ -35852,38 +36143,40 @@ input i_rty_i; - - - - +input jtag_read_enable; +input jtag_write_enable; +input [ 7:0] jtag_write_data; +input [ (32-1):0] jtag_address; + -output [ ((32-2)+2-1):2] pc_f; -reg [ ((32-2)+2-1):2] pc_f; -output [ ((32-2)+2-1):2] pc_d; -reg [ ((32-2)+2-1):2] pc_d; -output [ ((32-2)+2-1):2] pc_x; -reg [ ((32-2)+2-1):2] pc_x; -output [ ((32-2)+2-1):2] pc_m; -reg [ ((32-2)+2-1):2] pc_m; -output [ ((32-2)+2-1):2] pc_w; -reg [ ((32-2)+2-1):2] pc_w; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m; +output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w; - - - - - - - - +output icache_stall_request; +wire icache_stall_request; +output icache_restart_request; +wire icache_restart_request; +output icache_refill_request; +wire icache_refill_request; +output icache_refilling; +wire icache_refilling; + @@ -35896,11 +36189,11 @@ reg [ ((32-2)+2-1):2] pc_w; output [ (32-1):0] i_dat_o; - - -wire [ (32-1):0] i_dat_o; +reg [ (32-1):0] i_dat_o; + + output [ (32-1):0] i_adr_o; reg [ (32-1):0] i_adr_o; @@ -35908,21 +36201,21 @@ output i_cyc_o; reg i_cyc_o; output [ (4-1):0] i_sel_o; - - -wire [ (4-1):0] i_sel_o; +reg [ (4-1):0] i_sel_o; + + output i_stb_o; reg i_stb_o; output i_we_o; - - -wire i_we_o; +reg i_we_o; + + output [ (3-1):0] i_cti_o; reg [ (3-1):0] i_cti_o; @@ -35934,11 +36227,12 @@ wire [ (2-1):0] i_bte_o; - - - - +output [ 7:0] jtag_read_data; +reg [ 7:0] jtag_read_data; +output jtag_access_complete; +wire jtag_access_complete; + @@ -35959,31 +36253,30 @@ reg [ (32-1):0] instruction_d; -reg [ ((32-2)+2-1):2] pc_a; +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a; - - - - - - - - - - - - - +reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address; + -reg [ (32-1):0] wb_data_f; +wire icache_read_enable_f; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address; +reg icache_refill_ready; +reg [ (32-1):0] icache_refill_data; +wire [ (32-1):0] icache_data_f; +wire [ (3-1):0] first_cycle_type; +wire [ (3-1):0] next_cycle_type; +wire last_word; +wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address; - + + + @@ -36003,8 +36296,9 @@ reg [ (32-1):0] wb_data_f; - +reg jtag_access; + @@ -36121,35 +36415,36 @@ endfunction - - - - - - - - - - - - - - - - - - - - + +lm32_icache_medium_debug #( + .associativity (associativity), + .sets (sets), + .bytes_per_line (bytes_per_line), + .base_address (base_address), + .limit (limit) + ) icache ( - - - - - - + .clk_i (clk_i), + .rst_i (rst_i), + .stall_a (stall_a), + .stall_f (stall_f), + .branch_predict_taken_d (branch_predict_taken_d), + .valid_d (valid_d), + .address_a (pc_a), + .address_f (pc_f), + .read_enable_f (icache_read_enable_f), + .refill_ready (icache_refill_ready), + .refill_data (icache_refill_data), + .iflush (iflush), - + .stall_request (icache_stall_request), + .restart_request (icache_restart_request), + .refill_request (icache_refill_request), + .refill_address (icache_refill_address), + .refilling (icache_refilling), + .inst (icache_data_f) + ); + @@ -36158,16 +36453,19 @@ endfunction - - - + +assign icache_read_enable_f = (valid_f == 1'b1) + && (kill_f == 1'b0) + + - + - - + + ; + @@ -36195,10 +36493,11 @@ begin pc_a = branch_predict_address_d; else - - - + if (icache_restart_request == 1'b1) + pc_a = restart_address; + else + pc_a = pc_f + 1'b1; end @@ -36211,25 +36510,25 @@ end - - - + + +assign instruction_f = icache_data_f; + - + + + -assign instruction_f = wb_data_f; - - @@ -36237,11 +36536,11 @@ assign instruction_f = wb_data_f; - -assign i_dat_o = 32'd0; -assign i_we_o = 1'b0; -assign i_sel_o = 4'b1111; + + + + assign i_bte_o = 2'b00; @@ -36250,31 +36549,32 @@ assign i_bte_o = 2'b00; - - - - - - - - - - - - - - - - - - - - - - - - - +generate + case (bytes_per_line) + 4: + begin +assign first_cycle_type = 3'b111; +assign next_cycle_type = 3'b111; +assign last_word = 1'b1; +assign first_address = icache_refill_address; + end + 8: + begin +assign first_cycle_type = 3'b010; +assign next_cycle_type = 3'b111; +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; +assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; + end + 16: + begin +assign first_cycle_type = 3'b010; +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010; +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; +assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; + end + endcase +endgenerate + @@ -36286,11 +36586,11 @@ always @(posedge clk_i ) begin if (rst_i == 1'b1) begin - pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2]; - pc_d <= { (32-2){1'b0}}; - pc_x <= { (32-2){1'b0}}; - pc_m <= { (32-2){1'b0}}; - pc_w <= { (32-2){1'b0}}; + pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]; + pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; end else begin @@ -36308,13 +36608,14 @@ end - - - - - - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + else + begin + @@ -36326,14 +36627,18 @@ end - - - - - + + + if (icache_refill_request == 1'b1) + restart_address <= icache_refill_address; + + + end +end + @@ -36352,23 +36657,152 @@ end - + +assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1); +always @(*) +begin + case (jtag_address[1:0]) + 2'b00: jtag_read_data = i_dat_i[ 31:24]; + 2'b01: jtag_read_data = i_dat_i[ 23:16]; + 2'b10: jtag_read_data = i_dat_i[ 15:8]; + 2'b11: jtag_read_data = i_dat_i[ 7:0]; + endcase +end - - - - - - + + + + + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + i_cyc_o <= 1'b0; + i_stb_o <= 1'b0; + i_adr_o <= { 32{1'b0}}; + i_cti_o <= 3'b111; + i_lock_o <= 1'b0; + icache_refill_data <= { 32{1'b0}}; + icache_refill_ready <= 1'b0; + + + + + + + i_we_o <= 1'b0; + i_sel_o <= 4'b1111; + jtag_access <= 1'b0; + + + end + else + begin + icache_refill_ready <= 1'b0; + + if (i_cyc_o == 1'b1) + begin + + if ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) + begin + + + if (jtag_access == 1'b1) + begin + i_cyc_o <= 1'b0; + i_stb_o <= 1'b0; + i_we_o <= 1'b0; + jtag_access <= 1'b0; + end + else + + + begin + if (last_word == 1'b1) + begin + + i_cyc_o <= 1'b0; + i_stb_o <= 1'b0; + i_lock_o <= 1'b0; + end + + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; + i_cti_o <= next_cycle_type; + + icache_refill_ready <= 1'b1; + icache_refill_data <= i_dat_i; + end + end + + + + + + + + + end + else + begin + if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0)) + begin + + + + i_sel_o <= 4'b1111; + + i_adr_o <= {first_address, 2'b00}; + i_cyc_o <= 1'b1; + i_stb_o <= 1'b1; + i_cti_o <= first_cycle_type; + + + + end + else + begin + if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1)) + begin + case (jtag_address[1:0]) + 2'b00: i_sel_o <= 4'b1000; + 2'b01: i_sel_o <= 4'b0100; + 2'b10: i_sel_o <= 4'b0010; + 2'b11: i_sel_o <= 4'b0001; + endcase + i_adr_o <= jtag_address; + i_dat_o <= {4{jtag_write_data}}; + i_cyc_o <= 1'b1; + i_stb_o <= 1'b1; + i_we_o <= jtag_write_enable; + i_cti_o <= 3'b111; + jtag_access <= 1'b1; + end + end + + + + + + + + + + + + end + end +end + @@ -36379,50 +36813,23 @@ end - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - + + + @@ -36434,7 +36841,12 @@ end + + + + + @@ -36442,129 +36854,28 @@ end - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + - -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - i_cyc_o <= 1'b0; - i_stb_o <= 1'b0; - i_adr_o <= { 32{1'b0}}; - i_cti_o <= 3'b111; - i_lock_o <= 1'b0; - wb_data_f <= { 32{1'b0}}; - - - - - end - else - begin - - if (i_cyc_o == 1'b1) - begin - - if((i_ack_i == 1'b1) || (i_err_i == 1'b1)) - begin - - i_cyc_o <= 1'b0; - i_stb_o <= 1'b0; - - wb_data_f <= i_dat_i; - end - - - - - - - - - end - else - begin - - if ( (stall_a == 1'b0) - - - - - ) - begin - - - - - - i_adr_o <= {pc_a, 2'b00}; - i_cyc_o <= 1'b1; - i_stb_o <= 1'b1; - - - - - end - else - begin - if ( (stall_a == 1'b0) - - - - - ) - begin - - - - - end - end - end - end -end - @@ -36945,443 +37256,523 @@ endmodule - - - + - - - - - - - - + + - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +module lm32_jtag_medium_debug ( - - - - - - + clk_i, + rst_i, + jtag_clk, + jtag_update, + jtag_reg_q, + jtag_reg_addr_q, + + + csr, + csr_write_enable, + csr_write_data, + stall_x, - - - - + + + jtag_read_data, + jtag_access_complete, - - + + + exception_q_w, - + + + jtx_csr_read_data, + jrx_csr_read_data, - - + + + jtag_csr_write_enable, + jtag_csr_write_data, + jtag_csr, + jtag_read_enable, + jtag_write_enable, + jtag_write_data, + jtag_address, - - - - - - - + + + jtag_break, + jtag_reset, - - - - - + jtag_reg_d, + jtag_reg_addr_d + ); - - +input clk_i; +input rst_i; - - - - +input jtag_clk; +input jtag_update; +input [ 7:0] jtag_reg_q; +input [2:0] jtag_reg_addr_q; + + +input [ (5-1):0] csr; +input csr_write_enable; +input [ (32-1):0] csr_write_data; +input stall_x; - - - - + + +input [ 7:0] jtag_read_data; +input jtag_access_complete; - - + + +input exception_q_w; - - - - - - + +output [ (32-1):0] jtx_csr_read_data; +wire [ (32-1):0] jtx_csr_read_data; +output [ (32-1):0] jrx_csr_read_data; +wire [ (32-1):0] jrx_csr_read_data; - - - - - - - - - - - - - - + + +output jtag_csr_write_enable; +reg jtag_csr_write_enable; +output [ (32-1):0] jtag_csr_write_data; +wire [ (32-1):0] jtag_csr_write_data; +output [ (5-1):0] jtag_csr; +wire [ (5-1):0] jtag_csr; +output jtag_read_enable; +reg jtag_read_enable; +output jtag_write_enable; +reg jtag_write_enable; +output [ 7:0] jtag_write_data; +wire [ 7:0] jtag_write_data; +output [ (32-1):0] jtag_address; +wire [ (32-1):0] jtag_address; - - - - - - - + +output jtag_break; +reg jtag_break; +output jtag_reset; +reg jtag_reset; + + +output [ 7:0] jtag_reg_d; +reg [ 7:0] jtag_reg_d; +output [2:0] jtag_reg_addr_d; +wire [2:0] jtag_reg_addr_d; - - - - +reg rx_update; +reg rx_update_r; +reg rx_update_r_r; +reg rx_update_r_r_r; - +wire [ 7:0] rx_byte; +wire [2:0] rx_addr; + + +reg [ 7:0] uart_tx_byte; +reg uart_tx_valid; +reg [ 7:0] uart_rx_byte; +reg uart_rx_valid; + - - - - - +reg [ 3:0] command; + - +reg [ 7:0] jtag_byte_0; +reg [ 7:0] jtag_byte_1; +reg [ 7:0] jtag_byte_2; +reg [ 7:0] jtag_byte_3; +reg [ 7:0] jtag_byte_4; +reg processing; - - - - - - - +reg [ 3:0] state; + + +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; +assign jtag_csr = jtag_byte_4[ (5-1):0]; +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; +assign jtag_write_data = jtag_byte_4; - - - - - - - + + +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; + + + + +assign jtag_reg_addr_d[2] = processing; - - - - + + +assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00}; +assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte}; + - - +assign rx_byte = jtag_reg_q; +assign rx_addr = jtag_reg_addr_q; - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + rx_update <= 1'b0; + rx_update_r <= 1'b0; + rx_update_r_r <= 1'b0; + rx_update_r_r_r <= 1'b0; + end + else + begin + rx_update <= jtag_update; + rx_update_r <= rx_update; + rx_update_r_r <= rx_update_r; + rx_update_r_r_r <= rx_update_r_r; + end +end - - - - - - - - - - - - - - +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + state <= 4'h0; + command <= 4'b0000; + jtag_reg_d <= 8'h00; + + processing <= 1'b0; + jtag_csr_write_enable <= 1'b0; + jtag_read_enable <= 1'b0; + jtag_write_enable <= 1'b0; + - + - - - - - + jtag_break <= 1'b0; + jtag_reset <= 1'b0; - - - - + + + uart_tx_byte <= 8'h00; + uart_tx_valid <= 1'b0; + uart_rx_byte <= 8'h00; + uart_rx_valid <= 1'b0; - - - - - - - - - - - - - - - - - + end + else + begin + + + if ((csr_write_enable == 1'b1) && (stall_x == 1'b0)) + begin + case (csr) + 5'he: + begin - - - - - + uart_tx_byte <= csr_write_data[ 7:0]; + uart_tx_valid <= 1'b1; + end + 5'hf: + begin - - - - - + uart_rx_valid <= 1'b0; + end + endcase + end - - - - - - - - + + - - - - - + if (exception_q_w == 1'b1) + begin + jtag_break <= 1'b0; + jtag_reset <= 1'b0; + end - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + case (state) + 4'h0: + begin + + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + command <= rx_byte[7:4]; + case (rx_addr) + - + 3'b000: + begin + case (rx_byte[7:4]) + + + 4'b0001: + state <= 4'h1; + 4'b0011: + begin + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; + state <= 4'h6; + end + 4'b0010: + state <= 4'h1; + 4'b0100: + begin + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; + state <= 5; + end + 4'b0101: + state <= 4'h1; + - - + 4'b0110: + begin + + + uart_rx_valid <= 1'b0; + uart_tx_valid <= 1'b0; + - - - - - - - - - - - + jtag_break <= 1'b1; + end + 4'b0111: + begin + + + uart_rx_valid <= 1'b0; + uart_tx_valid <= 1'b0; + - - - - - + jtag_reset <= 1'b1; + end + endcase + end - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + 3'b001: + begin + uart_rx_byte <= rx_byte; + uart_rx_valid <= 1'b1; + end + 3'b010: + begin + jtag_reg_d <= uart_tx_byte; + uart_tx_valid <= 1'b0; + end + + default: + ; + endcase + end + end + 4'h1: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_0 <= rx_byte; + state <= 4'h2; + end + end + 4'h2: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_1 <= rx_byte; + state <= 4'h3; + end + end + 4'h3: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_2 <= rx_byte; + state <= 4'h4; + end + end + 4'h4: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_3 <= rx_byte; + if (command == 4'b0001) + state <= 4'h6; + else + state <= 4'h5; + end + end + 4'h5: + begin + if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) + begin + jtag_byte_4 <= rx_byte; + state <= 4'h6; + end + end + 4'h6: + begin + case (command) + 4'b0001, + 4'b0011: + begin + jtag_read_enable <= 1'b1; + processing <= 1'b1; + state <= 4'h7; + end + 4'b0010, + 4'b0100: + begin + jtag_write_enable <= 1'b1; + processing <= 1'b1; + state <= 4'h7; + end + 4'b0101: + begin + jtag_csr_write_enable <= 1'b1; + processing <= 1'b1; + state <= 4'h8; + end + endcase + end + 4'h7: + begin + if (jtag_access_complete == 1'b1) + begin + jtag_read_enable <= 1'b0; + jtag_reg_d <= jtag_read_data; + jtag_write_enable <= 1'b0; + processing <= 1'b0; + state <= 4'h0; + end + end + 4'h8: + begin + jtag_csr_write_enable <= 1'b0; + processing <= 1'b0; + state <= 4'h0; + end + + endcase + end +end + +endmodule + @@ -37736,7 +38127,7 @@ endmodule -module lm32_interrupt_medium ( +module lm32_interrupt_medium_debug ( clk_i, rst_i, @@ -37745,17 +38136,18 @@ module lm32_interrupt_medium ( stall_x, - - - - exception, + non_debug_exception, + debug_exception, + + eret_q_x, - + bret_q_x, + csr, csr_write_data, @@ -37784,20 +38176,21 @@ input [interrupts-1:0] interrupt; input stall_x; - - - -input exception; +input non_debug_exception; +input debug_exception; + + input eret_q_x; - +input bret_q_x; + -input [ (4 -1):0] csr; +input [ (5-1):0] csr; input [ (32-1):0] csr_write_data; input csr_write_enable; @@ -37824,8 +38217,9 @@ wire [interrupts-1:0] interrupt_n_exception; reg ie; reg eie; - +reg bie; + reg [interrupts-1:0] ip; reg [interrupts-1:0] im; @@ -37850,19 +38244,19 @@ generate always @(*) begin case (csr) - 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + 5'h0: csr_read_data = {{ 32-3{1'b0}}, - - - 1'b0, + bie, + + eie, ie }; - 4 'h2: csr_read_data = ip; - 4 'h1: csr_read_data = im; + 5'h2: csr_read_data = ip; + 5'h1: csr_read_data = im; default: csr_read_data = { 32{1'bx}}; endcase end @@ -37873,18 +38267,18 @@ end always @(*) begin case (csr) - 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + 5'h0: csr_read_data = {{ 32-3{1'b0}}, - - - 1'b0, + bie, + + eie, ie }; - 4 'h2: csr_read_data = ip; + 5'h2: csr_read_data = ip; default: csr_read_data = { 32{1'bx}}; endcase end @@ -37913,8 +38307,9 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; - + bie <= 1'b0; + im <= {interrupts{1'b0}}; ip <= {interrupts{1'b0}}; @@ -37926,13 +38321,21 @@ always @(posedge clk_i ) ip <= asserted; - - + + if (non_debug_exception == 1'b1) + begin - - - + eie <= ie; + ie <= 1'b0; + end + else if (debug_exception == 1'b1) + begin + bie <= ie; + ie <= 1'b0; + end + + @@ -37940,14 +38343,6 @@ always @(posedge clk_i ) - if (exception == 1'b1) - begin - - eie <= ie; - ie <= 1'b0; - end - - else if (stall_x == 1'b0) begin @@ -37965,26 +38360,28 @@ always @(posedge clk_i ) - - - + else if (bret_q_x == 1'b1) + + ie <= bie; + else if (csr_write_enable == 1'b1) begin - if (csr == 4 'h0) + if (csr == 5'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; - + bie <= csr_write_data[2]; + end - if (csr == 4 'h1) + if (csr == 5'h1) im <= csr_write_data[interrupts-1:0]; - if (csr == 4 'h2) + if (csr == 5'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -38001,8 +38398,9 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; - + bie <= 1'b0; + ip <= {interrupts{1'b0}}; eie_delay <= 0; @@ -38012,13 +38410,21 @@ always @(posedge clk_i ) ip <= asserted; - - + + if (non_debug_exception == 1'b1) + begin - - - + eie <= ie; + ie <= 1'b0; + end + else if (debug_exception == 1'b1) + begin + bie <= ie; + ie <= 1'b0; + end + + @@ -38026,14 +38432,6 @@ always @(posedge clk_i ) - if (exception == 1'b1) - begin - - eie <= ie; - ie <= 1'b0; - end - - else if (stall_x == 1'b0) begin @@ -38049,24 +38447,26 @@ always @(posedge clk_i ) end - - - + else if (bret_q_x == 1'b1) + + ie <= bie; + else if (csr_write_enable == 1'b1) begin - if (csr == 4 'h0) + if (csr == 5'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; - + bie <= csr_write_data[2]; + end - if (csr == 4 'h2) + if (csr == 5'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -38650,7 +39050,7 @@ endmodule -module lm32_top_medium_debug ( +module lm32_top_medium_icache_debug ( clk_i, rst_i, @@ -38712,6 +39112,7 @@ module lm32_top_medium_debug ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -38894,7 +39295,10 @@ endfunction -lm32_cpu_medium_debug cpu ( +lm32_cpu_medium_icache_debug + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), @@ -39374,7 +39778,7 @@ endmodule -module lm32_mc_arithmetic_medium_debug ( +module lm32_mc_arithmetic_medium_icache_debug ( clk_i, rst_i, @@ -40030,7 +40434,7 @@ endmodule -module lm32_cpu_medium_debug ( +module lm32_cpu_medium_icache_debug ( clk_i, @@ -40872,7 +41276,7 @@ endfunction -lm32_instruction_unit_medium_debug #( +lm32_instruction_unit_medium_icache_debug #( .eba_reset (eba_reset), .associativity (icache_associativity), .sets (icache_sets), @@ -40989,7 +41393,7 @@ lm32_instruction_unit_medium_debug #( ); -lm32_decoder_medium_debug decoder ( +lm32_decoder_medium_icache_debug decoder ( .instruction (instruction_d), @@ -41087,7 +41491,7 @@ lm32_decoder_medium_debug decoder ( ); -lm32_load_store_unit_medium_debug #( +lm32_load_store_unit_medium_icache_debug #( .associativity (dcache_associativity), .sets (dcache_sets), .bytes_per_line (dcache_bytes_per_line), @@ -41253,7 +41657,7 @@ lm32_multiplier multiplier ( -lm32_interrupt_medium_debug interrupt_unit ( +lm32_interrupt_medium_icache_debug interrupt_unit ( .clk_i (clk_i), .rst_i (rst_i), @@ -41289,7 +41693,7 @@ lm32_interrupt_medium_debug interrupt_unit ( -lm32_jtag_medium_debug jtag ( +lm32_jtag_medium_icache_debug jtag ( .clk_i (clk_i), .rst_i (rst_i), @@ -41353,7 +41757,7 @@ lm32_jtag_medium_debug jtag ( -lm32_debug_medium_debug #( +lm32_debug_medium_icache_debug #( .breakpoints (breakpoints), .watchpoints (watchpoints) ) hw_debug ( @@ -43513,7 +43917,7 @@ endmodule -module lm32_load_store_unit_medium_debug ( +module lm32_load_store_unit_medium_icache_debug ( clk_i, rst_i, @@ -44825,7 +45229,7 @@ endmodule -module lm32_decoder_medium_debug ( +module lm32_decoder_medium_icache_debug ( instruction, @@ -45944,7 +46348,7 @@ endmodule -module lm32_icache_medium_debug ( +module lm32_icache_medium_icache_debug ( clk_i, rst_i, @@ -47595,7 +47999,7 @@ endmodule -module lm32_debug_medium_debug ( +module lm32_debug_medium_icache_debug ( clk_i, rst_i, @@ -48344,7 +48748,7 @@ endmodule -module lm32_instruction_unit_medium_debug ( +module lm32_instruction_unit_medium_icache_debug ( clk_i, rst_i, @@ -48801,7 +49205,7 @@ endfunction -lm32_icache_medium_debug #( +lm32_icache_medium_icache_debug #( .associativity (associativity), .sets (sets), .bytes_per_line (bytes_per_line), @@ -49693,7 +50097,7 @@ endmodule -module lm32_jtag_medium_debug ( +module lm32_jtag_medium_icache_debug ( clk_i, rst_i, @@ -50512,7 +50916,7 @@ endmodule -module lm32_interrupt_medium_debug ( +module lm32_interrupt_medium_icache_debug ( clk_i, rst_i, @@ -51474,6 +51878,7 @@ module lm32_top_medium_icache ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -51655,7 +52060,10 @@ endfunction -lm32_cpu_medium_icache cpu ( +lm32_cpu_medium_icache + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), @@ -63400,14 +63808,6 @@ endmodule - - - - - - - - @@ -63433,16 +63833,13 @@ endmodule - - - - - + + + + - - - + @@ -63542,16 +63939,18 @@ endmodule + + - - - + + + @@ -63580,25 +63979,24 @@ endmodule - - - + + - - - + + + @@ -63699,47 +64097,27 @@ endmodule - - - - - - - - - - - - - - - - - + + - - + - + - - - - @@ -63748,8 +64126,6 @@ endmodule - - @@ -63757,19 +64133,28 @@ endmodule + + - + + - + + + + + + + + - @@ -63830,14 +64215,14 @@ endmodule + - - - + + @@ -63927,7 +64312,7 @@ endmodule -module lm32_top_medium_icache_debug ( +module lm32_top_medium ( clk_i, rst_i, @@ -63989,6 +64374,7 @@ module lm32_top_medium_icache_debug ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -64084,18 +64470,17 @@ wire [ (2-1):0] D_BTE_O; - -wire [ 7:0] jtag_reg_d; -wire [ 7:0] jtag_reg_q; -wire jtag_update; -wire [2:0] jtag_reg_addr_d; -wire [2:0] jtag_reg_addr_q; -wire jtck; -wire jrstn; + + + + + + + @@ -64171,7 +64556,10 @@ endfunction -lm32_cpu_medium_icache_debug cpu ( +lm32_cpu_medium + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), @@ -64192,13 +64580,12 @@ lm32_cpu_medium_icache_debug cpu ( - - .jtag_clk (jtck), - .jtag_update (jtag_update), - .jtag_reg_q (jtag_reg_q), - .jtag_reg_addr_q (jtag_reg_addr_q), - + + + + + @@ -64227,10 +64614,9 @@ lm32_cpu_medium_icache_debug cpu ( + + - .jtag_reg_d (jtag_reg_d), - .jtag_reg_addr_d (jtag_reg_addr_d), - @@ -64265,21 +64651,20 @@ lm32_cpu_medium_icache_debug cpu ( .D_BTE_O (D_BTE_O) ); - - + -jtag_cores jtag_cores ( + - .reg_d (jtag_reg_d), - .reg_addr_d (jtag_reg_addr_d), + + - .reg_update (jtag_update), - .reg_q (jtag_reg_q), - .reg_addr_q (jtag_reg_addr_q), - .jtck (jtck), - .jrstn (jrstn) - ); - + + + + + + + endmodule @@ -64651,7 +65036,7 @@ endmodule -module lm32_mc_arithmetic_medium_icache_debug ( +module lm32_mc_arithmetic_medium ( clk_i, rst_i, @@ -65307,7 +65692,7 @@ endmodule -module lm32_cpu_medium_icache_debug ( +module lm32_cpu_medium ( clk_i, @@ -65328,13 +65713,12 @@ module lm32_cpu_medium_icache_debug ( - - jtag_clk, - jtag_update, - jtag_reg_q, - jtag_reg_addr_q, - + + + + + @@ -65363,10 +65747,9 @@ module lm32_cpu_medium_icache_debug ( + + - jtag_reg_d, - jtag_reg_addr_d, - @@ -65407,25 +65790,24 @@ module lm32_cpu_medium_icache_debug ( parameter eba_reset = 32'h00000000; + -parameter deba_reset = 32'h10000000; - + + + + + -parameter icache_associativity = 1; -parameter icache_sets = 256; -parameter icache_bytes_per_line = 16; -parameter icache_base_address = 32'h0; -parameter icache_limit = 32'h7fffffff; - - - - - - +parameter icache_associativity = 1; +parameter icache_sets = 512; +parameter icache_bytes_per_line = 16; +parameter icache_base_address = 0; +parameter icache_limit = 0; + @@ -65445,11 +65827,11 @@ parameter dcache_limit = 0; + -parameter watchpoints = 32'h4; - - +parameter watchpoints = 0; + @@ -65491,12 +65873,11 @@ input [ (32-1):0] interrupt; + + + + -input jtag_clk; -input jtag_update; -input [ 7:0] jtag_reg_q; -input [2:0] jtag_reg_addr_q; - @@ -65536,12 +65917,11 @@ input D_RTY_I; + + + + -output [ 7:0] jtag_reg_d; -wire [ 7:0] jtag_reg_d; -output [2:0] jtag_reg_addr_d; -wire [2:0] jtag_reg_addr_d; - @@ -65605,9 +65985,8 @@ wire [ (2-1):0] D_BTE_O; + -reg valid_a; - reg valid_f; reg valid_d; @@ -65633,8 +66012,8 @@ reg [ 1:0] size_x; wire branch_d; wire branch_predict_d; wire branch_predict_taken_d; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d; +wire [ ((32-2)+2-1):2] branch_predict_address_d; +wire [ ((32-2)+2-1):2] branch_target_d; wire bi_unconditional; wire bi_conditional; reg branch_x; @@ -65646,9 +66025,9 @@ reg branch_predict_taken_m; wire branch_mispredict_taken_m; wire branch_flushX_m; wire branch_reg_d; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m; +wire [ ((32-2)+2-1):2] branch_offset_d; +reg [ ((32-2)+2-1):2] branch_target_x; +reg [ ((32-2)+2-1):2] branch_target_m; wire [ 0:0] d_result_sel_0_d; wire [ 1:0] d_result_sel_1_d; @@ -65723,15 +66102,14 @@ wire [ (5-1):0] write_idx_d; reg [ (5-1):0] write_idx_x; reg [ (5-1):0] write_idx_m; reg [ (5-1):0] write_idx_w; -wire [ (5-1):0] csr_d; -reg [ (5-1):0] csr_x; +wire [ (4 -1):0] csr_d; +reg [ (4 -1):0] csr_x; wire [ (3-1):0] condition_d; reg [ (3-1):0] condition_x; + + -wire break_d; -reg break_x; - wire scall_d; reg scall_x; @@ -65744,16 +66122,14 @@ wire eret_q_x; - -wire bret_d; -reg bret_x; -wire bret_q_x; - + + + + - wire csr_write_enable_d; reg csr_write_enable_x; @@ -65904,11 +66280,11 @@ wire [ (32-1):0] cfg2; reg [ (32-1):0] csr_read_data_x; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w; +wire [ ((32-2)+2-1):2] pc_f; +wire [ ((32-2)+2-1):2] pc_d; +wire [ ((32-2)+2-1):2] pc_x; +wire [ ((32-2)+2-1):2] pc_m; +wire [ ((32-2)+2-1):2] pc_w; @@ -65922,13 +66298,12 @@ wire [ (32-1):0] instruction_f; wire [ (32-1):0] instruction_d; + + + + + -wire iflush; -wire icache_stall_request; -wire icache_restart_request; -wire icache_refill_request; -wire icache_refilling; - @@ -65954,32 +66329,25 @@ wire stall_wb_load; - - - -wire [ (32-1):0] jtx_csr_read_data; -wire [ (32-1):0] jrx_csr_read_data; + + + + + + + - -wire jtag_csr_write_enable; -wire [ (32-1):0] jtag_csr_write_data; -wire [ (5-1):0] jtag_csr; -wire jtag_read_enable; -wire [ 7:0] jtag_read_data; -wire jtag_write_enable; -wire [ 7:0] jtag_write_data; -wire [ (32-1):0] jtag_address; -wire jtag_access_complete; - - -wire jtag_break; + + + + @@ -66009,11 +66377,10 @@ wire kill_x; wire kill_m; wire kill_w; -reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba; +reg [ (32-2)+2-1:8] eba; + -reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba; - reg [ (3-1):0] eid_x; @@ -66023,41 +66390,36 @@ reg [ (3-1):0] eid_x; - - - -wire dc_ss; + -wire dc_re; -wire bp_match; -wire wp_match; -wire exception_x; -reg exception_m; -wire debug_exception_x; -reg debug_exception_m; -reg debug_exception_w; -wire debug_exception_q_w; -wire non_debug_exception_x; -reg non_debug_exception_m; -reg non_debug_exception_w; -wire non_debug_exception_q_w; + + + + + + + + +wire exception_x; +reg exception_m; +reg exception_w; +wire exception_q_w; + - - -wire reset_exception; + + - @@ -66065,10 +66427,9 @@ wire interrupt_exception; + + -wire breakpoint_exception; -wire watchpoint_exception; - @@ -66149,7 +66510,7 @@ endfunction -lm32_instruction_unit_medium_icache_debug #( +lm32_instruction_unit_medium #( .eba_reset (eba_reset), .associativity (icache_associativity), .sets (icache_sets), @@ -66181,9 +66542,8 @@ lm32_instruction_unit_medium_icache_debug #( .branch_mispredict_taken_m (branch_mispredict_taken_m), .branch_target_m (branch_target_m), + - .iflush (iflush), - @@ -66207,12 +66567,11 @@ lm32_instruction_unit_medium_icache_debug #( + + + + - .jtag_read_enable (jtag_read_enable), - .jtag_write_enable (jtag_write_enable), - .jtag_write_data (jtag_write_data), - .jtag_address (jtag_address), - @@ -66222,12 +66581,11 @@ lm32_instruction_unit_medium_icache_debug #( .pc_m (pc_m), .pc_w (pc_w), + + + + - .icache_stall_request (icache_stall_request), - .icache_restart_request (icache_restart_request), - .icache_refill_request (icache_refill_request), - .icache_refilling (icache_refilling), - @@ -66248,10 +66606,9 @@ lm32_instruction_unit_medium_icache_debug #( + + - .jtag_read_data (jtag_read_data), - .jtag_access_complete (jtag_access_complete), - @@ -66266,7 +66623,7 @@ lm32_instruction_unit_medium_icache_debug #( ); -lm32_decoder_medium_icache_debug decoder ( +lm32_decoder_medium decoder ( .instruction (instruction_d), @@ -66345,16 +66702,14 @@ lm32_decoder_medium_icache_debug decoder ( .branch_reg (branch_reg_d), .condition (condition_d), + - .break_opcode (break_d), - .scall (scall_d), .eret (eret_d), + - .bret (bret_d), - @@ -66364,7 +66719,7 @@ lm32_decoder_medium_icache_debug decoder ( ); -lm32_load_store_unit_medium_icache_debug #( +lm32_load_store_unit_medium #( .associativity (dcache_associativity), .sets (dcache_sets), .bytes_per_line (dcache_bytes_per_line), @@ -66530,7 +66885,7 @@ lm32_multiplier multiplier ( -lm32_interrupt_medium_icache_debug interrupt_unit ( +lm32_interrupt_medium interrupt_unit ( .clk_i (clk_i), .rst_i (rst_i), @@ -66539,18 +66894,17 @@ lm32_interrupt_medium_icache_debug interrupt_unit ( .stall_x (stall_x), + + - .non_debug_exception (non_debug_exception_q_w), - .debug_exception (debug_exception_q_w), - - + .exception (exception_q_w), + .eret_q_x (eret_q_x), + - .bret_q_x (bret_q_x), - .csr (csr_x), .csr_write_data (operand_1_x), @@ -66565,116 +66919,95 @@ lm32_interrupt_medium_icache_debug interrupt_unit ( - -lm32_jtag_medium_icache_debug jtag ( + - .clk_i (clk_i), - .rst_i (rst_i), + + - .jtag_clk (jtag_clk), - .jtag_update (jtag_update), - .jtag_reg_q (jtag_reg_q), - .jtag_reg_addr_q (jtag_reg_addr_q), + + + + - - - .csr (csr_x), - .csr_write_data (operand_1_x), - .csr_write_enable (csr_write_enable_q_x), - .stall_x (stall_x), + + + + - - - .jtag_read_data (jtag_read_data), - .jtag_access_complete (jtag_access_complete), + + - - - .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), + - - - .jtx_csr_read_data (jtx_csr_read_data), - .jrx_csr_read_data (jrx_csr_read_data), + + - - - .jtag_csr_write_enable (jtag_csr_write_enable), - .jtag_csr_write_data (jtag_csr_write_data), - .jtag_csr (jtag_csr), - .jtag_read_enable (jtag_read_enable), - .jtag_write_enable (jtag_write_enable), - .jtag_write_data (jtag_write_data), - .jtag_address (jtag_address), + + + + + + + - - - .jtag_break (jtag_break), - .jtag_reset (reset_exception), + + - .jtag_reg_d (jtag_reg_d), - .jtag_reg_addr_d (jtag_reg_addr_d) - ); - - + + + - -lm32_debug_medium_icache_debug #( - .breakpoints (breakpoints), - .watchpoints (watchpoints) - ) hw_debug ( - - .clk_i (clk_i), - .rst_i (rst_i), - .pc_x (pc_x), - .load_x (load_x), - .store_x (store_x), - .load_store_address_x (adder_result_x), - .csr_write_enable_x (csr_write_enable_q_x), - .csr_write_data (operand_1_x), - .csr_x (csr_x), - .jtag_csr_write_enable (jtag_csr_write_enable), - .jtag_csr_write_data (jtag_csr_write_data), - .jtag_csr (jtag_csr), + + + + + + + + + + + + + + + + + - - - .eret_q_x (eret_q_x), - .bret_q_x (bret_q_x), - .stall_x (stall_x), - .exception_x (exception_x), - .q_x (q_x), - + + + + + + + + + + + + - - .dc_ss (dc_ss), - - - .dc_re (dc_re), - .bp_match (bp_match), - .wp_match (wp_match) - ); - @@ -67119,9 +67452,8 @@ assign kill_f = ( (valid_d == 1'b1) + - || (icache_refill_request == 1'b1) - @@ -67134,9 +67466,8 @@ assign kill_d = (branch_taken_m == 1'b1) + - || (icache_refill_request == 1'b1) - @@ -67165,25 +67496,21 @@ assign kill_w = 1'b0 - -assign breakpoint_exception = ( ( (break_x == 1'b1) - || (bp_match == 1'b1) - ) - && (valid_x == 1'b1) - ) - - - || (jtag_break == 1'b1) + + + + + + + + - ; - + -assign watchpoint_exception = wp_match == 1'b1; - @@ -67207,17 +67534,38 @@ assign system_call_exception = ( (scall_x == 1'b1) ); + + + -assign debug_exception_x = (breakpoint_exception == 1'b1) - || (watchpoint_exception == 1'b1) - ; + + + -assign non_debug_exception_x = (system_call_exception == 1'b1) - + + + - || (reset_exception == 1'b1) + + + + + + + + + + + + + + + + + +assign exception_x = (system_call_exception == 1'b1) @@ -67231,9 +67579,8 @@ assign non_debug_exception_x = (system_call_exception == 1'b1) || ( (interrupt_exception == 1'b1) + - && (dc_ss == 1'b0) - @@ -67244,54 +67591,27 @@ assign non_debug_exception_x = (system_call_exception == 1'b1) ; - -assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1); - - - - - - - - - - - - - - - - - - - - - always @(*) begin - - - - if (reset_exception == 1'b1) - eid_x = 3'h0; - else + + + - + + + + - if (breakpoint_exception == 1'b1) - eid_x = 3'd1; - else - @@ -67303,11 +67623,10 @@ begin + + + - if (watchpoint_exception == 1'b1) - eid_x = 3'd3; - else - @@ -67319,9 +67638,8 @@ begin if ( (interrupt_exception == 1'b1) + - && (dc_ss == 1'b0) - ) eid_x = 3'h6; @@ -67357,19 +67675,18 @@ assign stall_d = (stall_x == 1'b1) && (kill_d == 1'b0) ) + + + + + + + + + + + - || ( ( (break_d == 1'b1) - || (bret_d == 1'b1) - ) - && ( (load_q_x == 1'b1) - || (store_q_x == 1'b1) - || (load_q_m == 1'b1) - || (store_q_m == 1'b1) - || (D_CYC_O == 1'b1) - ) - && (kill_d == 1'b0) - ) - || ( (csr_write_enable_d == 1'b1) && (load_q_x == 1'b1) @@ -67431,14 +67748,16 @@ assign stall_m = (stall_wb_load == 1'b1) + + - || (icache_stall_request == 1'b1) - || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1))) - - - + + + || (I_CYC_O == 1'b1) + + @@ -67471,24 +67790,21 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0); assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1); assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1); + -assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1); - assign load_q_x = (load_x == 1'b1) && (q_x == 1'b1) + - && (bp_match == 1'b0) - ; assign store_q_x = (store_x == 1'b1) && (q_x == 1'b1) + - && (bp_match == 1'b0) - ; @@ -67499,13 +67815,13 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0); assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1); assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1); - -assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1)); -assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1)); - + +assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1)); + + assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0); assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1); @@ -67520,12 +67836,12 @@ assign cfg = { breakpoints[3:0], interrupts[5:0], - - 1'b1, - + 1'b0, + + @@ -67534,26 +67850,26 @@ assign cfg = { - - 1'b1, - - - - 1'b1, + 1'b0, - - + - 1'b1, + + 1'b0, + + + 1'b0, + + @@ -67625,22 +67941,19 @@ assign cfg2 = { + + + + + -assign iflush = ( (csr_write_enable_d == 1'b1) - && (csr_d == 5'h3) - && (stall_d == 1'b0) - && (kill_d == 1'b0) - && (valid_d == 1'b1)) - - - - || - ( (jtag_csr_write_enable == 1'b1) - && (jtag_csr == 5'h3)) + + + + + - ; - @@ -67656,7 +67969,7 @@ assign iflush = ( (csr_write_enable_d == 1'b1) -assign csr_d = read_idx_0_d[ (5-1):0]; +assign csr_d = read_idx_0_d[ (4 -1):0]; always @(*) @@ -67664,29 +67977,27 @@ begin case (csr_x) - 5'h0, - 5'h1, - 5'h2: csr_read_data_x = interrupt_csr_read_data_x; + 4 'h0, + 4 'h1, + 4 'h2: csr_read_data_x = interrupt_csr_read_data_x; - 5'h6: csr_read_data_x = cfg; - 5'h7: csr_read_data_x = {eba, 8'h00}; + 4 'h6: csr_read_data_x = cfg; + 4 'h7: csr_read_data_x = {eba, 8'h00}; + - 5'h9: csr_read_data_x = {deba, 8'h00}; - + + - 5'he: csr_read_data_x = jtx_csr_read_data; - 5'hf: csr_read_data_x = jrx_csr_read_data; - - 5'ha: csr_read_data_x = cfg2; + 4 'ha: csr_read_data_x = cfg2; default: csr_read_data_x = { 32{1'bx}}; endcase @@ -67700,40 +68011,36 @@ end always @(posedge clk_i ) begin if (rst_i == 1'b1) - eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + eba <= eba_reset[ (32-2)+2-1:8]; else begin - if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0)) - eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0)) + eba <= operand_1_x[ (32-2)+2-1:8]; + + - if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7)) - eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - end end + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - else - begin - if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0)) - deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; - - - if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9)) - deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8]; + + + + + + + + + + + - end -end - @@ -67768,11 +68075,10 @@ end - - + @@ -67786,20 +68092,19 @@ end - -always @(*) -begin - if (icache_refill_request == 1'b1) - valid_a = 1'b0; - else if (icache_restart_request == 1'b1) - valid_a = 1'b1; - else - valid_a = !icache_refilling; -end + + + + + + - + + + + @@ -67811,6 +68116,7 @@ end + always @(posedge clk_i ) @@ -67827,11 +68133,11 @@ begin begin if ((kill_f == 1'b1) || (stall_a == 1'b0)) + - valid_f <= valid_a; - - + valid_f <= 1'b1; + else if (stall_f == 1'b0) valid_f <= 1'b0; @@ -67876,7 +68182,7 @@ begin operand_0_x <= { 32{1'b0}}; operand_1_x <= { 32{1'b0}}; store_operand_x <= { 32{1'b0}}; - branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + branch_target_x <= { (32-2){1'b0}}; x_result_sel_csr_x <= 1'b0; @@ -67912,7 +68218,7 @@ begin m_bypass_enable_x <= 1'b0; write_enable_x <= 1'b0; write_idx_x <= { 5{1'b0}}; - csr_x <= { 5{1'b0}}; + csr_x <= { 4 {1'b0}}; load_x <= 1'b0; store_x <= 1'b0; size_x <= { 2{1'b0}}; @@ -67935,16 +68241,14 @@ begin branch_predict_taken_x <= 1'b0; condition_x <= 3'b000; + - break_x <= 1'b0; - scall_x <= 1'b0; eret_x <= 1'b0; + - bret_x <= 1'b0; - @@ -67953,7 +68257,7 @@ begin csr_write_enable_x <= 1'b0; operand_m <= { 32{1'b0}}; - branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + branch_target_m <= { (32-2){1'b0}}; m_result_sel_compare_m <= 1'b0; @@ -67981,10 +68285,9 @@ begin + + - debug_exception_m <= 1'b0; - non_debug_exception_m <= 1'b0; - operand_w <= { 32{1'b0}}; w_result_sel_load_w <= 1'b0; @@ -67996,13 +68299,13 @@ begin write_idx_w <= { 5{1'b0}}; write_enable_w <= 1'b0; - - debug_exception_w <= 1'b0; - non_debug_exception_w <= 1'b0; - + + exception_w <= 1'b0; + + @@ -68021,7 +68324,7 @@ begin operand_0_x <= d_result_0; operand_1_x <= d_result_1; store_operand_x <= bypass_data_1; - branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d; + branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d; x_result_sel_csr_x <= x_result_sel_csr_d; @@ -68079,9 +68382,8 @@ begin condition_x <= condition_d; csr_write_enable_x <= csr_write_enable_d; + - break_x <= break_d; - scall_x <= scall_d; @@ -68090,9 +68392,8 @@ begin eret_x <= eret_d; + - bret_x <= bret_d; - write_enable_x <= write_enable_d; end @@ -68139,40 +68440,40 @@ begin - - if (non_debug_exception_x == 1'b1) - write_idx_m <= 5'd30; - else if (debug_exception_x == 1'b1) - write_idx_m <= 5'd31; - else - write_idx_m <= write_idx_x; - - + + + + if (exception_x == 1'b1) + write_idx_m <= 5'd30; + else + write_idx_m <= write_idx_x; + + condition_met_m <= condition_met_x; + + + + + + + + + - if (exception_x == 1'b1) - if ((dc_re == 1'b1) - || ((debug_exception_x == 1'b1) - && (non_debug_exception_x == 1'b0))) - branch_target_m <= {deba, eid_x, {3{1'b0}}}; - else - branch_target_m <= {eba, eid_x, {3{1'b0}}}; - else - branch_target_m <= branch_target_x; - - + branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x; + @@ -68191,10 +68492,9 @@ begin write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x; + + - debug_exception_m <= debug_exception_x; - non_debug_exception_m <= non_debug_exception_x; - end @@ -68240,13 +68540,13 @@ begin write_enable_w <= write_enable_m; - - debug_exception_w <= debug_exception_m; - non_debug_exception_w <= non_debug_exception_m; - + + exception_w <= exception_m; + + @@ -68790,7 +69090,7 @@ endmodule -module lm32_load_store_unit_medium_icache_debug ( +module lm32_load_store_unit_medium ( clk_i, rst_i, @@ -70102,7 +70402,7 @@ endmodule -module lm32_decoder_medium_icache_debug ( +module lm32_decoder_medium ( instruction, @@ -70181,16 +70481,14 @@ module lm32_decoder_medium_icache_debug ( bi_conditional, bi_unconditional, + - break_opcode, - scall, eret, + - bret, - @@ -70274,8 +70572,8 @@ output [ (5-1):0] write_idx; wire [ (5-1):0] write_idx; output [ (32-1):0] immediate; wire [ (32-1):0] immediate; -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset; +output [ ((32-2)+2-1):2] branch_offset; +wire [ ((32-2)+2-1):2] branch_offset; output load; wire load; output store; @@ -70324,20 +70622,18 @@ wire bi_conditional; output bi_unconditional; wire bi_unconditional; - -output break_opcode; -wire break_opcode; + + output scall; wire scall; output eret; wire eret; - -output bret; -wire bret; + + @@ -70780,16 +71076,14 @@ assign branch = bra | call; assign branch_reg = op_call | op_b; assign condition = instruction[28:26]; + -assign break_opcode = op_raise & ~instruction[2]; - assign scall = op_raise & instruction[2]; assign eret = op_b & (instruction[25:21] == 5'd30); + -assign bret = op_b & (instruction[25:21] == 5'd31); - @@ -70815,8 +71109,8 @@ assign immediate = select_high_immediate == 1'b1 : extended_immediate; assign branch_offset = select_call_immediate == 1'b1 - ? (call_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]) - : (branch_immediate[ (clogb2(32'h7fffffff-32'h0)-2)-1:0]); + ? (call_immediate[ (32-2)-1:0]) + : (branch_immediate[ (32-2)-1:0]); endmodule @@ -71178,190 +71472,210 @@ endmodule + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + - + + + + + + + + + -module lm32_icache_medium_icache_debug ( + - clk_i, - rst_i, - stall_a, - stall_f, - address_a, - address_f, - read_enable_f, - refill_ready, - refill_data, - iflush, - + + + + + + + + + + + - - valid_d, - branch_predict_taken_d, - stall_request, - restart_request, - refill_request, - refill_address, - refilling, - inst - ); + + + + + + + + + -parameter associativity = 1; -parameter sets = 512; -parameter bytes_per_line = 16; -parameter base_address = 0; -parameter limit = 0; + + + + + -localparam addr_offset_width = clogb2(bytes_per_line)-1-2; -localparam addr_set_width = clogb2(sets)-1; -localparam addr_offset_lsb = 2; -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); -localparam addr_set_lsb = (addr_offset_msb+1); -localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); -localparam addr_tag_lsb = (addr_set_msb+1); -localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1; -localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); + + + + + + + + + -input clk_i; -input rst_i; + + -input stall_a; -input stall_f; + + -input valid_d; -input branch_predict_taken_d; + + -input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a; -input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f; -input read_enable_f; + + + -input refill_ready; -input [ (32-1):0] refill_data; + + -input iflush; - + + - -output stall_request; -wire stall_request; -output restart_request; -reg restart_request; -output refill_request; -wire refill_request; -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address; -output refilling; -reg refilling; -output [ (32-1):0] inst; -wire [ (32-1):0] inst; - - - - - -wire enable; -wire [0:associativity-1] way_mem_we; -wire [ (32-1):0] way_data[0:associativity-1]; -wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1]; -wire [0:associativity-1] way_valid; -wire [0:associativity-1] way_match; -wire miss; - -wire [ (addr_set_width-1):0] tmem_read_address; -wire [ (addr_set_width-1):0] tmem_write_address; -wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address; -wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address; -wire [ ((addr_tag_width+1)-1):0] tmem_write_data; - -reg [ 3:0] state; -wire flushing; -wire check; -wire refill; - -reg [associativity-1:0] refill_way_select; -reg [ addr_offset_msb:addr_offset_lsb] refill_offset; -wire last_refill; -reg [ (addr_set_width-1):0] flush_set; - -genvar i; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -71370,307 +71684,214 @@ genvar i; + + + + - -function integer clogb2; -input [31:0] value; -begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; -end -endfunction - -function integer clogb2_v1; -input [31:0] value; -reg [31:0] i; -reg [31:0] temp; -begin - temp = 0; - i = 0; - for (i = 0; temp < value; i = i + 1) - temp = 1< 4) -assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}; - else -assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb]; -endgenerate + + + -assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb]; - + + + + + + -assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb]; -assign tmem_write_address = flushing - ? flush_set - : refill_address[ addr_set_msb:addr_set_lsb]; + + -generate - if (bytes_per_line > 4) -assign last_refill = refill_offset == {addr_offset_width{1'b1}}; - else -assign last_refill = 1'b1; -endgenerate + + + -assign enable = (stall_a == 1'b0); + + + + -generate - if (associativity == 1) - begin : we_1 -assign way_mem_we[0] = (refill_ready == 1'b1); - end - else - begin : we_2 -assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1); -assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1); - end -endgenerate -assign tmem_write_data[ 0] = last_refill & !flushing; -assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb]; -assign flushing = |state[1:0]; -assign check = state[2]; -assign refill = state[3]; + + + -assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d); -assign stall_request = (check == 1'b0); -assign refill_request = (refill == 1'b1); - + + + + + + + + + -generate - if (associativity >= 2) - begin : way_select -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; - else - begin - if (miss == 1'b1) - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; - end -end - end -endgenerate + + + + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - refilling <= 1'b0; - else - refilling <= refill; -end + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - state <= 4'b0001; - flush_set <= { addr_set_width{1'b1}}; - refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}}; - restart_request <= 1'b0; - end - else - begin - case (state) + + + + + + + + + + - 4'b0001: - begin - if (flush_set == { addr_set_width{1'b0}}) - state <= 4'b0100; - flush_set <= flush_set - 1'b1; - end + + + + + + - 4'b0010: - begin - if (flush_set == { addr_set_width{1'b0}}) - + + + + - - state <= 4'b0100; + - flush_set <= flush_set - 1'b1; - end + - 4'b0100: - begin - if (stall_a == 1'b0) - restart_request <= 1'b0; - if (iflush == 1'b1) - begin - refill_address <= address_f; - state <= 4'b0010; - end - else if (miss == 1'b1) - begin - refill_address <= address_f; - state <= 4'b1000; - end - end + + + + + + + + + + + + + + + + - 4'b1000: - begin - if (refill_ready == 1'b1) - begin - if (last_refill == 1'b1) - begin - restart_request <= 1'b1; - state <= 4'b0100; - end - end - end + + + + + + + + + + + - endcase - end -end + + -generate - if (bytes_per_line > 4) - begin -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - refill_offset <= {addr_offset_width{1'b0}}; - else - begin - case (state) + + + + + + + + + + + - 4'b0100: - begin - if (iflush == 1'b1) - refill_offset <= {addr_offset_width{1'b0}}; - else if (miss == 1'b1) - refill_offset <= {addr_offset_width{1'b0}}; - end + + + + + + + - 4'b1000: - begin - if (refill_ready == 1'b1) - refill_offset <= refill_offset + 1'b1; - end + + + + + + + + + + - endcase - end -end - end -endgenerate -endmodule - + + @@ -72854,165 +73075,127 @@ endmodule + + + + + + - - - - - - - - - - - - -module lm32_debug_medium_icache_debug ( - clk_i, - rst_i, - pc_x, - load_x, - store_x, - load_store_address_x, - csr_write_enable_x, - csr_write_data, - csr_x, - - - jtag_csr_write_enable, - jtag_csr_write_data, - jtag_csr, + + + + + + + + + - - - - eret_q_x, - bret_q_x, - stall_x, - exception_x, - q_x, - - + + - - - - dc_ss, + + + + - - dc_re, - bp_match, - wp_match - ); + + + + + + + + -parameter breakpoints = 0; -parameter watchpoints = 0; + + -input clk_i; -input rst_i; -input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; -input load_x; -input store_x; -input [ (32-1):0] load_store_address_x; -input csr_write_enable_x; -input [ (32-1):0] csr_write_data; -input [ (5-1):0] csr_x; - -input jtag_csr_write_enable; -input [ (32-1):0] jtag_csr_write_data; -input [ (5-1):0] jtag_csr; - - + + -input eret_q_x; -input bret_q_x; -input stall_x; -input exception_x; -input q_x; - + + + + + + + + - + + - - - - - - - - -output dc_ss; -reg dc_ss; + + + + + - -output dc_re; -reg dc_re; -output bp_match; -wire bp_match; -output wp_match; -wire wp_match; - - - - - -genvar i; - + -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1]; -reg bp_e[0:breakpoints-1]; -wire [0:breakpoints-1]bp_match_n; - -reg [ 1:0] wpc_c[0:watchpoints-1]; -reg [ (32-1):0] wp[0:watchpoints-1]; -wire [0:watchpoints-1]wp_match_n; -wire debug_csr_write_enable; -wire [ (32-1):0] debug_csr_write_data; -wire [ (5-1):0] debug_csr; - -reg [ 2:0] state; + + + + + + + + - + + + + + + + + + + + + @@ -73020,6 +73203,7 @@ reg [ 2:0] state; + @@ -73027,35 +73211,48 @@ reg [ 2:0] state; + + + + + + + + + + + + + + + + + + + + + + + + + - -function integer clogb2; -input [31:0] value; -begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; -end -endfunction + + -function integer clogb2_v1; -input [31:0] value; -reg [31:0] i; -reg [31:0] temp; -begin - temp = 0; - i = 0; - for (i = 0; temp < value; i = i + 1) - temp = 1< 0) -assign bp_match = (|bp_match_n) || (state == 3'b011); - else -assign bp_match = state == 3'b011; - + + + + + + + + + + + - - + + -endgenerate - -generate - for (i = 0; i < watchpoints; i = i + 1) - begin : wp_comb -assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); - end -endgenerate -generate - if (watchpoints > 0) -assign wp_match = |wp_match_n; - else -assign wp_match = 1'b0; -endgenerate - - - -assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1); -assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data; -assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x; - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + -generate - for (i = 0; i < breakpoints; i = i + 1) - begin : bp_seq -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}}; - bp_e[i] <= 1'b0; - end - else - begin - if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i)) - begin - bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]; - bp_e[i] <= debug_csr_write_data[0]; - end - end -end - end -endgenerate - - -generate - for (i = 0; i < watchpoints; i = i + 1) - begin : wp_seq -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - wp[i] <= { 32{1'bx}}; - wpc_c[i] <= 2'b00; - end - else - begin - if (debug_csr_write_enable == 1'b1) - begin - if (debug_csr == 5'h8) - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; - if (debug_csr == 5'h18 + i) - wp[i] <= debug_csr_write_data; - end - end -end - end -endgenerate - - -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - dc_re <= 1'b0; - else - begin - if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) - dc_re <= debug_csr_write_data[1]; - end -end - - - + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - state <= 3'b000; - dc_ss <= 1'b0; - end - else - begin - if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8)) - begin - dc_ss <= debug_csr_write_data[0]; - if (debug_csr_write_data[0] == 1'b0) - state <= 3'b000; - else - state <= 3'b001; - end - case (state) - 3'b001: - begin + + + + + + + + + + + + + + + + + + - if ( ( (eret_q_x == 1'b1) - || (bret_q_x == 1'b1) - ) - && (stall_x == 1'b0) - ) - state <= 3'b010; - end - 3'b010: - begin + + + + + + + + + - if ((q_x == 1'b1) && (stall_x == 1'b0)) - state <= 3'b011; - end - 3'b011: - begin + + + + + - + - - if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0)) - begin - dc_ss <= 1'b0; - state <= 3'b100; - end - end - 3'b100: - begin + - + + + + + + + + + + + + + + - state <= 3'b000; - end - endcase - end -end - -endmodule - @@ -73621,7 +73759,7 @@ endmodule -module lm32_instruction_unit_medium_icache_debug ( +module lm32_instruction_unit_medium ( clk_i, rst_i, @@ -73646,9 +73784,8 @@ module lm32_instruction_unit_medium_icache_debug ( branch_mispredict_taken_m, branch_target_m, + - iflush, - @@ -73672,12 +73809,11 @@ module lm32_instruction_unit_medium_icache_debug ( + + + + - jtag_read_enable, - jtag_write_enable, - jtag_write_data, - jtag_address, - @@ -73687,12 +73823,11 @@ module lm32_instruction_unit_medium_icache_debug ( pc_m, pc_w, + + + + - icache_stall_request, - icache_restart_request, - icache_refill_request, - icache_refilling, - @@ -73713,10 +73848,9 @@ module lm32_instruction_unit_medium_icache_debug ( + + - jtag_read_data, - jtag_access_complete, - @@ -73764,7 +73898,7 @@ input valid_d; input kill_f; input branch_predict_taken_d; -input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d; +input [ ((32-2)+2-1):2] branch_predict_address_d; @@ -73774,12 +73908,11 @@ input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d; input exception_m; input branch_taken_m; input branch_mispredict_taken_m; -input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m; +input [ ((32-2)+2-1):2] branch_target_m; + -input iflush; - @@ -73805,40 +73938,38 @@ input i_rty_i; + + + + -input jtag_read_enable; -input jtag_write_enable; -input [ 7:0] jtag_write_data; -input [ (32-1):0] jtag_address; - -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f; -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d; -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x; -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m; -output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w; +output [ ((32-2)+2-1):2] pc_f; +reg [ ((32-2)+2-1):2] pc_f; +output [ ((32-2)+2-1):2] pc_d; +reg [ ((32-2)+2-1):2] pc_d; +output [ ((32-2)+2-1):2] pc_x; +reg [ ((32-2)+2-1):2] pc_x; +output [ ((32-2)+2-1):2] pc_m; +reg [ ((32-2)+2-1):2] pc_m; +output [ ((32-2)+2-1):2] pc_w; +reg [ ((32-2)+2-1):2] pc_w; + + + + + + + + -output icache_stall_request; -wire icache_stall_request; -output icache_restart_request; -wire icache_restart_request; -output icache_refill_request; -wire icache_refill_request; -output icache_refilling; -wire icache_refilling; - @@ -73851,11 +73982,11 @@ wire icache_refilling; output [ (32-1):0] i_dat_o; + -reg [ (32-1):0] i_dat_o; - - +wire [ (32-1):0] i_dat_o; + output [ (32-1):0] i_adr_o; reg [ (32-1):0] i_adr_o; @@ -73863,21 +73994,21 @@ output i_cyc_o; reg i_cyc_o; output [ (4-1):0] i_sel_o; + -reg [ (4-1):0] i_sel_o; - - +wire [ (4-1):0] i_sel_o; + output i_stb_o; reg i_stb_o; output i_we_o; + -reg i_we_o; - - +wire i_we_o; + output [ (3-1):0] i_cti_o; reg [ (3-1):0] i_cti_o; @@ -73889,12 +74020,11 @@ wire [ (2-1):0] i_bte_o; + + + + -output [ 7:0] jtag_read_data; -reg [ 7:0] jtag_read_data; -output jtag_access_complete; -wire jtag_access_complete; - @@ -73915,30 +74045,31 @@ reg [ (32-1):0] instruction_d; -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a; +reg [ ((32-2)+2-1):2] pc_a; + -reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address; - + + + + + + + + + -wire icache_read_enable_f; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address; -reg icache_refill_ready; -reg [ (32-1):0] icache_refill_data; -wire [ (32-1):0] icache_data_f; -wire [ (3-1):0] first_cycle_type; -wire [ (3-1):0] next_cycle_type; -wire last_word; -wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address; - - - + + +reg [ (32-1):0] wb_data_f; + + @@ -73958,9 +74089,8 @@ wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address; + -reg jtag_access; - @@ -74077,57 +74207,53 @@ endfunction - -lm32_icache_medium_icache_debug #( - .associativity (associativity), - .sets (sets), - .bytes_per_line (bytes_per_line), - .base_address (base_address), - .limit (limit) - ) icache ( + + + + + + + - .clk_i (clk_i), - .rst_i (rst_i), - .stall_a (stall_a), - .stall_f (stall_f), - .branch_predict_taken_d (branch_predict_taken_d), - .valid_d (valid_d), - .address_a (pc_a), - .address_f (pc_f), - .read_enable_f (icache_read_enable_f), - .refill_ready (icache_refill_ready), - .refill_data (icache_refill_data), - .iflush (iflush), + + + + + + + + + + + + + + + + + + + - .stall_request (icache_stall_request), - .restart_request (icache_restart_request), - .refill_request (icache_refill_request), - .refill_address (icache_refill_address), - .refilling (icache_refilling), - .inst (icache_data_f) - ); - - - -assign icache_read_enable_f = (valid_f == 1'b1) - && (kill_f == 1'b0) - + + + + - + - - ; - + + @@ -74155,11 +74281,10 @@ begin pc_a = branch_predict_address_d; else + + + - if (icache_restart_request == 1'b1) - pc_a = restart_address; - else - pc_a = pc_f + 1'b1; end @@ -74172,25 +74297,25 @@ end - - + + -assign instruction_f = icache_data_f; - - - + + - +assign instruction_f = wb_data_f; + + @@ -74198,11 +74323,11 @@ assign instruction_f = icache_data_f; - - - - +assign i_dat_o = 32'd0; +assign i_we_o = 1'b0; +assign i_sel_o = 4'b1111; + assign i_bte_o = 2'b00; @@ -74211,32 +74336,31 @@ assign i_bte_o = 2'b00; -generate - case (bytes_per_line) - 4: - begin -assign first_cycle_type = 3'b111; -assign next_cycle_type = 3'b111; -assign last_word = 1'b1; -assign first_address = icache_refill_address; - end - 8: - begin -assign first_cycle_type = 3'b010; -assign next_cycle_type = 3'b111; -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; -assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; - end - 16: - begin -assign first_cycle_type = 3'b010; -assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010; -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; -assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; - end - endcase -endgenerate - + + + + + + + + + + + + + + + + + + + + + + + + + @@ -74248,11 +74372,11 @@ always @(posedge clk_i ) begin if (rst_i == 1'b1) begin - pc_f <= eba_reset_minus_4[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]; - pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; - pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; - pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; - pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; + pc_f <= eba_reset_minus_4[ ((32-2)+2-1):2]; + pc_d <= { (32-2){1'b0}}; + pc_x <= { (32-2){1'b0}}; + pc_m <= { (32-2){1'b0}}; + pc_w <= { (32-2){1'b0}}; end else begin @@ -74270,14 +74394,13 @@ end + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}}; - else - begin - + + + + + @@ -74289,18 +74412,14 @@ begin + + + - - - if (icache_refill_request == 1'b1) - restart_address <= icache_refill_address; - - + + - end -end - @@ -74319,152 +74438,23 @@ end - -assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1); -always @(*) -begin - case (jtag_address[1:0]) - 2'b00: jtag_read_data = i_dat_i[ 31:24]; - 2'b01: jtag_read_data = i_dat_i[ 23:16]; - 2'b10: jtag_read_data = i_dat_i[ 15:8]; - 2'b11: jtag_read_data = i_dat_i[ 7:0]; - endcase -end - - - - - - - - -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - i_cyc_o <= 1'b0; - i_stb_o <= 1'b0; - i_adr_o <= { 32{1'b0}}; - i_cti_o <= 3'b111; - i_lock_o <= 1'b0; - icache_refill_data <= { 32{1'b0}}; - icache_refill_ready <= 1'b0; - - - - - - - i_we_o <= 1'b0; - i_sel_o <= 4'b1111; - jtag_access <= 1'b0; - - - end - else - begin - icache_refill_ready <= 1'b0; - - if (i_cyc_o == 1'b1) - begin - - if ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) - begin - - - if (jtag_access == 1'b1) - begin - i_cyc_o <= 1'b0; - i_stb_o <= 1'b0; - i_we_o <= 1'b0; - jtag_access <= 1'b0; - end - else + - begin - if (last_word == 1'b1) - begin - - i_cyc_o <= 1'b0; - i_stb_o <= 1'b0; - i_lock_o <= 1'b0; - end - - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; - i_cti_o <= next_cycle_type; - - icache_refill_ready <= 1'b1; - icache_refill_data <= i_dat_i; - end - end - - - - - - - - - end - else - begin - if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0)) - begin - - - i_sel_o <= 4'b1111; - + + + + + - i_adr_o <= {first_address, 2'b00}; - i_cyc_o <= 1'b1; - i_stb_o <= 1'b1; - i_cti_o <= first_cycle_type; - - - - end - - else - begin - if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1)) - begin - case (jtag_address[1:0]) - 2'b00: i_sel_o <= 4'b1000; - 2'b01: i_sel_o <= 4'b0100; - 2'b10: i_sel_o <= 4'b0010; - 2'b11: i_sel_o <= 4'b0001; - endcase - i_adr_o <= jtag_address; - i_dat_o <= {4{jtag_write_data}}; - i_cyc_o <= 1'b1; - i_stb_o <= 1'b1; - i_we_o <= jtag_write_enable; - i_cti_o <= 3'b111; - jtag_access <= 1'b1; - end - end - - - - - - - - - - - end - end -end - + @@ -74475,23 +74465,50 @@ end - + + + + + + + + - + + + - - + + + + + + + + + + + + + + + + + + + + + - @@ -74503,12 +74520,7 @@ end - - - - - @@ -74516,28 +74528,129 @@ end + + - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + +always @(posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + i_cyc_o <= 1'b0; + i_stb_o <= 1'b0; + i_adr_o <= { 32{1'b0}}; + i_cti_o <= 3'b111; + i_lock_o <= 1'b0; + wb_data_f <= { 32{1'b0}}; + + + + + end + else + begin + + if (i_cyc_o == 1'b1) + begin + + if((i_ack_i == 1'b1) || (i_err_i == 1'b1)) + begin + + i_cyc_o <= 1'b0; + i_stb_o <= 1'b0; + + wb_data_f <= i_dat_i; + end + + + + + + + + + end + else + begin + + if ( (stall_a == 1'b0) + + + + + ) + begin + + + + + + i_adr_o <= {pc_a, 2'b00}; + i_cyc_o <= 1'b1; + i_stb_o <= 1'b1; + + + + + end + else + begin + if ( (stall_a == 1'b0) + + + + + ) + begin + + + + + end + end + end + end +end + @@ -74918,523 +75031,443 @@ endmodule + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + - - + + + + + + + + + + - - - - - - - - - - -module lm32_jtag_medium_icache_debug ( - clk_i, - rst_i, - jtag_clk, - jtag_update, - jtag_reg_q, - jtag_reg_addr_q, - - - csr, - csr_write_enable, - csr_write_data, - stall_x, + + + + + + + + + + - - - jtag_read_data, - jtag_access_complete, + + - - - exception_q_w, - - - jtx_csr_read_data, - jrx_csr_read_data, + + + - - - jtag_csr_write_enable, - jtag_csr_write_data, - jtag_csr, - jtag_read_enable, - jtag_write_enable, - jtag_write_data, - jtag_address, + + + + + + + - - - jtag_break, - jtag_reset, + + - jtag_reg_d, - jtag_reg_addr_d - ); - + + + -input clk_i; -input rst_i; -input jtag_clk; -input jtag_update; -input [ 7:0] jtag_reg_q; -input [2:0] jtag_reg_addr_q; + + - + + + + -input [ (5-1):0] csr; -input csr_write_enable; -input [ (32-1):0] csr_write_data; -input stall_x; + + + + - - -input [ 7:0] jtag_read_data; -input jtag_access_complete; + + - - -input exception_q_w; + - - -output [ (32-1):0] jtx_csr_read_data; -wire [ (32-1):0] jtx_csr_read_data; -output [ (32-1):0] jrx_csr_read_data; -wire [ (32-1):0] jrx_csr_read_data; + + + + - - -output jtag_csr_write_enable; -reg jtag_csr_write_enable; -output [ (32-1):0] jtag_csr_write_data; -wire [ (32-1):0] jtag_csr_write_data; -output [ (5-1):0] jtag_csr; -wire [ (5-1):0] jtag_csr; -output jtag_read_enable; -reg jtag_read_enable; -output jtag_write_enable; -reg jtag_write_enable; -output [ 7:0] jtag_write_data; -wire [ 7:0] jtag_write_data; -output [ (32-1):0] jtag_address; -wire [ (32-1):0] jtag_address; + + + + + + + + + + + + + + - - -output jtag_break; -reg jtag_break; -output jtag_reset; -reg jtag_reset; + + + + -output [ 7:0] jtag_reg_d; -reg [ 7:0] jtag_reg_d; -output [2:0] jtag_reg_addr_d; -wire [2:0] jtag_reg_addr_d; + + + + -reg rx_update; -reg rx_update_r; -reg rx_update_r_r; -reg rx_update_r_r_r; - + + + + -wire [ 7:0] rx_byte; -wire [2:0] rx_addr; + - -reg [ 7:0] uart_tx_byte; -reg uart_tx_valid; -reg [ 7:0] uart_rx_byte; -reg uart_rx_valid; - + + + + + -reg [ 3:0] command; - -reg [ 7:0] jtag_byte_0; -reg [ 7:0] jtag_byte_1; -reg [ 7:0] jtag_byte_2; -reg [ 7:0] jtag_byte_3; -reg [ 7:0] jtag_byte_4; -reg processing; + + + + + + + -reg [ 3:0] state; - + - -assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; -assign jtag_csr = jtag_byte_4[ (5-1):0]; -assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; -assign jtag_write_data = jtag_byte_4; + + + + - - -assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; - - - + + - + -assign jtag_reg_addr_d[2] = processing; + - - -assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00}; -assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte}; - + + + -assign rx_byte = jtag_reg_q; -assign rx_addr = jtag_reg_addr_q; - + + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - rx_update <= 1'b0; - rx_update_r <= 1'b0; - rx_update_r_r <= 1'b0; - rx_update_r_r_r <= 1'b0; - end - else - begin - rx_update <= jtag_update; - rx_update_r <= rx_update; - rx_update_r_r <= rx_update_r; - rx_update_r_r_r <= rx_update_r_r; - end -end + -always @(posedge clk_i ) -begin - if (rst_i == 1'b1) - begin - state <= 4'h0; - command <= 4'b0000; - jtag_reg_d <= 8'h00; - + + + + + + + + + + + + + + - processing <= 1'b0; - jtag_csr_write_enable <= 1'b0; - jtag_read_enable <= 1'b0; - jtag_write_enable <= 1'b0; - - - jtag_break <= 1'b0; - jtag_reset <= 1'b0; - + - - - uart_tx_byte <= 8'h00; - uart_tx_valid <= 1'b0; - uart_rx_byte <= 8'h00; - uart_rx_valid <= 1'b0; + + + + + + + + + - end - else - begin - - - if ((csr_write_enable == 1'b1) && (stall_x == 1'b0)) - begin - case (csr) - 5'he: - begin - - uart_tx_byte <= csr_write_data[ 7:0]; - uart_tx_valid <= 1'b1; - end - 5'hf: - begin - - uart_rx_valid <= 1'b0; - end - endcase - end + + - + + + + + + + + + + - if (exception_q_w == 1'b1) - begin - jtag_break <= 1'b0; - jtag_reset <= 1'b0; - end + + + + + + + + + + + + + + + + + + + + + - case (state) - 4'h0: - begin + + + - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - command <= rx_byte[7:4]; - case (rx_addr) - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - 3'b000: - begin - case (rx_byte[7:4]) - + + + + + + + - 4'b0001: - state <= 4'h1; - 4'b0011: - begin - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; - state <= 4'h6; - end - 4'b0010: - state <= 4'h1; - 4'b0100: - begin - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; - state <= 5; - end - 4'b0101: - state <= 4'h1; - + - 4'b0110: - begin - - - uart_rx_valid <= 1'b0; - uart_tx_valid <= 1'b0; - + + - jtag_break <= 1'b1; - end - 4'b0111: - begin - - - uart_rx_valid <= 1'b0; - uart_tx_valid <= 1'b0; - + + + + + + + + + + + - jtag_reset <= 1'b1; - end - endcase - end + + + + + - - + + - 3'b001: - begin - uart_rx_byte <= rx_byte; - uart_rx_valid <= 1'b1; - end - 3'b010: - begin - jtag_reg_d <= uart_tx_byte; - uart_tx_valid <= 1'b0; - end - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - default: - ; - endcase - end - end - 4'h1: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_0 <= rx_byte; - state <= 4'h2; - end - end - 4'h2: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_1 <= rx_byte; - state <= 4'h3; - end - end - 4'h3: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_2 <= rx_byte; - state <= 4'h4; - end - end - 4'h4: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_3 <= rx_byte; - if (command == 4'b0001) - state <= 4'h6; - else - state <= 4'h5; - end - end - 4'h5: - begin - if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1) - begin - jtag_byte_4 <= rx_byte; - state <= 4'h6; - end - end - 4'h6: - begin - case (command) - 4'b0001, - 4'b0011: - begin - jtag_read_enable <= 1'b1; - processing <= 1'b1; - state <= 4'h7; - end - 4'b0010, - 4'b0100: - begin - jtag_write_enable <= 1'b1; - processing <= 1'b1; - state <= 4'h7; - end - 4'b0101: - begin - jtag_csr_write_enable <= 1'b1; - processing <= 1'b1; - state <= 4'h8; - end - endcase - end - 4'h7: - begin - if (jtag_access_complete == 1'b1) - begin - jtag_read_enable <= 1'b0; - jtag_reg_d <= jtag_read_data; - jtag_write_enable <= 1'b0; - processing <= 1'b0; - state <= 4'h0; - end - end - 4'h8: - begin - jtag_csr_write_enable <= 1'b0; - processing <= 1'b0; - state <= 4'h0; - end - - endcase - end -end - -endmodule - @@ -75789,7 +75822,7 @@ endmodule -module lm32_interrupt_medium_icache_debug ( +module lm32_interrupt_medium ( clk_i, rst_i, @@ -75798,18 +75831,17 @@ module lm32_interrupt_medium_icache_debug ( stall_x, - - non_debug_exception, - debug_exception, - + + exception, + + eret_q_x, + - bret_q_x, - csr, csr_write_data, @@ -75838,21 +75870,20 @@ input [interrupts-1:0] interrupt; input stall_x; + + -input non_debug_exception; -input debug_exception; - - +input exception; + input eret_q_x; + -input bret_q_x; - -input [ (5-1):0] csr; +input [ (4 -1):0] csr; input [ (32-1):0] csr_write_data; input csr_write_enable; @@ -75879,9 +75910,8 @@ wire [interrupts-1:0] interrupt_n_exception; reg ie; reg eie; + -reg bie; - reg [interrupts-1:0] ip; reg [interrupts-1:0] im; @@ -75906,19 +75936,19 @@ generate always @(*) begin case (csr) - 5'h0: csr_read_data = {{ 32-3{1'b0}}, + 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + - bie, - - + 1'b0, + eie, ie }; - 5'h2: csr_read_data = ip; - 5'h1: csr_read_data = im; + 4 'h2: csr_read_data = ip; + 4 'h1: csr_read_data = im; default: csr_read_data = { 32{1'bx}}; endcase end @@ -75929,18 +75959,18 @@ end always @(*) begin case (csr) - 5'h0: csr_read_data = {{ 32-3{1'b0}}, + 4 'h0: csr_read_data = {{ 32-3{1'b0}}, + - bie, - - + 1'b0, + eie, ie }; - 5'h2: csr_read_data = ip; + 4 'h2: csr_read_data = ip; default: csr_read_data = { 32{1'bx}}; endcase end @@ -75969,9 +75999,8 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; + - bie <= 1'b0; - im <= {interrupts{1'b0}}; ip <= {interrupts{1'b0}}; @@ -75983,21 +76012,13 @@ always @(posedge clk_i ) ip <= asserted; - - if (non_debug_exception == 1'b1) - begin + + - eie <= ie; - ie <= 1'b0; - end - else if (debug_exception == 1'b1) - begin + + + - bie <= ie; - ie <= 1'b0; - end - - @@ -76005,6 +76026,14 @@ always @(posedge clk_i ) + if (exception == 1'b1) + begin + + eie <= ie; + ie <= 1'b0; + end + + else if (stall_x == 1'b0) begin @@ -76022,28 +76051,26 @@ always @(posedge clk_i ) - - else if (bret_q_x == 1'b1) - ie <= bie; - + + + else if (csr_write_enable == 1'b1) begin - if (csr == 5'h0) + if (csr == 4 'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; + - bie <= csr_write_data[2]; - end - if (csr == 5'h1) + if (csr == 4 'h1) im <= csr_write_data[interrupts-1:0]; - if (csr == 5'h2) + if (csr == 4 'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -76060,9 +76087,8 @@ always @(posedge clk_i ) ie <= 1'b0; eie <= 1'b0; + - bie <= 1'b0; - ip <= {interrupts{1'b0}}; eie_delay <= 0; @@ -76072,21 +76098,13 @@ always @(posedge clk_i ) ip <= asserted; - - if (non_debug_exception == 1'b1) - begin + + - eie <= ie; - ie <= 1'b0; - end - else if (debug_exception == 1'b1) - begin + + + - bie <= ie; - ie <= 1'b0; - end - - @@ -76094,6 +76112,14 @@ always @(posedge clk_i ) + if (exception == 1'b1) + begin + + eie <= ie; + ie <= 1'b0; + end + + else if (stall_x == 1'b0) begin @@ -76109,26 +76135,24 @@ always @(posedge clk_i ) end - - else if (bret_q_x == 1'b1) - ie <= bie; - + + + else if (csr_write_enable == 1'b1) begin - if (csr == 5'h0) + if (csr == 4 'h0) begin ie <= csr_write_data[0]; eie <= csr_write_data[1]; + - bie <= csr_write_data[2]; - end - if (csr == 5'h2) + if (csr == 4 'h2) ip <= asserted & ~csr_write_data[interrupts-1:0]; end end @@ -76747,6 +76771,7 @@ module lm32_top_minimal ( D_BTE_O ); +parameter eba_reset = 32'h00000000; @@ -76928,7 +76953,10 @@ endfunction -lm32_cpu_minimal cpu ( +lm32_cpu_minimal + #( + .eba_reset(eba_reset) + ) cpu ( .clk_i (clk_i), diff --git a/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd b/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd index 73b87ee..32b8a87 100644 --- a/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd +++ b/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd @@ -4,7 +4,8 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wishbone_pkg.all; entity xwb_lm32 is -generic(g_profile: string); +generic(g_profile: string; +g_reset_vector: std_logic_vector(31 downto 0) := x"00000000"); port( clk_sys_i : in std_logic; rst_n_i : in std_logic; @@ -37,7 +38,9 @@ if profile_name = "full" then return 4; end if; if profile_name = "full_debug" then return 4; end if; return 0; end function; -component lm32_top_minimal is port ( +component lm32_top_minimal is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -69,7 +72,9 @@ component lm32_top_minimal is port ( D_LOCK_O : out std_logic; D_BTE_O : out std_logic_vector(1 downto 0)); end component; -component lm32_top_medium is port ( +component lm32_top_medium is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -101,7 +106,9 @@ component lm32_top_medium is port ( D_LOCK_O : out std_logic; D_BTE_O : out std_logic_vector(1 downto 0)); end component; -component lm32_top_medium_icache is port ( +component lm32_top_medium_icache is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -133,7 +140,9 @@ component lm32_top_medium_icache is port ( D_LOCK_O : out std_logic; D_BTE_O : out std_logic_vector(1 downto 0)); end component; -component lm32_top_medium_debug is port ( +component lm32_top_medium_debug is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -165,7 +174,9 @@ component lm32_top_medium_debug is port ( D_LOCK_O : out std_logic; D_BTE_O : out std_logic_vector(1 downto 0)); end component; -component lm32_top_medium_icache_debug is port ( +component lm32_top_medium_icache_debug is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -197,7 +208,9 @@ component lm32_top_medium_icache_debug is port ( D_LOCK_O : out std_logic; D_BTE_O : out std_logic_vector(1 downto 0)); end component; -component lm32_top_full is port ( +component lm32_top_full is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -229,7 +242,9 @@ component lm32_top_full is port ( D_LOCK_O : out std_logic; D_BTE_O : out std_logic_vector(1 downto 0)); end component; -component lm32_top_full_debug is port ( +component lm32_top_full_debug is +generic ( eba_reset: std_logic_vector(31 downto 0) ); +port ( clk_i : in std_logic; rst_i : in std_logic; @@ -326,6 +341,8 @@ begin gen_profile_minimal: if (g_profile = "minimal") generate U_Wrapped_LM32: lm32_top_minimal +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, @@ -367,6 +384,8 @@ end generate gen_profile_minimal; gen_profile_medium: if (g_profile = "medium") generate U_Wrapped_LM32: lm32_top_medium +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, @@ -408,6 +427,8 @@ end generate gen_profile_medium; gen_profile_medium_icache: if (g_profile = "medium_icache") generate U_Wrapped_LM32: lm32_top_medium_icache +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, @@ -449,6 +470,8 @@ end generate gen_profile_medium_icache; gen_profile_medium_debug: if (g_profile = "medium_debug") generate U_Wrapped_LM32: lm32_top_medium_debug +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, @@ -490,6 +513,8 @@ end generate gen_profile_medium_debug; gen_profile_medium_icache_debug: if (g_profile = "medium_icache_debug") generate U_Wrapped_LM32: lm32_top_medium_icache_debug +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, @@ -531,6 +556,8 @@ end generate gen_profile_medium_icache_debug; gen_profile_full: if (g_profile = "full") generate U_Wrapped_LM32: lm32_top_full +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, @@ -572,6 +599,8 @@ end generate gen_profile_full; gen_profile_full_debug: if (g_profile = "full_debug") generate U_Wrapped_LM32: lm32_top_full_debug +generic map ( + eba_reset => g_reset_vector) port map( clk_i => clk_sys_i, rst_i => rst, diff --git a/modules/wishbone/wb_lm32/src/lm32_top.v b/modules/wishbone/wb_lm32/src/lm32_top.v index 9d8a037..7003859 100644 --- a/modules/wishbone/wb_lm32/src/lm32_top.v +++ b/modules/wishbone/wb_lm32/src/lm32_top.v @@ -89,6 +89,7 @@ module lm32_top ( D_BTE_O ); +parameter eba_reset = 32'h00000000; ///////////////////////////////////////////////////// // Inputs ///////////////////////////////////////////////////// @@ -210,7 +211,10 @@ wire trace_bret; // Indicates a bret instruction ///////////////////////////////////////////////////// // LM32 CPU -lm32_cpu cpu ( +lm32_cpu + #( + .eba_reset(eba_reset) + ) cpu ( // ----- Inputs ------- .clk_i (clk_i), `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd index 35f6f24..105cced 100644 --- a/modules/wishbone/wishbone_pkg.vhd +++ b/modules/wishbone/wishbone_pkg.vhd @@ -520,7 +520,8 @@ package wishbone_pkg is component xwb_lm32 generic ( - g_profile : string); + g_profile : string; + g_reset_vector : std_logic_vector(31 downto 0) := x"00000000"); port ( clk_sys_i : in std_logic; rst_n_i : in std_logic; diff --git a/testbench/wishbone/lm32_testsys/lm32_test_system.vhd b/testbench/wishbone/lm32_testsys/lm32_test_system.vhd index 02fc46f..7ad2f8b 100644 --- a/testbench/wishbone/lm32_testsys/lm32_test_system.vhd +++ b/testbench/wishbone/lm32_testsys/lm32_test_system.vhd @@ -35,8 +35,8 @@ architecture rtl of lm32_test_system is constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) := - (0 => x"00000000", -- 64KB of fpga memory - 1 => x"10000000", -- The second port to the same memory + (0 => x"00880000", -- 64KB of fpga memory + 1 => x"10880000", -- The second port to the same memory 2 => x"20000000"); -- Peripherals constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) := @@ -50,7 +50,8 @@ begin -- rtl U_CPU : xwb_lm32 generic map ( - g_profile => "medium") + g_profile => "medium", + g_reset_vector => x"00880000") port map ( clk_sys_i => clk_sys_i, rst_n_i => rst_n_i, diff --git a/testbench/wishbone/lm32_testsys/sw/main.ram b/testbench/wishbone/lm32_testsys/sw/main.ram index 43e4885..b3242a8 100644 --- a/testbench/wishbone/lm32_testsys/sw/main.ram +++ b/testbench/wishbone/lm32_testsys/sw/main.ram @@ -1,7 +1,7 @@ write 0 98000000 write 1 D0000000 write 2 D0200000 -write 3 78010000 +write 3 78010088 write 4 38210000 write 5 D0E10000 write 6 F800003A @@ -63,17 +63,17 @@ write 3d 00000000 write 3e 00000000 write 3f 00000000 write 40 98000000 -write 41 781C0000 +write 41 781C0088 write 42 3B9CFFFC -write 43 781A0000 +write 43 781A0088 write 44 3B5A8390 -write 45 78010000 -write 46 38210394 +write 45 78010088 +write 46 382103A0 write 47 34020000 -write 48 78030000 -write 49 38630394 +write 48 78030088 +write 49 386303A0 write 4a C8611800 -write 4b F800005F +write 4b F800005C write 4c 34010000 write 4d 34020000 write 4e 34030000 @@ -119,112 +119,115 @@ write 75 379CFFFC write 76 5B9D0004 write 77 F8000014 write 78 34010055 -write 79 F8000017 +write 79 F8000016 write 7a 34010055 -write 7b F8000015 +write 7b F8000014 write 7c 34010055 -write 7d F8000013 +write 7d F8000012 write 7e 34010055 -write 7f F8000011 +write 7f F8000010 write 80 34010055 -write 81 F800000F +write 81 F800000E write 82 34010055 -write 83 F800000D +write 83 F800000C write 84 34010055 -write 85 F800000B +write 85 F800000A write 86 34010055 -write 87 F8000009 +write 87 F8000008 write 88 2B9D0004 write 89 379C0004 write 8a C3A00000 -write 8b 78012000 -write 8c 38210000 -write 8d 3402147B -write 8e 58220004 -write 8f C3A00000 -write 90 379CFFFC -write 91 5B9D0004 -write 92 78022000 -write 93 202300FF -write 94 38420000 -write 95 28410000 -write 96 20210001 -write 97 5C20FFFE -write 98 58430008 -write 99 3401000A -write 9a 5C610003 -write 9b 3401000D -write 9c FBFFFFF4 -write 9d 2B9D0004 -write 9e 379C0004 -write 9f C3A00000 -write a0 78012000 -write a1 38210000 -write a2 28210000 -write a3 20210002 -write a4 C3A00000 -write a5 78012000 -write a6 38210000 -write a7 2821000C -write a8 202100FF -write a9 C3A00000 -write aa B8204000 -write ab B8202800 -write ac 34010003 -write ad B8602000 -write ae 204900FF -write af 50230023 -write b0 A1010800 -write b1 44200009 -write b2 212200FF -write b3 34030000 -write b4 B4A30800 -write b5 30220000 -write b6 34630001 -write b7 5C64FFFD -write b8 B9000800 -write b9 C3A00000 -write ba 3D210008 -write bb 3403000F -write bc B8290800 -write bd 3C220010 -write be B9003800 -write bf B8412800 -write c0 B8603000 -write c1 B9000800 -write c2 B8801000 -write c3 54830011 -write c4 34030000 -write c5 34060003 -write c6 B4E31000 -write c7 34630004 -write c8 58450000 -write c9 C8830800 -write ca 5426FFFC -write cb 3482FFFC -write cc 00410002 -write cd 20440003 -write ce 34210001 -write cf 3C210002 -write d0 B4E13800 -write d1 B8E02800 -write d2 5C80FFE0 -write d3 E3FFFFE5 -write d4 58250000 -write d5 58250004 -write d6 58250008 -write d7 5825000C -write d8 3442FFF0 -write d9 34210010 -write da 5446FFFA -write db 3481FFF0 -write dc 00220004 -write dd 2024000F -write de 34420001 -write df 3C420004 -write e0 34010003 -write e1 B5023800 -write e2 5481FFE2 -write e3 B8E02800 -write e4 E3FFFFEE -write e5 E3FFFFEE +write 8b 3402147B +write 8c 78012000 +write 8d 58220004 +write 8e C3A00000 +write 8f 379CFFFC +write 90 5B9D0004 +write 91 78022000 +write 92 202100FF +write 93 28430000 +write 94 20630001 +write 95 5C60FFFE +write 96 78022000 +write 97 58410008 +write 98 3402000A +write 99 5C220003 +write 9a 3401000D +write 9b FBFFFFF4 +write 9c 2B9D0004 +write 9d 379C0004 +write 9e C3A00000 +write 9f 78012000 +write a0 28210000 +write a1 20210002 +write a2 C3A00000 +write a3 78012000 +write a4 2821000C +write a5 202100FF +write a6 C3A00000 +write a7 20250003 +write a8 B8202000 +write a9 44A0000B +write aa 4460002C +write ab 3463FFFF +write ac 204600FF +write ad E0000003 +write ae 44600028 +write af 3463FFFF +write b0 30860000 +write b1 34840001 +write b2 20850003 +write b3 5CA0FFFB +write b4 34050003 +write b5 50A3001A +write b6 204500FF +write b7 3CA60008 +write b8 340A000F +write b9 B8C52800 +write ba 3CA60010 +write bb B8804000 +write bc B8C53000 +write bd B8603800 +write be B8802800 +write bf 3409000F +write c0 546A0017 +write c1 34040000 +write c2 34070003 +write c3 B5042800 +write c4 34840004 +write c5 58A60000 +write c6 C8642800 +write c7 54A7FFFC +write c8 3463FFFC +write c9 00640002 +write ca 20630003 +write cb 34840001 +write cc 3C840002 +write cd B5044000 +write ce B9002000 +write cf 44600007 +write d0 204200FF +write d1 34050000 +write d2 B4853000 +write d3 30C20000 +write d4 34A50001 +write d5 5C65FFFD +write d6 C3A00000 +write d7 58A60000 +write d8 58A60004 +write d9 58A60008 +write da 58A6000C +write db 34E7FFF0 +write dc 34A50010 +write dd 54E9FFFA +write de 3463FFF0 +write df 00680004 +write e0 2063000F +write e1 35080001 +write e2 3D080004 +write e3 B4884000 +write e4 34040003 +write e5 5464FFDC +write e6 B9002000 +write e7 E3FFFFE8 +write e8 E3FFFFE8 diff --git a/testbench/wishbone/lm32_testsys/sw/target/lm32/ram.ld b/testbench/wishbone/lm32_testsys/sw/target/lm32/ram.ld index 86ec2e9..c92e4da 100644 --- a/testbench/wishbone/lm32_testsys/sw/target/lm32/ram.ld +++ b/testbench/wishbone/lm32_testsys/sw/target/lm32/ram.ld @@ -31,7 +31,7 @@ GROUP(-lgcc -lc) MEMORY { - ram : ORIGIN = 0x00000000, LENGTH = 0x10000 + ram : ORIGIN = 0x00880000, LENGTH = 0x10000 } SECTIONS diff --git a/testbench/wishbone/lm32_testsys/wave.do b/testbench/wishbone/lm32_testsys/wave.do index c1c8f83..b41f072 100644 --- a/testbench/wishbone/lm32_testsys/wave.do +++ b/testbench/wishbone/lm32_testsys/wave.do @@ -9,8 +9,10 @@ add wave -noupdate /main/DUT/U_CPU/gen_profile_medium/U_Wrapped_LM32/D_ACK_I add wave -noupdate /main/DUT/U_CPU/data_was_busy add wave -noupdate /main/DUT/U_CPU/data_addr_reg add wave -noupdate /main/DUT/U_CPU/data_remaining +add wave -noupdate /main/DUT/U_CPU/iwb_o +add wave -noupdate /main/DUT/U_CPU/iwb_i TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2672526 ps} 0} +WaveRestoreCursors {{Cursor 1} {25475000 ps} 0} configure wave -namecolwidth 350 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -25,4 +27,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2262366 ps} {3082686 ps} +WaveRestoreZoom {0 ps} {105 us}