Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP

Loading…

Various changes #64

Merged
merged 3 commits into from

3 participants

@bgamari

I found the USART change to be useful. The other patch fixes incorrect memory offsets for the ADCs in the stm32f4's memory map.

@bgamari

Changed ADC_BASE to ADC_COMMON_BASE for clarify.

@karlp
Collaborator

Good catch on the adc dma stuff, looks like it was carried over from the f10yxx ref manual.

@esden esden referenced this pull request from a commit
@esden esden Merging pull request #64 Various changes
Merge remote-tracking branch 'bgamari/master'
44e350a
@esden esden merged commit 08a14a9 into from
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Commits on Nov 8, 2012
  1. @bgamari
Commits on Nov 15, 2012
  1. @bgamari
  2. @bgamari

    stm32/f4/adc: DMA can always be used with ADC2

    bgamari authored
    I can't find any evidence in the manual to support this comment's claim.
This page is out of date. Refresh to see the latest.
View
5 include/libopencm3/stm32/f4/memorymap.h
@@ -75,8 +75,9 @@
#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100)
+#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)
+#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)
/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800)
/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
View
2  include/libopencm3/stm32/usart.h
@@ -371,6 +371,8 @@ void usart_enable_rx_interrupt(u32 usart);
void usart_disable_rx_interrupt(u32 usart);
void usart_enable_tx_interrupt(u32 usart);
void usart_disable_tx_interrupt(u32 usart);
+void usart_enable_error_interrupt(u32 usart);
+void usart_disable_error_interrupt(u32 usart);
bool usart_get_flag(u32 usart, u32 flag);
bool usart_get_interrupt_source(u32 usart, u32 flag);
View
10 lib/stm32/f4/adc.c
@@ -435,17 +435,12 @@ void adc_set_right_aligned(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable DMA Transfers
-Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5.
-ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer
-mode.
-
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_dma(u32 adc)
{
- if ((adc == ADC1) | (adc == ADC3))
- ADC_CR2(adc) |= ADC_CR2_DMA;
+ ADC_CR2(adc) |= ADC_CR2_DMA;
}
/*-----------------------------------------------------------------------------*/
@@ -456,8 +451,7 @@ void adc_enable_dma(u32 adc)
void adc_disable_dma(u32 adc)
{
- if ((adc == ADC1) | (adc == ADC3))
- ADC_CR2(adc) &= ~ADC_CR2_DMA;
+ ADC_CR2(adc) &= ~ADC_CR2_DMA;
}
/*-----------------------------------------------------------------------------*/
View
21 lib/stm32/usart.c
@@ -398,6 +398,27 @@ void usart_disable_tx_interrupt(u32 usart)
USART_CR1(usart) &= ~USART_CR1_TXEIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Error Interrupt Enable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
+void usart_enable_error_interrupt(u32 usart)
+{
+ USART_CR3(usart) |= USART_CR3_EIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Error Interrupt Disable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
+void usart_disable_error_interrupt(u32 usart)
+{
+ USART_CR3(usart) &= ~USART_CR3_EIE;
+}
/*---------------------------------------------------------------------------*/
/** @brief USART Read a Status Flag.
Something went wrong with that request. Please try again.