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Initial classification hierarchy #235

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imphil opened this issue May 16, 2018 · 1 comment

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@imphil
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commented May 16, 2018

As discussed I've taken a bit of time to create an initial classification hierarchy for LibreCores. I'm not sure yet where we'll hit a sweet spot between details and abstraction. Unless someone has strong objections, let's go with that one and improve on it over time.

The format follows pypi (https://pypi.org/classifiers/).

License :: Free and Open :: permissive :: BSD
License :: Free and Open :: permissive :: MIT
License :: Free and Open :: permissive :: Apache License
License :: Free and Open :: permissive :: Solderpad License
License :: Free and Open :: permissive :: other
License :: Free and Open :: weak copyleft :: Mozilla Public License (MPL)
License :: Free and Open :: weak copyleft :: Solderpad License
License :: Free and Open :: weak copyleft :: GNU Lesser General Public License v2 (LGPLv2)
License :: Free and Open :: weak copyleft :: GNU Lesser General Public License v2 or later (LGPLv2+)
License :: Free and Open :: weak copyleft :: GNU Lesser General Public License v3 (LGPLv3)
License :: Free and Open :: weak copyleft :: GNU Lesser General Public License v3 or later (LGPLv3+)
License :: Free and Open :: weak copyleft :: other
License :: Free and Open :: copyleft :: GNU Public License v2 (GPLv2)
License :: Free and Open :: copyleft :: GNU Public License v2 or later (GPLv2+)
License :: Free and Open :: copyleft :: GNU Public License v3 (GPLv3)
License :: Free and Open :: copyleft :: GNU Public License v3 or later (GPLv3+)
License :: Other/Proprietary License
License :: Public Domain/CC0


Tool :: Simulation :: Verilator
Tool :: Simulation :: Icarus Verilog
Tool :: Simulation :: GHDL
Tool :: Simulation :: Synopsys VCS
Tool :: Simulation :: Mentor ModelSim/Questa
Tool :: Simulation :: Cadence Incisive (NCsim)
Tool :: Simulation :: Aldec Riviera
Tool :: Simulation :: other

Tool :: Synthesis/Implementation :: Synopsys Synplify
Tool :: Synthesis/Implementation :: Cadence Genus
Tool :: Synthesis/Implementation :: Xilinx Vivado
Tool :: Synthesis/Implementation :: Xilinx ISE
Tool :: Synthesis/Implementation :: Altera Quartus
Tool :: Synthesis/Implementation :: Yosys

Target :: Simulation

Target :: FPGA :: Xilinx :: Spartan 3
Target :: FPGA :: Xilinx :: Spartan 6
Target :: FPGA :: Xilinx :: 7 series
Target :: FPGA :: Xilinx :: UltraScale
Target :: FPGA :: Xilinx :: other
Target :: FPGA :: Altera/Intel
Target :: FPGA :: Lattice
Target :: FPGA :: Microsemi
Target :: FPGA :: other

Target :: ASIC

Proven on :: FPGA
Proven on :: ASIC

Programming Language :: Verilog :: Verilog 95
Programming Language :: Verilog :: Verilog 2001
Programming Language :: Verilog :: SystemVerilog 2005 (IEEE 1800-2005)
Programming Language :: Verilog :: SystemVerilog 2009 (IEEE 1800-2009)
Programming Language :: Verilog :: SystemVerilog 2012 (IEEE 1800-2012)
Programming Language :: Verilog :: SystemVerilog 2017 (IEEE 1800-2017)
Programming Language :: VHDL :: VHDL 1987/1993/2000/2002 (IEEE 1076-1987/1993/2000/2002)
Programming Language :: VHDL :: VHDL 2008 (IEEE 1076-2008)
Programming Language :: Chisel
Programming Language :: MyHDL
Programming Language :: TL-Verilog
Programming Language :: SystemC
Programming Language :: C
Programming Language :: C++
Programming Language :: Perl
Programming Language :: Python
Programming Language :: Java
Programming Language :: TCL
Programming Language :: other

Topic :: Hardware :: CPU :: OpenRISC
Topic :: Hardware :: CPU :: RISC-V
Topic :: Hardware :: CPU :: other
Topic :: Hardware :: GPU
Topic :: Hardware :: DSP
Topic :: Hardware :: I/O :: UART
Topic :: Hardware :: I/O :: USB
Topic :: Hardware :: I/O :: PCI Express (PCIe)
Topic :: Hardware :: I/O :: GPIO
Topic :: Hardware :: I/O :: Ethernet
Topic :: Hardware :: Interconnect :: Wishbone
Topic :: Hardware :: Interconnect :: AXI
Topic :: Hardware :: Debug and Monitoring
Topic :: Hardware :: Crypto and Hashing
Topic :: Hardware :: other

Topic :: Software :: Application
Topic :: Software :: Library

Support :: Commercially supported
Support :: Community supported

LibreCores :: Featured

Weak spots currently:

  • I clearly have very little knowledge about non-Xilinx FPGA families. Help wanted to fill in details.
  • I'm inclined to cut down the licenses part to a bare minimum (e.g. stop after permissive/weak copyleft, etc.). The details of the license can be already (and in future) found in the separate license field, no need to "abuse" the categories feature to duplicate this information.

Please comment below if you have additions to this initial hierarchy, I'll update this text then to document the consensus.

@imphil

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commented Jul 9, 2018

Seems like we got nobody to disagree (or care), this is now commited.

@imphil imphil closed this Jul 9, 2018

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