This projects covers the 1st LibreSilicon Test Chip.
There is a tradition in the Silicon Foundry business to code name Process Control / Process Evaluation Modules (PCM/PEM) with big rivers. Following that tradition, we like to call the 1st LibreSilicon Test / Evaluation Wafer "Pearl River". The Pearl River (珠江) flows close to LibreSilicons rented 1st Clean Room Facility.
Currently we are using a patched version of Magic 8.2.
For the technology representing we patched the SCMOS technology file from Mosis. Our technology file is stored in the PearlRiver Repository.
All Layout files are stored inside
- Library/magic Folder, and
- Layout/magic Folder.
For evaluating relevant parameters, we are using test structures which are placed in form of a triangle; representing the bottom, left, upper and right side of the die.
View Layout files with
magic -T scmos.tech Layout/magic/PearlRiver_quarter.mag
for the quarters, or
magic -T scmos.tech Layout/magic/PearlRiver_die.mag
for the whole die.
For documentation we are using LaTeX.
All LaTeX files are stored inside
- Documentation/LaTeX Folder
Please read the documentation carefully.
If you do not understand, what the hack we are doing here, please sit back with a good textbook about CMOS or ASIC technology development and learn. Please come back later.
This branch was created to add the high-voltage NMOS device.