MStar MSC313: MIU DDR controller driver

linux-chenxing · Jul 19, 2021 · f3a4f3d81314124e8a3b3a38ba8cb49dc711383c · f3a4f3d
1 parent cbe9cdb
commit f3a4f3d81314124e8a3b3a38ba8cb49dc711383c
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diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi
@@ -64,3 +64,7 @@
 	interrupts-extended = <&gpio_pm 0 29 IRQ_TYPE_LEVEL_HIGH>;
 			      /*<&intc_fiq 23 IRQ_TYPE_LEVEL_HIGH>;*/
 };
+
+&miu {
+	compatible = "mstar,ssc8336-miu";
+};
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -579,6 +579,26 @@
 				#dma-cells = <1>;
 			};
 
+			miu: miu@202000 {
+				compatible = "mstar,msc313-miu";
+				reg = <0x202000	0x200>,
+				      <0x202400 0x200>,
+				      <0x202200 0x200>;
+				interrupt-parent = <&intc_irq>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "miu", "ddr";
+				clocks = <&clkgen MSC313_CLKGEN_DEGLITCHES MSC313_CLKGEN_MIU 0>,
+					 <&clkgen MSC313_CLKGEN_DEGLITCHES MSC313_CLKGEN_DDR_SYN 0>;
+				/*mstar,rd-timing = <0xB>;*/
+				mstar,trcd = <0x6>;
+				mstar,trp = <0x6>;
+				#clock-cells = <0>;
+				clock-output-names = "ddrpll";
+				/* Comments suggest the miu size is 256MB */
+				dma-ranges = <0x00000000 0x20000000 0x10000000>;
+				#interconnect-cells = <1>;
+			};
+
 			l3bridge: l3bridge@204400 {
 				compatible = "mstar,l3bridge";
 				reg = <0x204400 0x200>;

diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_TI_EMIF)		+= emif.o
 obj-$(CONFIG_OMAP_GPMC)		+= omap-gpmc.o
 obj-$(CONFIG_FSL_CORENET_CF)	+= fsl-corenet-cf.o
 obj-$(CONFIG_FSL_IFC)		+= fsl_ifc.o
+obj-$(CONFIG_ARCH_MSTARV7)	+= mstar-msc313_miu.o
 obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
 obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
 obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o