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fel: Faster USB transfers via 'fel write' to DRAM
By adjusting the MMU translation table before restoring it and by enabling the I-cache with branch prediction, we can improve performance. The DRAM area (0x40000000-0xC0000000) becomes write-combine mapped and the BROM code becomes mapped as cacheable memory. This is expected to be safe and should not cause any coherency problems. Transfer speed improvements: A10 : ~330 KB/s -> ~600 KB/s A13 : ~330 KB/s -> ~600 KB/s A20 : ~320 KB/s -> ~960 KB/s A31s : ~250 KB/s -> ~510 KB/s Signed-off-by: Siarhei Siamashka <firstname.lastname@example.org> Acked-by: Hans de Goede <email@example.com>
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