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fel: Set the AUXCR L2EN bit for A10/A13
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. And if L2EN is not set, then the Linux system ends up booted with the L2 cache disabled. According to the Cortex-A8 TRM, the L2 cache is only enabled when both L2EN bit and the C bit from the CP15 Control Register c1 are set. Because the BROM does not set the C bit, this change should not affect the functionality of the FEL mode in any way. Signed-off-by: Siarhei Siamashka <firstname.lastname@example.org> Acked-by: Hans de Goede <email@example.com>
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