diff --git a/drivers/gpu/drm/i915_legacy/intel_dp_mst.c b/drivers/gpu/drm/i915_legacy/intel_dp_mst.c
index 46d54efc1b28..ffdc80bfde15 100644
--- a/drivers/gpu/drm/i915_legacy/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915_legacy/intel_dp_mst.c
@@ -125,7 +125,15 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
 	limits.min_bpp = intel_dp_min_bpp(pipe_config);
-	limits.max_bpp = pipe_config->pipe_bpp;
+	/*
+	 * FIXME: If all the streams can't fit into the link with
+	 * their current pipe_bpp we should reduce pipe_bpp across
+	 * the board until things start to fit. Until then we
+	 * limit to <= 8bpc since that's what was hardcoded for all
+	 * MST streams previously. This hack should be removed once
+	 * we have the proper retry logic in place.
+	 */
+	limits.max_bpp = min(pipe_config->pipe_bpp, 24);
 
 	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
 
diff --git a/drivers/gpu/drm/i915_legacy/intel_workarounds.c b/drivers/gpu/drm/i915_legacy/intel_workarounds.c
index edd57a5e0495..b50a7c3f22bf 100644
--- a/drivers/gpu/drm/i915_legacy/intel_workarounds.c
+++ b/drivers/gpu/drm/i915_legacy/intel_workarounds.c
@@ -294,11 +294,6 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine)
 			  FLOW_CONTROL_ENABLE |
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
-	if (!IS_COFFEELAKE(i915))
-		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
-				  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
-
 	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
 	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,