diff --git a/Config.in b/Config.in index 16962fe44..d1069354b 100644 --- a/Config.in +++ b/Config.in @@ -71,7 +71,7 @@ config CONFIG_OS_MEM_BANK config CONFIG_OS_MEM_SIZE string "Extern Memory Bank Size" default "0x20000000" if CONFIG_SAMA5D3XEK - default "0x8000000" if CONFIG_AT91SAM9X5EK || CONFIG_AT91SAM9N12EK + default "0x8000000" if CONFIG_AT91SAM9X5EK || CONFIG_AT91ARIAG25 || CONFIG_AT91SAM9N12EK default "0x4000000" config CONFIG_LINUX_KERNEL_ARG_STRING @@ -94,6 +94,7 @@ config CONFIG_LINUX_KERNEL_ARG_STRING default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9263EK && CONFIG_SDCARD default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9XEEK && CONFIG_SDCARD default "mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9X5EK && CONFIG_SDCARD + default "mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91ARIAG25 && CONFIG_SDCARD default "mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9N12EK && CONFIG_SDCARD default "mem=512M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_SAMA5D3XEK && CONFIG_SDCARD default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9M10G45EK && CONFIG_SDCARD @@ -168,7 +169,7 @@ config CONFIG_OS_MEM_BANK config CONFIG_OS_MEM_SIZE string "Extern Memory Bank Size" default "0x20000000" if CONFIG_SAMA5D3XEK - default "0x8000000" if CONFIG_AT91SAM9X5EK || CONFIG_AT91SAM9N12EK + default "0x8000000" if CONFIG_AT91SAM9X5EK || CONFIG_AT91ARIAG25 || CONFIG_AT91SAM9N12EK default "0x4000000" config CONFIG_LINUX_KERNEL_ARG_STRING @@ -262,7 +263,7 @@ config CONFIG_IMG_SIZE config CONFIG_JUMP_ADDR string "The External Ram Address to Load U-Boot Image" default "0x73F00000" if CONFIG_AT91SAM9M10G45EK - default "0x26F00000" if CONFIG_AT91SAM9X5EK || CONFIG_AT91SAM9N12EK || CONFIG_SAMA5D3XEK + default "0x26F00000" if CONFIG_AT91SAM9X5EK || CONFIG_AT91ARIAG25 || CONFIG_AT91SAM9N12EK || CONFIG_AT91SAMA5D3XEK default "0x21F00000" if CONFIG_AT91SAM9260EK || CONFIG_AT91SAM9261EK || CONFIG_AT91SAM9263EK || CONFIG_AT91SAM9G10EK || CONFIG_AT91SAM9G20EK || CONFIG_AT91SAM9RLEK default "0x23F00000" help @@ -356,7 +357,7 @@ config CONFIG_THUMB Build code in thumb mode config CONFIG_SCLK - depends on CONFIG_AT91SAM9RLEK || CONFIG_AT91SAM9M10G45EK || CONFIG_AT91SAM9X5EK || CONFIG_AT91SAM9N12EK || CONFIG_SAMA5D3XEK + depends on CONFIG_AT91SAM9RLEK || CONFIG_AT91SAM9M10G45EK || CONFIG_AT91SAM9X5EK || CONFIG_AT91ARIAG25 || CONFIG_AT91SAM9N12EK || CONFIG_AT91SAMA5D3XEK bool "Use external 32KHZ oscillator as source of slow clock" help Use external 32KHZ oscillator as source of slow clock diff --git a/board/Config.in b/board/Config.in index b99b6cdfc..9a22f66c5 100644 --- a/board/Config.in +++ b/board/Config.in @@ -156,6 +156,19 @@ config CONFIG_AT91SAM9X5EK help Use the AT91SAM9X5EK Development board +config CONFIG_AT91ARIAG25 + bool "at91ariag25" + select CONFIG_DDR2 + select ALLOW_SDCARD + select ALLOW_HSMCI + select ALLOW_CPU_CLK_400MHZ + select ALLOW_CRYSTAL_12_000MHZ + select ALLOW_PIO3 + select CPU_HAS_PMECC + help + Use the ARIAG25 SoM + + config CONFIG_AT91SAM9N12EK bool "at91sam9n12ek" select CONFIG_DDR2 @@ -207,6 +220,7 @@ config CONFIG_CHIP default "AT91SAM9G20" if CONFIG_AT91SAM9G20EK default "AT91SAM9G45" if CONFIG_AT91SAM9M10G45EK default "AT91SAM9X5" if CONFIG_AT91SAM9X5EK + default "AT91SAM9X5" if CONFIG_AT91ARIAG25 default "AT91SAM9N12" if CONFIG_AT91SAM9N12EK default "SAMA5D3X" if CONFIG_SAMA5D3XEK help @@ -223,6 +237,7 @@ config CONFIG_BOARD default "at91sam9g10ek" if CONFIG_AT91SAM9G10EK default "at91sam9g20ek" if CONFIG_AT91SAM9G20EK default "at91sam9x5ek" if CONFIG_AT91SAM9X5EK + default "at91ariag25" if CONFIG_AT91ARIAG25 default "at91sam9n12ek" if CONFIG_AT91SAM9N12EK default "at91sam9m10g45ek" if CONFIG_AT91SAM9M10G45EK default "sama5d3xek" if CONFIG_SAMA5D3XEK @@ -241,6 +256,7 @@ config CONFIG_MACH_TYPE default "0x658" if CONFIG_AT91SAM9G20EK default "1830" if CONFIG_AT91SAM9M10G45EK # 1830 default "3373" if CONFIG_AT91SAM9X5EK # 3373 + default "4149" if CONFIG_AT91ARIAG25 default "9999" if CONFIG_AT91SAM9N12EK default "9999" if CONFIG_SAMA5D3XEK help @@ -267,6 +283,7 @@ config CONFIG_TOP_OF_MEMORY default "0x304000" if CONFIG_AT91SAM9G20EK default "0x30A000" if CONFIG_AT91SAM9M10G45EK default "0x308000" if CONFIG_AT91SAM9X5EK + default "0x308000" if CONFIG_AT91ARIAG25 default "0x308000" if CONFIG_AT91SAM9N12EK default "0x310000" if CONFIG_SAMA5D3XEK help diff --git a/board/at91ariag25/at91ariag25.c b/board/at91ariag25/at91ariag25.c new file mode 100644 index 000000000..aa6af5869 --- /dev/null +++ b/board/at91ariag25/at91ariag25.c @@ -0,0 +1,391 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * Copyright (c) 2013, Acme Systems srl + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "common.h" +#include "hardware.h" +#include "arch/at91_ccfg.h" +#include "arch/at91_rstc.h" +#include "arch/at91_pmc.h" +#include "arch/at91_smc.h" +#include "arch/at91_pio.h" +#include "arch/at91_ddrsdrc.h" +#include "gpio.h" +#include "pmc.h" +#include "usart.h" +#include "debug.h" +#include "ddramc.h" +#include "slowclk.h" +#include "timer.h" +#include "watchdog.h" +#include "string.h" +#include "at91ariag25.h" + +#include "onewire_info.h" + +#ifdef CONFIG_USER_HW_INIT +extern void hw_init_hook(void); +#endif + +static void at91_dbgu_hw_init(void) +{ + /* Configure DBGU pins */ + const struct pio_desc dbgu_pins[] = { + {"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + /* Configure the dbgu pins */ + pmc_enable_periph_clock(AT91C_ID_PIOA_B); + pio_configure(dbgu_pins); +} + +static void initialize_dbgu(void) +{ + at91_dbgu_hw_init(); + usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE)); +} + +// addressing RTC lockup at reboot and correct working of wakeup function to be able to restart the board +// (needs to short SHDN with EN5V) 29 08 2013 +#ifndef RTC_IDR +#define RTC_IDR 0x24 +#endif + +static void initialize_rtc(void) +{ + /* disable all RTC interrupts, just in case */ + writel(0xffffffff, (RTC_IDR + AT91C_BASE_RTC)); + writel(0xfffffe14, 0x20003); // to enable raise of SHDN line when rtc wakes up to correct start the board again +} +// end 29 08 2013 + +#ifdef CONFIG_DDR2 +/* Using the Micron MT47H64M16HR-3 */ +static void ddramc_reg_config(struct ddramc_register *ddramc_config) +{ + ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS + | AT91C_DDRC2_MD_DDR2_SDRAM); + + ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */ + | AT91C_DDRC2_NR_13 /* 13 row bits (8K) */ + | AT91C_DDRC2_CAS_3 /* CAS Latency 3 */ + | AT91C_DDRC2_NB_BANKS_8 /* 8 banks */ + | AT91C_DDRC2_DLL_RESET_DISABLED /* DLL not reset */ + | AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/ + + /* + * Make sure to uncomment the following line if the DDR controller + * shares the EBI with another memory controller (SMC, NAND,..). + * For instance, AT91C_DDRC2_EBISHARE shall be set if NAND flash + * data line 0 is positioned on EBI data line 0 (AT91C_EBI_NFD0_ON_D16 bit + * cleared in CCFG_EBICSA register). + * + * For Atmel AT91SAM9x5-EK revision B onwards, this AT91C_DDRC2_EBISHARE bit + * is cleared because the NAND flash data line 0 is positioned on EBI + * data line number 16 (AT91C_EBI_NFD0_ON_D16 bit set in CCFG_EBICSA + * register). Only the DDR controller function is thus used on lower + * EBI data lines. + */ + //ddramc_config->cr |= AT91C_DDRC2_EBISHARE; /* DQM is shared with other controller */ + + + /* + * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us. + * With a 133 MHz frequency, the refresh timer count register must to be + * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824 + * or (7.81 x 133 MHz) ~ 1040 i.e. 0x410. + */ + ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */ + + /* One clock cycle @ 133 MHz = 7.5 ns */ + ddramc_config->t0pr = (AT91C_DDRC2_TRAS_6 /* 6 * 7.5 = 45 ns */ + | AT91C_DDRC2_TRCD_2 /* 2 * 7.5 = 22.5 ns */ + | AT91C_DDRC2_TWR_2 /* 2 * 7.5 = 15 ns */ + | AT91C_DDRC2_TRC_8 /* 8 * 7.5 = 75 ns */ + | AT91C_DDRC2_TRP_2 /* 2 * 7.5 = 15 ns */ + | AT91C_DDRC2_TRRD_2 /* 2 * 7.5 = 15 ns */ + | AT91C_DDRC2_TWTR_2 /* 2 clock cycles min */ + | AT91C_DDRC2_TMRD_2); /* 2 clock cycles */ + + ddramc_config->t1pr = (AT91C_DDRC2_TXP_2 /* 2 clock cycles */ + | AT91C_DDRC2_TXSRD_200 /* 200 clock cycles */ + | AT91C_DDRC2_TXSNR_19 /* 19 * 7.5 = 142.5 ns*/ + | AT91C_DDRC2_TRFC_18); /* 18 * 7.5 = 135 ns */ + + ddramc_config->t2pr = (AT91C_DDRC2_TFAW_7 /* 7 * 7.5 = 52.5 ns */ + | AT91C_DDRC2_TRTP_2 /* 2 clock cycles min */ + | AT91C_DDRC2_TRPA_3 /* 3 * 7.5 = 22.5 ns */ + | AT91C_DDRC2_TXARDS_7 /* 7 clock cycles */ + | AT91C_DDRC2_TXARD_2); /* 2 clock cycles */ +} + +static void ddramc_init(void) +{ + unsigned long csa; + struct ddramc_register ddramc_reg; + + ddramc_reg_config(&ddramc_reg); + + /* ENABLE DDR2 clock */ + writel(AT91C_PMC_DDR, AT91C_BASE_PMC + PMC_SCER); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + csa |= AT91C_EBI_CS1A_SDRAMC; + /*csa &= ~AT91C_EBI_DBPUC; + csa |= AT91C_EBI_DBPDC; + csa |= AT91C_EBI_DRV_HD;*/ + + writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA); + + /* DDRAM2 Controller initialize */ + ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg); +} +#endif /* #ifdef CONFIG_DDR2 */ + +static void one_wire_hw_init(void) +{ + const struct pio_desc wire_pio[] = { + {"1-Wire", AT91C_PIN_PB(18), 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + pmc_enable_periph_clock(AT91C_ID_PIOA_B); + pio_configure(wire_pio); +} + +#ifdef CONFIG_HW_INIT +void hw_init(void) +{ + /* Disable watchdog */ + at91_disable_wdt(); + + /* At this stage the main oscillator is + *supposed to be enabled PCK = MCK = MOSC + */ + pmc_init_pll(0); + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); + + /* PCK = PLLA/2 = 3 * MCK */ + pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT); + + /* Switch MCK on PLLA output */ + pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT); + + /*Enable External Reset */ + writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); + + /* Init timer */ + timer_init(); + +#ifdef CONFIG_SCLK + slowclk_enable_osc32(); +#endif + +// addressing RTC lockup at reboot and correct working of wakeup function to be able to restart the board +// (needs to short SHDN with EN5V) 29 08 2013 + /* Initialize realtime clock (RTC) */ + initialize_rtc(); +// end 29 08 2013 + + /* Initialize dbgu */ + initialize_dbgu(); + +#ifdef CONFIG_DDR2 + /* Initialize DDRAM Controller */ + ddramc_init(); +#endif + /* one wire pin init */ + one_wire_hw_init(); + +#ifdef CONFIG_USER_HW_INIT + hw_init_hook(); +#endif +} +#endif /* #ifdef CONFIG_HW_INIT */ + +#ifdef CONFIG_DATAFLASH +void at91_spi0_hw_init(void) +{ + /* Configure PINs for SPI0 */ + const struct pio_desc spi0_pins[] = { + {"MISO", AT91C_PIN_PA(11), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"MOSI", AT91C_PIN_PA(12), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"SPCK", AT91C_PIN_PA(13), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + pmc_enable_periph_clock(AT91C_ID_PIOA_B); + pio_configure(spi0_pins); + + pmc_enable_periph_clock(AT91C_ID_SPI0); +} +#endif /* #ifdef CONFIG_DATAFLASH */ + +#ifdef CONFIG_SDCARD +static void sdcard_set_of_name_board(char *of_name) +{ +/* unsigned int cpu_board_id = get_cm_sn(); + unsigned int disp_board_id = get_dm_sn(); + + if (cpu_board_id == BOARD_ID_SAM9G15_CM) + strcpy(of_name, "at91sam9g15ek"); + else if (cpu_board_id == BOARD_ID_SAM9G25_CM) + strcpy(of_name, "at91sam9g25ek"); + else if (cpu_board_id == BOARD_ID_SAM9G35_CM) + strcpy(of_name, "at91sam9g35ek"); + else if (cpu_board_id == BOARD_ID_SAM9X25_CM) + strcpy(of_name, "at91sam9x25ek"); + else if (cpu_board_id == BOARD_ID_SAM9X35_CM) + strcpy(of_name, "at91sam9x35ek"); + else + dbg_log(1, "WARNING: Not correct CPU board ID\n\r"); + + if (disp_board_id == BOARD_ID_PDA_DM) + strcat(of_name, "_pda"); +*/ + strcat(of_name, ".dtb"); +} + +void at91_mci0_hw_init(void) +{ + const struct pio_desc mci_pins[] = { + {"MCCK", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCCDA", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCDA0", AT91C_PIN_PA(15), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCDA1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCDA2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCDA3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + /* Configure the PIO controller */ + pmc_enable_periph_clock(AT91C_ID_PIOA_B); + pio_configure(mci_pins); + + /* Enable the clock */ + writel((1 << AT91C_ID_HSMCI0), (PMC_PCER + AT91C_BASE_PMC)); + + /* Set of name function pointer */ + sdcard_set_of_name = &sdcard_set_of_name_board; +} +#endif /* #ifdef CONFIG_SDCARD */ + +#ifdef CONFIG_NANDFLASH +void nandflash_hw_init(void) +{ + unsigned int reg; + + /* Configure Nand PINs */ + const struct pio_desc nand_pins_hi[] = { + {"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT}, + {"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + const struct pio_desc nand_pins_lo[] = { + {"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + reg |= AT91C_EBI_CS3A_SM; + if (get_cm_rev() == 'A') + reg &= ~AT91C_EBI_NFD0_ON_D16; + else + reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); + + reg &= ~AT91C_EBI_DRV; + writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); + + /* Configure SMC CS3 */ + writel((AT91C_SMC_NWESETUP_(1) + | AT91C_SMC_NCS_WRSETUP_(0) + | AT91C_SMC_NRDSETUP_(2) + | AT91C_SMC_NCS_RDSETUP_(0)), + AT91C_BASE_SMC + SMC_SETUP3); + + writel((AT91C_SMC_NWEPULSE_(3) + | AT91C_SMC_NCS_WRPULSE_(5) + | AT91C_SMC_NRDPULSE_(4) + | AT91C_SMC_NCS_RDPULSE_(6)), + AT91C_BASE_SMC + SMC_PULSE3); + + writel((AT91C_SMC_NWECYCLE_(5) + | AT91C_SMC_NRDCYCLE_(7)), + AT91C_BASE_SMC + SMC_CYCLE3); + + writel((AT91C_SMC_READMODE + | AT91C_SMC_WRITEMODE + | AT91C_SMC_NWAITM_NWAIT_DISABLE + | AT91C_SMC_DBW_WIDTH_BITS_8 + | AT91_SMC_TDF_(1)), + AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ + if (get_cm_rev() == 'A') + pio_configure(nand_pins_lo); + else + pio_configure(nand_pins_hi); + + writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC)); +} + +void nandflash_config_buswidth(unsigned char busw) +{ + unsigned long csa; + + csa = readl(AT91C_BASE_SMC + SMC_CTRL3); + + if (busw == 0) + csa |= AT91C_SMC_DBW_WIDTH_BITS_8; + else + csa |= AT91C_SMC_DBW_WIDTH_BITS_16; + + writel(csa, AT91C_BASE_SMC + SMC_CTRL3); +} +#endif /* #ifdef CONFIG_NANDFLASH */ diff --git a/board/at91ariag25/at91ariag25.h b/board/at91ariag25/at91ariag25.h new file mode 100644 index 000000000..85dcb897a --- /dev/null +++ b/board/at91ariag25/at91ariag25.h @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __AT91ARIAG25_H__ +#define __AT91ARIAG25_H__ + +/* + * PMC Settings + * + * The main oscillator is enabled as soon as possible in the lowlevel_clock_init + * and MCK is switched on the main oscillator. + * PLL initialization is done later in the hw_init() function + */ +#define MASTER_CLOCK 132096000 +#define PLL_LOCK_TIMEOUT 10000 + +#define BAUD_RATE 115200 +#define BOARD_MAINOSC 12000000 +#define BOARD_MCK ((unsigned long)((BOARD_MAINOSC / 3 / 2 / 3) * 200)) +#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) +#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0) +#define BOARD_PLLACOUNT (0x3F << 8) +#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16)) +#define BOARD_DIVA (AT91C_CKGR_DIVA & 3) + +#define BOARD_PRESCALER_MAIN_CLOCK (AT91C_PMC_PLLADIV2_2 \ + | AT91C_PMC_MDIV_3 \ + | AT91C_PMC_CSS_MAIN_CLK) + +#define BOARD_PRESCALER_PLLA (AT91C_PMC_PLLADIV2_2 \ + | AT91C_PMC_MDIV_3 \ + | AT91C_PMC_CSS_PLLA_CLK) + +#define PLLA_SETTINGS (BOARD_CKGR_PLLA \ + | BOARD_PLLACOUNT \ + | BOARD_MULA \ + | BOARD_DIVA) + +#define PLLUTMI +#define PLLUTMI_SETTINGS 0x10193F05 + +/* + * DataFlash Settings + */ +#define CONFIG_SYS_SPI_CLOCK AT91C_SPI_CLK +#define CONFIG_SYS_SPI_BUS 0 +#define CONFIG_SYS_SPI_MODE SPI_MODE3 + +#if CONFIG_SYS_SPI_BUS == 0 +#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI0 +#elif CONFIG_SYS_SPI_BUS == 1 +#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI1 +#endif + +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(14) +#elif (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(7) +#endif + +/* + * NandFlash Settings + */ +#define CONFIG_SYS_NAND_BASE AT91C_BASE_CS3 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) + +#define CONFIG_SYS_NAND_OE_PIN AT91C_PIN_PD(0) +#define CONFIG_SYS_NAND_WE_PIN AT91C_PIN_PD(1) +#define CONFIG_SYS_NAND_ALE_PIN AT91C_PIN_PD(2) +#define CONFIG_SYS_NAND_CLE_PIN AT91C_PIN_PD(3) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91C_PIN_PD(4) + +#define PMECC_ERROR_CORR_BITS 2 +#define PMECC_SECTOR_SIZE 512 + +#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET 0xC000 +#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET 0x8000 + +#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET_1024 0x18000 +#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET_1024 0x10000 + +/* + * MCI Settings + */ +#define CONFIG_SYS_BASE_MCI AT91C_BASE_HSMCI0 + +/* + * One wire pin + */ +#define CONFIG_SYS_ONE_WIRE_PIN AT91C_PIN_PB(18) + +/* function */ +extern void hw_init(void); + +extern void nandflash_hw_init(void); +extern void nandflash_config_buswidth(unsigned char busw); + +extern void at91_spi0_hw_init(void); + +extern void at91_mci0_hw_init(void); + +#endif /*#ifndef __AT91ARIAG25_H__ */ diff --git a/board/at91ariag25/at91ariag25sd_linux_dt_defconfig b/board/at91ariag25/at91ariag25sd_linux_dt_defconfig new file mode 100644 index 000000000..02e938611 --- /dev/null +++ b/board/at91ariag25/at91ariag25sd_linux_dt_defconfig @@ -0,0 +1,108 @@ +# +# Default .config file for Aria G25 +# +HAVE_DOT_CONFIG=y +CONFIG_BOARDNAME="at91ariag25" +# CONFIG_AT91SAM9260EK is not set +# CONFIG_AT91SAM9261EK is not set +# CONFIG_AT91SAM9263EK is not set +# CONFIG_AT91SAM9RLEK is not set +# CONFIG_AT91SAM9XEEK is not set +# CONFIG_AT91SAM9G10EK is not set +# CONFIG_AT91SAM9G20EK is not set +# CONFIG_AT91SAM9M10G45EK is not set +# CONFIG_AT91SAM9X5EK is not set +CONFIG_AT91ARIAG25=y +# CONFIG_AT91SAM9N12EK is not set +# CONFIG_AT91SAMA5D3XEK is not set +CONFIG_CHIP="AT91SAM9X5" +CONFIG_BOARD="at91ariag25" +CONFIG_MACH_TYPE="4149" +CONFIG_LINK_ADDR="0x000000" +CONFIG_TOP_OF_MEMORY="0x308000" +CONFIG_CRYSTAL_12_000MHZ=y +# CONFIG_CRYSTAL_16_000MHZ is not set +# CONFIG_CRYSTAL_16_36766MHZ is not set +# CONFIG_CRYSTAL_18_432MHZ is not set +ALLOW_CRYSTAL_12_000MHZ=y +CONFIG_CRYSTAL="CRYSTAL_12_000MHZ" +# CONFIG_CPU_CLK_166MHZ is not set +# CONFIG_CPU_CLK_180MHZ is not set +# CONFIG_CPU_CLK_200MHZ is not set +# CONFIG_CPU_CLK_240MHZ is not set +# CONFIG_CPU_CLK_266MHZ is not set +CONFIG_CPU_CLK_400MHZ=y +# CONFIG_CPU_CLK_533MHZ is not set +ALLOW_CPU_CLK_400MHZ=y +# DISABLE_CPU_CLK_240MHZ is not set +# CONFIG_BUS_SPEED_83MHZ is not set +# CONFIG_BUS_SPEED_90MHZ is not set +# CONFIG_BUS_SPEED_100MHZ is not set +CONFIG_BUS_SPEED_133MHZ=y +ALLOW_PIO3=y +CONFIG_HAS_PIO3=y +CPU_HAS_PMECC=y +# CONFIG_LOAD_ONE_WIRE is not set +# CONFIG_MMC_SUPPORT is not set + +# +# Memory selection +# +# CONFIG_SDRAM is not set +# CONFIG_SDDRC is not set +CONFIG_DDR2=y +# ALLOW_DATAFLASH is not set +# ALLOW_FLASH is not set +# ALLOW_NANDFLASH is not set +ALLOW_SDCARD=y +ALLOW_HSMCI=y +# ALLOW_PSRAM is not set +# ALLOW_SDRAM_16BIT is not set +# CONFIG_RAM_32MB is not set +# CONFIG_RAM_64MB is not set +# CONFIG_RAM_128MB is not set +CONFIG_RAM_256MB=y +# CONFIG_RAM_512MB is not set +# CONFIG_DATAFLASH is not set +# CONFIG_FLASH is not set +# CONFIG_NANDFLASH is not set +CONFIG_SDCARD=y +CONFIG_MEMORY="sdcard" + +# +# SD Card Configuration +# +# CONFIG_SDCARD_HS is not set +CONFIG_FATFS=y +CONFIG_LONG_FILENAME=y +CONFIG_BOOTSTRAP_MAXSIZE="23000" +CONFIG_PROJECT="sdcard" +# CONFIG_LOAD_UBOOT is not set +CONFIG_LOAD_LINUX=y +# CONFIG_LOAD_ANDROID is not set +# CONFIG_LOAD_1MB is not set +# CONFIG_LOAD_4MB is not set +# CONFIG_LOAD_64KB is not set + +# +# Linux Image Storage Setup +# +CONFIG_OS_MEM_BANK="0x20000000" +CONFIG_OS_MEM_SIZE="0x10000000" +CONFIG_LINUX_KERNEL_ARG_STRING="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootdelay=1" +CONFIG_OS_IMAGE_NAME="image.bin" +CONFIG_JUMP_ADDR="0x22000000" +CONFIG_OF_LIBFDT=y +CONFIG_OF_FILENAME="at91-ariag25" +CONFIG_OF_ADDRESS="0x21000000" +CONFIG_IMAGE_NAME="linux" +# CONFIG_LONG_TEST is not set +CONFIG_DEBUG=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_LOUD is not set +# CONFIG_DEBUG_VERY_LOUD is not set +CONFIG_HW_INIT=y +# CONFIG_USER_HW_INIT is not set +# CONFIG_THUMB is not set +CONFIG_SCLK=y +CONFIG_DISABLE_WATCHDOG=y diff --git a/board/at91ariag25/board.mk b/board/at91ariag25/board.mk new file mode 100644 index 000000000..446973ca2 --- /dev/null +++ b/board/at91ariag25/board.mk @@ -0,0 +1,7 @@ +CPPFLAGS += \ + -DCONFIG_AT91ARIAG25 \ + -mcpu=arm926ej-s + +ASFLAGS += \ + -DCONFIG_AT91ARIAG25 \ + -mcpu=arm926ej-s diff --git a/include/board.h b/include/board.h index 29024338c..2ad79a740 100644 --- a/include/board.h +++ b/include/board.h @@ -64,6 +64,10 @@ #include "at91sam9x5ek.h" #endif +#ifdef CONFIG_AT91ARIAG25 +#include "at91ariag25.h" +#endif + #ifdef CONFIG_AT91SAM9N12EK #include "at91sam9n12ek.h" #endif