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Commits on Nov 30, 2015
  1. Makefile: add EXTRAVERSION for linux4sam 5.0

    Nicolas Ferre
    Nicolas Ferre committed Nov 30, 2015
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
  2. Merge branch 'at91-4.1-trunk/dt' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 30, 2015
  3. Merge branch 'at91-4.1-trunk/qspi' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 30, 2015
  4. mtd: atmel-quadspi: add driver for Atmel QSPI controller

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Sep 15, 2015
    This driver add support to the new Atmel QSPI controller embedded into
    sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
    controller.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  5. ARM: at91/dt: remove m25p,num-dummy-cycles old property

    Nicolas Ferre
    Nicolas Ferre committed Nov 27, 2015
    This property is not needed anymore.
    
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Commits on Nov 27, 2015
  1. ARM: at91/dt: disable HW SHA: issue in recent kernels

    Nicolas Ferre
    Nicolas Ferre committed Nov 27, 2015
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
  2. ARM: at91/defconfig: add quadspi support in sama5_defconfig

    Nicolas Ferre
    Nicolas Ferre committed Nov 27, 2015
    Add QSPI driver.
    
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
  3. Documentation: atmel-quadspi: add binding file for Atmel QSPI driver

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Sep 15, 2015
    This patch documents the DT bindings for the driver of the Atmel QSPI
    controller embedded inside sama5d2x SoCs.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
    Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
    Acked-by: Marek Vasut <marex@denx.de>
    Acked-by: Rob Herring <robh@kernel.org>
  4. mtd: m25p80: add support of dual and quad spi protocols to all commands

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Sep 18, 2015
    Before this patch, m25p80_read() supported few SPI protocols:
    - regular SPI 1-1-1
    - SPI Dual Output 1-1-2
    - SPI Quad Output 1-1-4
    On the other hand, all other m25p80_*() hooks only supported SPI 1-1-1.
    
    However once their Quad mode enabled, Micron and Macronix spi-nor memories
    expect all commands to use the SPI 4-4-4 protocol.
    
    Also, once their Dual mode enabled, Micron spi-nor memories expect all
    commands to use the SPI-2-2-2 protocol.
    
    So this patch adds support to all currently existing SPI protocols to
    cover as many protocols as possible.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  5. mtd: spi-nor: fix Quad SPI mode support for Spansion, Micron and Macr…

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Sep 18, 2015
    …onix
    
    This patch reworks the support of Quad and Dual SPI protocols for Micron,
    Spansion and Macronix Quad/Dual capable memories. Indeed, in the best
    case, only Spansion memories are correctly supported by the current
    spi-nor framework.
    
    1 - Micron:
    When their Quad SPI mode is enabled, Micron spi-nor memories expect all
    commands to use the SPI 4-4-4 protocol. Also when the Dual SPI mode is
    enabled, all commands must use the SPI 2-2-2 protocol.
    
    Before this patch, the spi-nor framework used to always enable the Quad
    mode when the mode argument of spi_nor_scan() took the value SPI_NOR_QUAD.
    That was not suited with drivers only supporting SPI 1-x-4 protocols but
    not the 4-4-4 (e.g. the m25p80 driver). Also the SPI controller was not
    notified about which SPI protocol to use to transfert command. We cannot
    rely only on the op code: in Extended SPI mode the 0x6b command must  use
    the SPI 1-1-4 protocol whereas in Quad SPi mode the SPI 4-4-4 protocol
    must be use instead.
    
    After this patch, the spi-nor framework uses the result of the
    spi_nor_read_id() function to choose the right SPI protocol to be used.
    If the reg_proto was set to SPI_PROTO_4_4_4, we already know that the Quad
    SPI mode is already enabled and that the SPI controller supports the SPI
    4-4-4 protocol (otherwise it would have fail to read the JEDEC ID with the
    0xaf op code). For the very same reason, if the reg_proto was set to
    SPI_PROTO_2_2_2, we already know that the Dual mode is already enabled and
    that the SPI controller supports the SPI 2-2-2 protocol.
    Otherwise we switch back to the Extended SPI protocol, which supports at
    least the Fast Read commands:
    - 1-1-1 (0x0b)
    - Dual Output 1-1-2 (0x3b)
    - Quad Output 1-1-4 (0x6b)
    
    We also safely set the number of dummy cycles to 8 for Fast Read commands
    through the Volatile Configuration Register (VCR): some drivers (m25p80)
    or SPI controllers only support a number of dummy cycles multiple of 8.
    This number may have previouly been set to an unsupported value by an
    early bootloader or at reset thanks to the Non-Volatile Configuration
    Register.
    
    Finally the XIP bit is always set in the VCR to disable the Continuous
    Read mode as we don't want to care about mode cycles.
    
    2 - Macronix:
    When the QPI mode is enabled, all commands must use the SPI 4-4-4 protocol
    and only the 0xeb op code is supported for Fast Read commands.
    Before this patch, the spi-nor framework used to force the QPI mode but
    used the 0x6b op code for Fast Read commands when the SPI controller
    claims to support Quad SPI mode.
    This patch uses the result of spi_nor_read_id() to guess whether the QPI
    mode is both enable and supported by the SPI controller (otherwise it
    would have failed to read the JEDEC ID with the 0xaf op code).
    When the QPI mode is disabled, Macronix memories still support the
    following Fast Read commands:
    - 1-1-1 (0x0b)
    - Dual Output 1-1-2 (0x3b)
    - Quad Output 1-1-4 (0x6b)
    So if the QPI mode has not already been enabled, there is not need to
    enable it. We also avoid the 0xbb (Dual I/O 1-2-2) and 0xeb (Quad I/O
    1-4-4) op codes on purpose as we don't want to care about the value to set
    in mode cycles not to enter the Continuous Read (Performance Enhance)
    mode.
    
    As for Micron memories, the spi-nor framework now safely sets the number
    of dummy cycles to 8 thanks to 2 volatile bits inside the Configuration
    Register.
    
    3 - Spansion:
    As for Macronix, we avoid the 0xbb (Dual I/O 1-2-2) and 0xeb (Quad I/O
    1-4-4) op codes on purpose as we don't want to care about the value to set
    in mode cycles not to enter in the Continuous Read mode.
    
    Besides, we only care about the Quad Enable bit inside the Configuration
    Register (CR) when using Quad operations. In such a case, we first check
    its state before trying to set it. Now we also notify the user about the
    update of this non-volatile bit.
    
    We also check the Latency Code (LC) in CR to know the exact number of
    dummy cycles to use when performing a Fast Read operation. Currently only
    the 0x0b, 0x3b and 0x6b op codes are used to perform Fast Read operation
    so the number of dummy cycles is always either 0 or 8. Hence no regression
    should be introduced.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  6. mtd: spi-nor: properly detect the memory when it boots in Quad or Dua…

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Sep 18, 2015
    …l mode
    
    The quad (or dual) mode of a spi-nor memory may be enabled at boot time by
    non-volatile bits in some setting register. Also such a mode may have
    already been enabled at early stage by some boot loader.
    
    Hence, we should not guess the spi-nor memory is always configured for the
    regular SPI 1-1-1 protocol.
    
    Micron and Macronix memories, once their Quad (or dual for Micron) mode
    enabled, no longer process the regular JEDEC Read ID (0x9f) command but
    instead reply to a new command: JEDEC Read ID Multiple I/O (0xaf).
    Besides, in Quad mode both memory manufacturers expect ALL commands to
    use the SPI 4-4-4 protocol. For Micron memories, enabling their Dual mode
    implies to use the SPI 2-2-2 protocol for ALL commands.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Commits on Nov 26, 2015
  1. mtd: spi-nor: remove unused read_xfer/write_xfer hooks

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Sep 18, 2015
    struct spi_nor_xfer_cfg and read_xfer/write_xfer hooks were never used by
    any driver. Do some cleanup by removing them.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  2. Merge branch 'at91-4.1-trunk/sdmmc' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
  3. Merge branch 'at91-4.1-trunk/base_spi' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
  4. spi: atmel: Fix DMA-setup for transfers with more than 8 bits per word

    dmosberger authored and Nicolas Ferre committed Oct 20, 2015
    The DMA-slave configuration depends on the whether <= 8 or > 8 bits
    are transferred per word, so we need to call
    atmel_spi_dma_slave_config() with the correct value.
    
    Signed-off-by: David Mosberger <davidm@egauge.net>
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Cc: stable@vger.kernel.org
  5. spi: atmel: remove warning when !CONFIG_PM_SLEEP

    alexandrebelloni authored and Nicolas Ferre committed Sep 10, 2015
    When CONFIG_PM is defined but not CONFIG_PM_SLEEP (this happens when
    CONFIG_SUSPEND is not defined), there is the following warning:
    
    drivers/spi/spi-atmel.c:1723:12: warning: ‘atmel_spi_suspend’ defined but not used [-Wunused-function]
    drivers/spi/spi-atmel.c:1741:12: warning: ‘atmel_spi_resume’ defined but not used [-Wunused-function]
    
    Enclose both atmel_spi_suspend and atmel_spi_resume in #ifdef
    CONFIG_PM_SLEEP/#endif to solve that.
    
    Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
    Signed-off-by: Mark Brown <broonie@kernel.org>
  6. spi: atmel: update DT bindings documentation

    Cyrille Pitchen Nicolas Ferre
    Cyrille Pitchen authored and Nicolas Ferre committed Jun 16, 2015
    - add new property "atmel,fifo-size"
    - change "cs-gpios" to optional for SPI controller version >= 2.
    
    Please be aware that the VERSION register can not be used to guess the
    size of FIFOs. Indeed, for a given hardware version, the SPI controller
    can be integrated on Atmel SoCs with different FIFO sizes. Also the
    "atmel,fifo-size" property is optional as older SPI controllers don't
    embed FIFO at all.
    
    Besides, the FIFO size can not be read or guessed from other registers:
    When designing the FIFO feature, no dedicated registers were added to
    store this size. Unused spaces in the I/O register range are limited and
    better reserved for future usages. Instead, the FIFO size of each
    peripheral is documented in the programmer datasheet.
    
    Finally, on a given SoC, there can be several instances of the SPI
    controller with different FIFO sizes. This explain why we'd rather use a
    dedicated DT property than use the "compatible" property.
    
    For instance, sama5d2x SoCs come with some SPI controllers, the ones
    inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
    use 16 data FIFOs. All these SPI controllers share the same IP version.
    
    Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
    Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
    Signed-off-by: Mark Brown <broonie@kernel.org>
  7. mmc: sdhci-of-at91: controller is suspended too early

    ldesroches committed Nov 26, 2015
    The controller is suspended before sdhci_add_host(). It causes to read 0
    in register because the controller clock is disabled. Increment the
    usage count before calling sdhci_add_host(), decrement it after and put
    it in suspend if it is possible.
    
    Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
  8. Merge branch 'at91-4.1-trunk/base+4.3' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
  9. Merge branch 'at91-4.1-trunk/dt' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
  10. ARM: at91/dt: sama5d2: classd: add sound card name

    sowu authored and Nicolas Ferre committed Nov 23, 2015
    Add sound card name for samad2-xplained.
    
    Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
    [nicolas.ferre@atmel.com: add name to sama5d2 Xplained pda4 as well]
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
  11. ARM: at91/dt: sama5d2: classd: add GCK's parent clock

    sowu authored and Nicolas Ferre committed Nov 23, 2015
    Set GCK's parent as audio pmc clock.
    
    Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
  12. wireless: regulatory: reduce log level of CRDA related messages

    tpetazzoni authored and Nicolas Ferre committed Jul 9, 2015
    With a basic Linux userspace, the messages "Calling CRDA to update
    world regulatory domain" appears 10 times after boot every second or
    so, followed by a final "Exceeded CRDA call max attempts. Not calling
    CRDA". For those of us not having the corresponding userspace parts,
    having those messages repeatedly displayed at boot time is a bit
    annoying, so this commit reduces their log level to pr_debug().
    
    Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Signed-off-by: Johannes Berg <johannes.berg@intel.com>
  13. mmc: sdhci-of-at91: add presets setup

    ldesroches committed Nov 25, 2015
    The controller claims to support SDR104 but is not totally true since
    the maximum sd clock frequency is 120 MHz instead of 208 MHz for this
    mode. The sdhci core is not aware about this and will compute a wrong
    clock divider so preset has to be used to fix that.
    
    Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
  14. Merge branch 'at91-4.1-trunk/base_dma' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
  15. ARM: at91/defconfig: remove KEXEC from defconfig

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
    This option is not frequently used and easy to add by whoever needs it.
    
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
  16. ARM: at91/sama5_defconfig: enable CPU idle

    wenyouya authored and Nicolas Ferre committed Nov 26, 2015
    Add CONFIG_CPU_IDLE=y to enable CPU idle PM support.
    
    Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
  17. Merge branch 'at91-4.1-trunk/defconfig' into linux-4.1-at91

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
    Conflicts:
    	arch/arm/configs/sama5d2_defconfig
  18. ARM: at91/defconfig: remove the special sama5d2_defconfig

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
    This SoC is now handled normally by the generic sama5_defconfig, no need to
    keep a special defconfig.
    
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
  19. ARM: at91/defconfig: add the HID_GENERIC to sama5_defconfig

    Nicolas Ferre
    Nicolas Ferre committed Nov 26, 2015
    This option can be handy for connecting an USB mouse of keyboard.
    
    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Commits on Nov 24, 2015
  1. Revert "mmc: sdhci at91: add suspend/resume"

    ldesroches committed Nov 24, 2015
    This reverts commit 9072c49.