{
    "csr_bases": {
        "ctrl": 301989888,
        "ddrphy": 301991936,
        "ethmac": 301993984,
        "ethphy": 301996032,
        "identifier_mem": 301998080,
        "leds": 302000128,
        "sdblock2mem": 302002176,
        "sdcore": 302004224,
        "sdirq": 302006272,
        "sdmem2block": 302008320,
        "sdphy": 302010368,
        "sdram": 302012416,
        "timer0": 302014464,
        "uart": 302016512
    },
    "csr_registers": {
        "ctrl_reset": {
            "addr": 301989888,
            "size": 1,
            "type": "rw"
        },
        "ctrl_scratch": {
            "addr": 301989892,
            "size": 1,
            "type": "rw"
        },
        "ctrl_bus_errors": {
            "addr": 301989896,
            "size": 1,
            "type": "ro"
        },
        "ddrphy_rst": {
            "addr": 301991936,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_dly_sel": {
            "addr": 301991940,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_half_sys8x_taps": {
            "addr": 301991944,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_wlevel_en": {
            "addr": 301991948,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_wlevel_strobe": {
            "addr": 301991952,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_rdly_dq_rst": {
            "addr": 301991956,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_rdly_dq_inc": {
            "addr": 301991960,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_rdly_dq_bitslip_rst": {
            "addr": 301991964,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_rdly_dq_bitslip": {
            "addr": 301991968,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_wdly_dq_bitslip_rst": {
            "addr": 301991972,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_wdly_dq_bitslip": {
            "addr": 301991976,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_rdphase": {
            "addr": 301991980,
            "size": 1,
            "type": "rw"
        },
        "ddrphy_wrphase": {
            "addr": 301991984,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_writer_slot": {
            "addr": 301993984,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_writer_length": {
            "addr": 301993988,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_writer_errors": {
            "addr": 301993992,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_writer_ev_status": {
            "addr": 301993996,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_writer_ev_pending": {
            "addr": 301994000,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_writer_ev_enable": {
            "addr": 301994004,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_reader_start": {
            "addr": 301994008,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_reader_ready": {
            "addr": 301994012,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_reader_level": {
            "addr": 301994016,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_reader_slot": {
            "addr": 301994020,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_reader_length": {
            "addr": 301994024,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_reader_ev_status": {
            "addr": 301994028,
            "size": 1,
            "type": "ro"
        },
        "ethmac_sram_reader_ev_pending": {
            "addr": 301994032,
            "size": 1,
            "type": "rw"
        },
        "ethmac_sram_reader_ev_enable": {
            "addr": 301994036,
            "size": 1,
            "type": "rw"
        },
        "ethmac_preamble_crc": {
            "addr": 301994040,
            "size": 1,
            "type": "ro"
        },
        "ethmac_rx_datapath_preamble_errors": {
            "addr": 301994044,
            "size": 1,
            "type": "ro"
        },
        "ethmac_rx_datapath_crc_errors": {
            "addr": 301994048,
            "size": 1,
            "type": "ro"
        },
        "ethphy_crg_reset": {
            "addr": 301996032,
            "size": 1,
            "type": "rw"
        },
        "ethphy_mdio_w": {
            "addr": 301996036,
            "size": 1,
            "type": "rw"
        },
        "ethphy_mdio_r": {
            "addr": 301996040,
            "size": 1,
            "type": "ro"
        },
        "leds_out": {
            "addr": 302000128,
            "size": 1,
            "type": "rw"
        },
        "sdblock2mem_dma_base": {
            "addr": 302002176,
            "size": 2,
            "type": "rw"
        },
        "sdblock2mem_dma_length": {
            "addr": 302002184,
            "size": 1,
            "type": "rw"
        },
        "sdblock2mem_dma_enable": {
            "addr": 302002188,
            "size": 1,
            "type": "rw"
        },
        "sdblock2mem_dma_done": {
            "addr": 302002192,
            "size": 1,
            "type": "ro"
        },
        "sdblock2mem_dma_loop": {
            "addr": 302002196,
            "size": 1,
            "type": "rw"
        },
        "sdblock2mem_dma_offset": {
            "addr": 302002200,
            "size": 1,
            "type": "ro"
        },
        "sdcore_cmd_argument": {
            "addr": 302004224,
            "size": 1,
            "type": "rw"
        },
        "sdcore_cmd_command": {
            "addr": 302004228,
            "size": 1,
            "type": "rw"
        },
        "sdcore_cmd_send": {
            "addr": 302004232,
            "size": 1,
            "type": "rw"
        },
        "sdcore_cmd_response": {
            "addr": 302004236,
            "size": 4,
            "type": "ro"
        },
        "sdcore_cmd_event": {
            "addr": 302004252,
            "size": 1,
            "type": "ro"
        },
        "sdcore_data_event": {
            "addr": 302004256,
            "size": 1,
            "type": "ro"
        },
        "sdcore_block_length": {
            "addr": 302004260,
            "size": 1,
            "type": "rw"
        },
        "sdcore_block_count": {
            "addr": 302004264,
            "size": 1,
            "type": "rw"
        },
        "sdirq_status": {
            "addr": 302006272,
            "size": 1,
            "type": "ro"
        },
        "sdirq_pending": {
            "addr": 302006276,
            "size": 1,
            "type": "rw"
        },
        "sdirq_enable": {
            "addr": 302006280,
            "size": 1,
            "type": "rw"
        },
        "sdmem2block_dma_base": {
            "addr": 302008320,
            "size": 2,
            "type": "rw"
        },
        "sdmem2block_dma_length": {
            "addr": 302008328,
            "size": 1,
            "type": "rw"
        },
        "sdmem2block_dma_enable": {
            "addr": 302008332,
            "size": 1,
            "type": "rw"
        },
        "sdmem2block_dma_done": {
            "addr": 302008336,
            "size": 1,
            "type": "ro"
        },
        "sdmem2block_dma_loop": {
            "addr": 302008340,
            "size": 1,
            "type": "rw"
        },
        "sdmem2block_dma_offset": {
            "addr": 302008344,
            "size": 1,
            "type": "ro"
        },
        "sdphy_card_detect": {
            "addr": 302010368,
            "size": 1,
            "type": "ro"
        },
        "sdphy_clocker_divider": {
            "addr": 302010372,
            "size": 1,
            "type": "rw"
        },
        "sdphy_init_initialize": {
            "addr": 302010376,
            "size": 1,
            "type": "rw"
        },
        "sdphy_dataw_status": {
            "addr": 302010380,
            "size": 1,
            "type": "ro"
        },
        "sdram_dfii_control": {
            "addr": 302012416,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi0_command": {
            "addr": 302012420,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi0_command_issue": {
            "addr": 302012424,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi0_address": {
            "addr": 302012428,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi0_baddress": {
            "addr": 302012432,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi0_wrdata": {
            "addr": 302012436,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi0_rddata": {
            "addr": 302012440,
            "size": 1,
            "type": "ro"
        },
        "sdram_dfii_pi1_command": {
            "addr": 302012444,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi1_command_issue": {
            "addr": 302012448,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi1_address": {
            "addr": 302012452,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi1_baddress": {
            "addr": 302012456,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi1_wrdata": {
            "addr": 302012460,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi1_rddata": {
            "addr": 302012464,
            "size": 1,
            "type": "ro"
        },
        "sdram_dfii_pi2_command": {
            "addr": 302012468,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi2_command_issue": {
            "addr": 302012472,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi2_address": {
            "addr": 302012476,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi2_baddress": {
            "addr": 302012480,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi2_wrdata": {
            "addr": 302012484,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi2_rddata": {
            "addr": 302012488,
            "size": 1,
            "type": "ro"
        },
        "sdram_dfii_pi3_command": {
            "addr": 302012492,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi3_command_issue": {
            "addr": 302012496,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi3_address": {
            "addr": 302012500,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi3_baddress": {
            "addr": 302012504,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi3_wrdata": {
            "addr": 302012508,
            "size": 1,
            "type": "rw"
        },
        "sdram_dfii_pi3_rddata": {
            "addr": 302012512,
            "size": 1,
            "type": "ro"
        },
        "timer0_load": {
            "addr": 302014464,
            "size": 1,
            "type": "rw"
        },
        "timer0_reload": {
            "addr": 302014468,
            "size": 1,
            "type": "rw"
        },
        "timer0_en": {
            "addr": 302014472,
            "size": 1,
            "type": "rw"
        },
        "timer0_update_value": {
            "addr": 302014476,
            "size": 1,
            "type": "rw"
        },
        "timer0_value": {
            "addr": 302014480,
            "size": 1,
            "type": "ro"
        },
        "timer0_ev_status": {
            "addr": 302014484,
            "size": 1,
            "type": "ro"
        },
        "timer0_ev_pending": {
            "addr": 302014488,
            "size": 1,
            "type": "rw"
        },
        "timer0_ev_enable": {
            "addr": 302014492,
            "size": 1,
            "type": "rw"
        },
        "uart_rxtx": {
            "addr": 302016512,
            "size": 1,
            "type": "rw"
        },
        "uart_txfull": {
            "addr": 302016516,
            "size": 1,
            "type": "ro"
        },
        "uart_rxempty": {
            "addr": 302016520,
            "size": 1,
            "type": "ro"
        },
        "uart_ev_status": {
            "addr": 302016524,
            "size": 1,
            "type": "ro"
        },
        "uart_ev_pending": {
            "addr": 302016528,
            "size": 1,
            "type": "rw"
        },
        "uart_ev_enable": {
            "addr": 302016532,
            "size": 1,
            "type": "rw"
        },
        "uart_txempty": {
            "addr": 302016536,
            "size": 1,
            "type": "ro"
        },
        "uart_rxfull": {
            "addr": 302016540,
            "size": 1,
            "type": "ro"
        }
    },
    "constants": {
        "config_clock_frequency": 50000000,
        "config_cpu_has_interrupt": null,
        "config_cpu_reset_addr": 268435456,
        "config_cpu_count": 1,
        "config_cpu_isa": "rv64imac",
        "config_cpu_mmu": "sv39",
        "config_cpu_dcache_size": 4096,
        "config_cpu_dcache_ways": 2,
        "config_cpu_dcache_block_size": 64,
        "config_cpu_icache_size": 4096,
        "config_cpu_icache_ways": 2,
        "config_cpu_icache_block_size": 64,
        "config_cpu_dtlb_size": 4,
        "config_cpu_dtlb_ways": 1,
        "config_cpu_itlb_size": 4,
        "config_cpu_itlb_ways": 1,
        "config_cpu_type_rocket": null,
        "config_cpu_variant_linuxd": null,
        "config_cpu_human_name": "rocketrv64[imac]",
        "config_cpu_nop": "nop",
        "config_csr_data_width": 32,
        "config_csr_alignment": 32,
        "config_bus_standard": "wishbone",
        "config_bus_data_width": 32,
        "config_bus_address_width": 32,
        "config_bus_bursting": 0,
        "config_cpu_has_dma_bus": null,
        "ethmac_rx_slots": 2,
        "ethmac_tx_slots": 2,
        "ethmac_slot_size": 2048,
        "ethmac_interrupt": 2,
        "sdirq_interrupt": 3,
        "timer0_interrupt": 1,
        "uart_interrupt": 0
    },
    "memories": {
        "opensbi": {
            "base": 2147483648,
            "size": 2097152,
            "type": "io+linker"
        },
        "plic": {
            "base": 201326592,
            "size": 4194304,
            "type": "cached+linker"
        },
        "clint": {
            "base": 33554432,
            "size": 65536,
            "type": "cached+linker"
        },
        "rom": {
            "base": 268435456,
            "size": 131072,
            "type": "cached"
        },
        "sram": {
            "base": 285212672,
            "size": 8192,
            "type": "cached"
        },
        "main_ram": {
            "base": 2147483648,
            "size": 536870912,
            "type": "cached"
        },
        "ethmac": {
            "base": 805306368,
            "size": 8192,
            "type": "io"
        },
        "csr": {
            "base": 301989888,
            "size": 65536,
            "type": "io"
        }
    }
}