#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD

# IOs ----------------------------------------------------------------------------------------------

_io = [
    # Clk / Rst
    ("sys_clk",    0, Pins("M22"), IOStandard("LVCMOS33")),
    ("sys_reset",  0, Pins("J8"),  IOStandard("LVCMOS33")),

    # Leds
    ("user_led",   0, Pins("J6"),   IOStandard("LVCMOS33")),
    ("user_led",   1, Pins("H6"),   IOStandard("LVCMOS33")),
    #("fpga_done",  2, Pins("W10"),  IOStandard("LVCMOS33")),

    # Buttons
    ("key0",   0, Pins("H7"),   IOStandard("LVCMOS33")),
    #("key1",   1, Pins("J8"),   IOStandard("LVCMOS33")),
    #("prog_b", 2, Pins("AE16"), IOStandard("LVCMOS33")),

    # Serial
    ("serial", 0,
        Subsignal("tx", Pins("E3")),
        Subsignal("rx", Pins("F3")),
        IOStandard("LVCMOS33"),
    ),

    # SPIFlash
    ("spiflash", 0,
        Subsignal("cs_n", Pins("P18")),
        Subsignal("clk",  Pins("H13")),
        Subsignal("mosi", Pins("R14")),
        Subsignal("miso", Pins("R15")),
        Subsignal("wp",   Pins("P14")),
        Subsignal("hold", Pins("N14")),
        IOStandard("LVCMOS33"),
    ),
    
    ("spiflash4x", 0,
        Subsignal("cs_n", Pins("P18")),
        Subsignal("clk",  Pins("H13")),
        Subsignal("dq",   Pins("R14", "R15", "P14", "N14")),
        IOStandard("LVCMOS33")
    ),

    # DDR3 SDRAM
    ("ddram", 0,
        Subsignal("a", Pins(
            "E17 G17 F17 C17 G16 D16 H16 E16",
            "H14 F15 F20 H15 C18 G15"),
            IOStandard("SSTL135")),
        Subsignal("ba",    Pins("B17 D18 A17"), IOStandard("SSTL135")),
        Subsignal("ras_n", Pins("A19"), IOStandard("SSTL135")),
        Subsignal("cas_n", Pins("B19"), IOStandard("SSTL135")),
        Subsignal("we_n",  Pins("A18"), IOStandard("SSTL135")),
        Subsignal("cs_n",  Pins("E22"), IOStandard("SSTL135")),
        Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL135")),
        Subsignal("dq", Pins(
            "D21 C21 B22 B21 D19 E20 C19 D20",
            "C23 D23 B24 B25 C24 C26 A25 B26"),
            IOStandard("SSTL135"),
            Misc("IN_TERM=UNTUNED_SPLIT_40")),
        Subsignal("dqs_p", Pins("B20 A23"),
            IOStandard("DIFF_SSTL135"),
            Misc("IN_TERM=UNTUNED_SPLIT_40")),
        Subsignal("dqs_n", Pins("A20 A24"),
            IOStandard("DIFF_SSTL135"),
            Misc("IN_TERM=UNTUNED_SPLIT_40")),
        Subsignal("clk_p", Pins("F18"), IOStandard("DIFF_SSTL135")),
        Subsignal("clk_n", Pins("F19"), IOStandard("DIFF_SSTL135")),
        Subsignal("cke",   Pins("E18"), IOStandard("SSTL135")),
        Subsignal("odt",   Pins("G19"), IOStandard("SSTL135")),
        Subsignal("reset_n", Pins("H17"), IOStandard("SSTL135")),
        Misc("SLEW=FAST"),
    ),

    # MII Ethernet
    ("eth_ref_clk", 0, Pins("U1"), IOStandard("LVCMOS33")),
    ("eth_clocks", 0,
        Subsignal("tx", Pins("M2")),
        Subsignal("rx", Pins("P4")),
        IOStandard("LVCMOS33"),
    ),
    ("eth", 0,
        Subsignal("rst_n",   Pins("R1")),
        Subsignal("mdio",    Pins("H1")),
        Subsignal("mdc",     Pins("H2")),
        Subsignal("rx_dv",   Pins("L3")),
        Subsignal("rx_er",   Pins("U5")),
        Subsignal("rx_data", Pins("M4 N3 N4 P3")),
        Subsignal("tx_en",   Pins("T2")),
        Subsignal("tx_data", Pins("R2 P1 N2 N1")),
        Subsignal("col",     Pins("U4")),
        Subsignal("crs",     Pins("U2")),
        IOStandard("LVCMOS33"),
    ),
]

#        Subsignal("tx_data", Pins("R2 P1 N2 N1 M1 L2 K2 K1")),

'''
def usb_pmod_io(pmod):
    return [
        # USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
        ("usb_uart", 0,
            Subsignal("tx", Pins(f"{pmod}:1")),
            Subsignal("rx", Pins(f"{pmod}:2")),
            IOStandard("LVCMOS33")
        ),
    ]
_usb_uart_pmod_io = usb_pmod_io("pmodb") # USB-UART PMOD on JB.
'''

# Platform -----------------------------------------------------------------------------------------

class Platform(XilinxPlatform):
    default_clk_name   = "sys_clk"
    default_clk_period = 1e9/100e6

    def __init__(self):
        XilinxPlatform.__init__(self, "xc7a100t-2fgg676", _io, toolchain="vivado")
        self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
        self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
        self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
        self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk_1]")
        self.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks UCIO-1]")

    def create_programmer(self):
        return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a100t.bit")

    def do_finalize(self, fragment):
        XilinxPlatform.do_finalize(self, fragment)
        self.add_period_constraint(self.lookup_request("sys_clk", loose=True), 1e9/100e6)