SpinalHDL git repository not detected #390
Comments
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Hi, |
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Which exact directory needs to be cloned using the --recursive argument? |
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I assume it's this one? --> https://github.com/litex-hub/pythondata-cpu-vexriscv_smp/tree/master Update: git submodule update --recursive --remoteon the pythondata-cpu-vexriscv-smp directory but I'm prompted with the same error as above regarding the same directory/repo. |
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Hmm this is weird |
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I cloned https://github.com/SpinalHDL/SpinalHDL/tree/002ffd50bca59e0f8b9c74b0d00cac86d8379810 and got a different hash than the one above. Should I just manually clone it where the incorrect hash is? |
Yes, you realy need to have the correct git commit hash |
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Just out of curiosity, the path specified in the error is here: fatal: not a git repository: /home/jason/.sbt/1.0/staging/7a0d3e6968cc5c46ea70/spinalhdl/../../../../.git/modules/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDLwhich would be the same path as... /home/jason/.sbt/.git/modules/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDLThis path does not exist. Is this the path I need to reclone to repository for SpinalHDL (/LiteX holds all the files for this project)? /home/jason/Desktop/LiteX/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL |
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that is realy weird XD Can you try to : cd /home/jason/Desktop/LiteX
rm -rf pythondata-cpu-vexriscv-smp
git clone https://github.com/litex-hub/pythondata-cpu-vexriscv_smp.git --recursiveAnd then retry the generation ? Just to be sure we are in sync |
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I ran everything as you said, and it's still throwing the same error with the exact same path. jason@jason-VirtualBox:~/Desktop/LiteX$ git clone https://github.com/litex-hub/pythondata-cpu-vexriscv_smp.git --recursive
Cloning into 'pythondata-cpu-vexriscv_smp'...
remote: Enumerating objects: 348, done.
remote: Counting objects: 100% (259/259), done.
remote: Compressing objects: 100% (50/50), done.
remote: Total 348 (delta 225), reused 234 (delta 208), pack-reused 89
Receiving objects: 100% (348/348), 4.54 MiB | 1.75 MiB/s, done.
Resolving deltas: 100% (230/230), done.
Submodule 'pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL' (https://github.com/SpinalHDL/SpinalHDL.git) registered for path 'pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL'
Submodule 'pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv' (https://github.com/SpinalHDL/VexRiscv.git) registered for path 'pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv'
Cloning into '/home/jason/Desktop/LiteX/pythondata-cpu-vexriscv_smp/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL'...
remote: Enumerating objects: 109411, done.
remote: Counting objects: 100% (8574/8574), done.
remote: Compressing objects: 100% (4116/4116), done.
remote: Total 109411 (delta 5124), reused 6559 (delta 3289), pack-reused 100837
Receiving objects: 100% (109411/109411), 66.36 MiB | 1.83 MiB/s, done.
Resolving deltas: 100% (52711/52711), done.
Cloning into '/home/jason/Desktop/LiteX/pythondata-cpu-vexriscv_smp/pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv'...
remote: Enumerating objects: 16588, done.
remote: Counting objects: 100% (4444/4444), done.
remote: Compressing objects: 100% (1073/1073), done.
remote: Total 16588 (delta 3509), reused 4088 (delta 3348), pack-reused 12144
Receiving objects: 100% (16588/16588), 13.06 MiB | 1.72 MiB/s, done.
Resolving deltas: 100% (9973/9973), done.
Submodule path 'pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL': checked out '002ffd50bca59e0f8b9c74b0d00cac86d8379810'
Submodule 'tester/src/test/python/cocotblib' (https://github.com/SpinalHDL/CocotbLib.git) registered for path 'pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL/tester/src/test/python/cocotblib'
Cloning into '/home/jason/Desktop/LiteX/pythondata-cpu-vexriscv_smp/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL/tester/src/test/python/cocotblib'...
remote: Enumerating objects: 124, done.
remote: Counting objects: 100% (56/56), done.
remote: Compressing objects: 100% (13/13), done.
remote: Total 124 (delta 45), reused 43 (delta 43), pack-reused 68
Receiving objects: 100% (124/124), 30.72 KiB | 241.00 KiB/s, done.
Resolving deltas: 100% (68/68), done.
Submodule path 'pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL/tester/src/test/python/cocotblib': checked out 'a98830423924fc89bfebae84cb802fc90d352602'
Submodule path 'pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv': checked out '625fc8437952ca00d474f0547faef72cbe68a32c'
Submodule 'src/test/resources/VexRiscvRegressionData' (https://github.com/SpinalHDL/VexRiscvRegressionData.git) registered for path 'pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv/src/test/resources/VexRiscvRegressionData'
Cloning into '/home/jason/Desktop/LiteX/pythondata-cpu-vexriscv_smp/pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv/src/test/resources/VexRiscvRegressionData'...
remote: Enumerating objects: 78, done.
remote: Total 78 (delta 0), reused 0 (delta 0), pack-reused 78
Receiving objects: 100% (78/78), 10.88 MiB | 1.76 MiB/s, done.
Resolving deltas: 100% (2/2), done.
Submodule path 'pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv/src/test/resources/VexRiscvRegressionData': checked out '539398c1481203a51115b5f1228ea961f0ac9bd3'Above is the output when cloning the repo, in-case there is anything interesting that might help you find the issue. |
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Thanks I think your install of litex isn't done via the https://github.com/enjoy-digital/litex?tab=readme-ov-file#quick-start-guide, as i can now see your : How did you installed litex ? |
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I just followed here, https://github.com/litex-hub/linux-on-litex-vexriscv/?tab=readme-ov-file#-installing-litex, but I'll follow the link you just sent and see if that addresses the issue |
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https://github.com/litex-hub/linux-on-litex-vexriscv/?tab=readme-ov-file#-installing-litex is good aswell. Hmmm and in which directory did you run that installation script ? |
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I'm running the ./litex_setup.py in ./Litex/linux-on-litex-vexriscv |
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I followed the other link you sent, but I didn't get a BIOS prompt like the instructions indicated... root@jason-VirtualBox:/home/jason/Desktop/LiteX/linux-on-litex-vexriscv# litex_sim --cpu-type=vexriscv
/usr/local/lib/python3.12/dist-packages/litescope-0.0.0-py3.12.egg/litescope/software/dump/sigrok.py:112: SyntaxWarning: invalid escape sequence '\w'
/usr/local/lib/python3.12/dist-packages/litescope-0.0.0-py3.12.egg/litescope/software/dump/sigrok.py:112: SyntaxWarning: invalid escape sequence '\w'
/usr/local/lib/python3.12/dist-packages/litescope-0.0.0-py3.12.egg/litescope/software/dump/vcd.py:33: SyntaxWarning: invalid escape sequence '\d'
/usr/local/lib/python3.12/dist-packages/litescope-0.0.0-py3.12.egg/litescope/software/dump/vcd.py:33: SyntaxWarning: invalid escape sequence '\d'
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-06-10 09:00:30)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-06-10 09:00:30)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 3).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 2.
INFO:SoCCSRHandler:uart CSR allocated at Location 3.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False, Linker: False
Bus Regions: (3)
rom : Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True, Linker: False
sram : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False
csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (4)
- ctrl : 0
- identifier_mem : 1
- timer0 : 2
- uart : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
SimSoC
└─── crg (CRG)
└─── bus (SoCBusHandler)
│ └─── _interconnect (InterconnectShared)
│ │ └─── arbiter (Arbiter)
│ │ │ └─── rr (RoundRobin)
│ │ └─── decoder (Decoder)
│ │ └─── timeout (Timeout)
│ │ │ └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscv)
│ └─── [VexRiscv]
└─── rom (SRAM)
└─── sram (SRAM)
└─── identifier (Identifier)
└─── uart_phy (RS232PHYModel)
└─── uart (UART)
│ └─── ev (EventManager)
│ │ └─── eventsourceprocess_0* (EventSourceProcess)
│ │ └─── eventsourceprocess_1* (EventSourceProcess)
│ └─── tx_fifo (SyncFIFO)
│ │ └─── fifo (SyncFIFOBuffered)
│ │ │ └─── fifo (SyncFIFO)
│ └─── rx_fifo (SyncFIFO)
│ │ └─── fifo (SyncFIFOBuffered)
│ │ │ └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│ └─── ev (EventManager)
│ │ └─── eventsourceprocess_0* (EventSourceProcess)
└─── csr_bridge (Wishbone2CSR)
│ └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│ └─── csrbank_0* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ └─── sram_0* (SRAM)
│ └─── csrbank_1* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstorage_4* (CSRStorage)
│ └─── csrbank_2* (CSRBank)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstatus_3* (CSRStatus)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstatus_4* (CSRStatus)
│ │ └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.
INFO:SoC:--------------------------------------------------------------------------------
Traceback (most recent call last):
File "/usr/local/bin/litex_sim", line 33, in <module>
sys.exit(load_entry_point('litex==2023.12', 'console_scripts', 'litex_sim')())
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.12/dist-packages/litex-2023.12-py3.12.egg/litex/tools/litex_sim.py", line 560, in main
builder.build(
File "/usr/local/lib/python3.12/dist-packages/litex-2023.12-py3.12.egg/litex/soc/integration/builder.py", line 375, in build
self._generate_includes(with_bios=with_bios)
File "/usr/local/lib/python3.12/dist-packages/litex-2023.12-py3.12.egg/litex/soc/integration/builder.py", line 220, in _generate_includes
variables_contents = self._get_variables_contents()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.12/dist-packages/litex-2023.12-py3.12.egg/litex/soc/integration/builder.py", line 188, in _get_variables_contents
picolibc_directory = get_data_mod("software", "picolibc").data_location
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.12/dist-packages/litex-2023.12-py3.12.egg/litex/__init__.py", line 16, in get_data_mod
raise ImportError("""\
ImportError: pythondata-software-picolibc module not installed! Unable to use picolibc software.
No module named 'pythondata_software_picolibc'
You can install this by running;
pip3 install git+https://github.com/litex-hub/pythondata-software-picolibc.git
I'm not sure if a clean install would do the trick at this point? |
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hmm, it seems that you may have a broken litex intall. |
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I just ran $ ./litex_sim.py --init --install --user
$ ./litex_sim.py --updateAnd seemed to fix everything. Thank you again! |
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Running
and I'm currently getting this error:
I'm aware that it says that the given directory does not exist, however, when I run the following, it says the HEAD is detached:
jason@jason-VirtualBox:~/Desktop/LiteX/pythondata-cpu-vexriscv-smp/.git/modules/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL$ git status HEAD detached at 002ffd50b nothing to commit, working tree cleanWould it be safe to just manually clone the SpinalHDL git repository, or is there a proper way to ensure that this can detect it as the proper git repository?
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