# This file is Copyright (c) 2015 Yann Sionneau # This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ ("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")), # ("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")), ("user_btn", 0, Pins("J8"), IOStandard("LVCMOS33")), ("clk50", 0, Pins("M22"), IOStandard("LVCMOS33")), ("cpu_reset", 0, Pins("H7"), IOStandard("LVCMOS33")), #estaba en 33 ("serial", 0, Subsignal("tx", Pins("E3")), Subsignal("rx", Pins("F3")), IOStandard("LVCMOS33") ), ("spiflash4x", 0, Subsignal("cs_n", Pins("P18")), Subsignal("clk", Pins("H13")), Subsignal("dq", Pins("R14", "R15", "P14", "N14")), IOStandard("LVCMOS33") ), ("ddram", 0, Subsignal("a", Pins( "E17 G17 F17 C17 G16 D16 H16 E16", "H14 F15 F20 H15 C18 G15"), IOStandard("SSTL135")), Subsignal("ba", Pins("B17 D18 A17"), IOStandard("SSTL135")), Subsignal("ras_n", Pins("A19"), IOStandard("SSTL135")), Subsignal("cas_n", Pins("B19"), IOStandard("SSTL135")), Subsignal("we_n", Pins("A18"), IOStandard("SSTL135")), Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL135")), Subsignal("dq", Pins( "D21 C21 B22 B21 D19 E20 C19 D20", "C23 D23 B24 B25 C24 C26 A25 B26"), IOStandard("SSTL135"), Misc("IN_TERM=UNTUNED_SPLIT_40")), Subsignal("dqs_p", Pins("B20 A23"), IOStandard("DIFF_SSTL135")), #, Misc("IN_TERM=UNTUNED_SPLIT_40") Subsignal("dqs_n", Pins("A20 A24"), IOStandard("DIFF_SSTL135")), #, Misc("IN_TERM=UNTUNED_SPLIT_40") Subsignal("clk_p", Pins("F18"), IOStandard("DIFF_SSTL135")), Subsignal("clk_n", Pins("F19"), IOStandard("DIFF_SSTL135")), Subsignal("cke", Pins("E18"), IOStandard("SSTL135")), Subsignal("odt", Pins("G19"), IOStandard("SSTL135")), Subsignal("reset_n", Pins("H17"), IOStandard("SSTL135")), Misc("SLEW=FAST"), ), ("eth_clocks", 0, Subsignal("tx", Pins("M2")), Subsignal("rx", Pins("P4")), Subsignal("gtx", Pins("U1")), IOStandard("LVCMOS25") ), ("eth", 0, Subsignal("rst_n", Pins("R1")), #Signal to ground # Subsignal("int_n", Pins("L16")), #Signal to 3.3V Subsignal("mdio", Pins("H1")), Subsignal("mdc", Pins("H2")), Subsignal("rx_dv", Pins("L3")), Subsignal("rx_er", Pins("U5")), Subsignal("rx_data", Pins("M4 N3 N4 P3 R3 T3 T4 T5")), Subsignal("tx_en", Pins("T2")), Subsignal("tx_er", Pins("J1")), Subsignal("tx_data", Pins("R2 P1 N2 N1 M1 L2 K2 K1")), Subsignal("col", Pins("U4")), # col/mod:0 Subsignal("crs", Pins("U2")), IOStandard("LVCMOS25") ), # PMOD A ("pmoda", 0, Pins("H4 F4 A4 A5 J4 G4 B4 B5"), IOStandard("LVCMOS33")), # PMOD B ("pmodb", 0, Pins("D5 G5 G7 G8 E5 E6 D6 G6"), IOStandard("LVCMOS33")), #SPI SD CARD ("spisdcard", 0, Subsignal("clk", Pins("G7")), Subsignal("cs_n", Pins("D5")), Subsignal("mosi", Pins("G5")), Subsignal("miso", Pins("G8")), IOStandard("LVCMOS33") ), # HDMI out ("hdmi_out", 0, Subsignal("clk_p", Pins("D4"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("C4"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("E1"), IOStandard("TMDS_33")), Subsignal("data0_n", Pins("D1"), IOStandard("TMDS_33")), Subsignal("data1_p", Pins("F2"), IOStandard("TMDS_33")), Subsignal("data1_n", Pins("E2"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("G2"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("G1"), IOStandard("TMDS_33")), Subsignal("scl", Pins("B2"), IOStandard("LVCMOS33")), Subsignal("sda", Pins("A2"), IOStandard("LVCMOS33")), Subsignal("hdp", Pins("A3"), IOStandard("LVCMOS33")), Subsignal("cec", Pins("B1"), IOStandard("LVCMOS33")), # FIXME # Subsignal("txen", Pins(""), IOStandard("LVCMOS33")), # FIXME ), ] # Connectors --------------------------------------------------------------------------------------- _connectors = [ ("pmoda", "H4 F4 A4 A5 J4 G4 B4 B5"), ("pmodb", "D5 G5 G7 G8 E5 E6 D6 G6"), # ("LPC", { # } # ) ] # PMODS -------------------------------------------------------------------------------------------- def sdcard_pmod_io(pmod): return [ # SDCard PMOD: # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/ # Over J10 connector # SIGNAL - CONN/PIN # 3.3V - 12/3.3V # GND - 5/GND # MISO - 4/G8 # CLK - 3/G7 # MOSI - 2/G5 # CS - 1/D5 ("spisdcard", 0, Subsignal("clk", Pins(f"{pmod}:2")), Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")), Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")), Subsignal("miso", Pins(f"{pmod}:3"), Misc("PULLUP True")), Misc("SLEW=FAST"), IOStandard("LVCMOS33"), ), ] _sdcard_pmod_io = sdcard_pmod_io("pmodb") # SDCARD PMOD on JD. # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 def __init__(self): XilinxPlatform.__init__(self, "xc7a100tfgg676-2", _io, toolchain="vivado") self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] # self.toolchain.additional_commands = \ # ["write_cfgmem -force -format bin -interface spix4 -size 16 " # "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] # self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]") self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50]") def create_programmer(self): # bscan_spi = "bscan_spi_xc7a100t.bit" # return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) # return OpenOCD("openocd_nexys_video.cfg", "QMTECH.bit") return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) # self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/25e6)