__ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Dec 25 2020 09:18:04 BIOS CRC passed (5171d98e) Migen git sha1: d42aa6f LiteX git sha1: bddb1706 --=============== SoC ==================-- CPU: VexRiscv SMP-LINUX @ 150MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 8-bit data ROM: 64KiB SRAM: 8KiB L2: 0KiB SDRAM: 262144KiB 16-bit @ 1200MT/s (CL-10 CWL-7) --========== Initialization ============-- Ethernet init... Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write latency calibration: m0:0 m1:0 Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |01111111111111110000000000000000| delays: 09+-07 m0, b2: |00000000000000000011111111111110| delays: 24+-06 m0, b3: |00000000000000000000000000000000| delays: - m0, b4: |00000000000000000000000000000000| delays: - m0, b5: |00000000000000000000000000000000| delays: - m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b01 delays: 09+-07 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00111111111111100000000000000000| delays: 08+-06 m1, b2: |00000000000000000011111111111110| delays: 24+-06 m1, b3: |00000000000000000000000000000000| delays: - m1, b4: |00000000000000000000000000000000| delays: - m1, b5: |00000000000000000000000000000000| delays: - m1, b6: |00000000000000000000000000000000| delays: - m1, b7: |00000000000000000000000000000000| delays: - best: m1, b01 delays: 08+-06 Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 47MiB/s, 381Mbps Read speed: 39MiB/s, 312Mbps --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro [LXTERM] Received firmware download request from the device. [LXTERM] Uploading ./Image to 0x40000000 (7287696 bytes)... [LXTERM] Upload complete (248.2KB/s). [LXTERM] Uploading ./rv32.dtb to 0x40ef0000 (2485 bytes)... [LXTERM] Upload complete (229.5KB/s). [LXTERM] Uploading ./rootfs.cpio to 0x41000000 (5639680 bytes)... [LXTERM] Upload complete (247.5KB/s). [LXTERM] Uploading ./opensbi.bin to 0x40f00000 (53640 bytes)... [LXTERM] Upload complete (247.6KB/s). [LXTERM] Booting the device. [LXTERM] Done. Executing booted program at 0x40f00000 --============= Liftoff! ===============-- OpenSBI v0.8-1-gecf7701 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : LiteX / VexRiscv-SMP Platform Features : timer,mfdeleg Platform HART Count : 8 Boot HART ID : 0 Boot HART ISA : rv32imas BOOT HART Features : time BOOT HART PMP Count : 0 Firmware Base : 0x40f00000 Firmware Size : 124 KB Runtime SBI Version : 0.2 MIDELEG : 0x00000222 MEDELEG : 0x0000b101 [ 0.000000] Linux version 5.10.0-rc6 (florent@panda) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2020.11-281-g69e5046e7b) 10.2.0, GNU ld (GNU Binutils) 2.33.1) #32 SMP Tue Dec 15 10:55:28 CET 2020 [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') [ 0.000000] printk: bootconsole [sbi0] enabled [ 0.000000] Initial ramdisk at: 0x(ptrval) (8388608 bytes) [ 0.000000] Zone ranges: [ 0.000000] Normal [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] SBI specification v0.2 detected [ 0.000000] SBI implementation ID=0x1 Version=0x8 [ 0.000000] SBI v0.2 TIME extension detected [ 0.000000] SBI v0.2 IPI extension detected [ 0.000000] SBI v0.2 RFENCE extension detected [ 0.000000] SBI v0.2 HSM extension detected [ 0.000000] riscv: ISA extensions aim [ 0.000000] riscv: ELF capabilities aim [ 0.000000] percpu: Embedded 10 pages/cpu s18892 r0 d22068 u40960 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 65024 [ 0.000000] Kernel command line: mem=256M@0x40000000 rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32 [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear) [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear) [ 0.000000] Sorting __ex_table... [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] Memory: 243800K/262144K available (5494K kernel code, 573K rwdata, 829K rodata, 178K init, 221K bss, 18344K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] riscv-intc: 32 local interrupts mapped [ 0.000000] plic: interrupt-controller@f0c00000: mapped 32 interrupts with 1 handlers for 2 contexts. [ 0.000000] random: get_random_bytes called from start_kernel+0x35c/0x4dc with crng_init=0 [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x2298375bd0, max_idle_ns: 440795208267 ns [ 0.000105] sched_clock: 64 bits at 150MHz, resolution 6ns, wraps every 2199023255551ns [ 0.002443] Console: colour dummy device 80x25 [ 0.003489] Calibrating delay loop (skipped), value calculated using timer frequency.. 300.00 BogoMIPS (lpj=600000) [ 0.005360] pid_max: default: 32768 minimum: 301 [ 0.008450] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.009801] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.026343] rcu: Hierarchical SRCU implementation. [ 0.030579] smp: Bringing up secondary CPUs ... [ 0.031455] smp: Brought up 1 node, 1 CPU [ 0.035560] devtmpfs: initialized [ 0.054392] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.056130] futex hash table entries: 256 (order: 2, 16384 bytes, linear) [ 0.060260] NET: Registered protocol family 16 [ 0.168818] FPGA manager framework [ 0.177750] clocksource: Switched to clocksource riscv_clocksource [ 0.283415] NET: Registered protocol family 2 [ 0.289456] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) [ 0.291287] TCP established hash table entries: 2048 (order: 1, 8192 bytes, linear) [ 0.292889] TCP bind hash table entries: 2048 (order: 2, 16384 bytes, linear) [ 0.294597] TCP: Hash tables configured (established 2048 bind 2048) [ 0.296284] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.297811] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.304538] Unpacking initramfs... [ 0.858127] Initramfs unpacking failed: invalid magic at start of compressed archive [ 0.894602] Freeing initrd memory: 8192K [ 0.900959] workingset: timestamp_bits=30 max_order=16 bucket_order=0 [ 1.059967] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 1.061261] io scheduler mq-deadline registered [ 1.062319] io scheduler kyber registered [ 1.068276] LiteX SoC Controller driver initialized: subreg=1, align=4 [ 1.722856] f0001000.serial: ttyLXU0 at MMIO 0xf0001000 (irq = 0, base_baud = 0) is a liteuart [ 1.725760] printk: console [liteuart0] enabled [ 1.725760] printk: console [liteuart0] enabled [ 1.726753] printk: bootconsole [sbi0] disabled [ 1.726753] printk: bootconsole [sbi0] disabled [ 1.737404] litex-spiflash f0005800.spiflash: unrecognized JEDEC id bytes: ff ff ff ff ff ff [ 1.738069] litex-spiflash f0005800.spiflash: SPI_NOR_SCAN FAILED [ 1.738595] litex-spiflash: probe of f0005800.spiflash failed with error -2 [ 1.758144] libphy: Fixed MDIO Bus: probed [ 1.759091] liteeth f0004800.mac: IRQ index 0 not found [ 1.759448] liteeth f0004800.mac: Failed to get IRQ, using polling [ 1.767354] liteeth f0004800.mac eth0: irq 0, mapped at a0409800 [ 1.770000] i2c /dev entries driver [ 1.802472] mmc_spi spi0.0: SD/MMC host mmc0, no WP, no poweroff, cd polling [ 1.826923] NET: Registered protocol family 10 [ 1.838271] Segment Routing with IPv6 [ 1.839271] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver [ 1.867399] Freeing unused kernel memory: 176K [ 1.867670] Kernel memory protection not selected by kernel config. [ 1.868120] Run /init as init process [ 1.942536] mmc0: host does not support reading read-only switch, assuming write-enable [ 1.943056] mmc0: new SDHC card on SPI [ 1.952401] mmcblk0: mmc0:0000 SB32G 29.7 GiB [ 2.084940] mmcblk0: p1 [ 2.282938] tmpfs: Unknown parameter 'mode' mount: mounting tmpfs on /dev/shm failed: Invalid argument [ 2.287377] tmpfs: Unknown parameter 'mode' mount: mounting tmpfs on /tmp failed: Invalid argument [ 2.291903] tmpfs: Unknown parameter 'mode' mount: mounting tmpfs on /run failed: Invalid argument Starting syslogd: OK Starting klogd: OK Running sysctl: OK Saving random seed: [ 3.222872] random: dd: uninitialized urandom read (512 bytes read) OK Starting network: OK Welcome to Buildroot buildroot login: root __ _ / / (_)__ __ ____ __ / /__/ / _ \/ // /\ \ / /____/_/_//_/\_,_//_\_\ / _ \/ _ \ __ _ __ _ _\___/_//_/ ___ _ / / (_) /____ | |/_/__| | / /____ __ / _ \(_)__ _____ __ / /__/ / __/ -_)>