{"payload":{"header_redesign_enabled":false,"results":[{"id":"166614783","archived":false,"color":"#b2b7f8","followers":128,"has_funding_file":false,"hl_name":"liuqdev/8-bits-RISC-CPU-Verilog","hl_trunc_description":"Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":166614783,"name":"8-bits-RISC-CPU-Verilog","owner_id":18116496,"owner_login":"liuqdev","updated_at":"2019-01-20T02:49:20.967Z","has_issues":true}},"sponsorable":false,"topics":["cpu","fsm","verilog","risc"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":70,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aliuqdev%252F8-bits-RISC-CPU-Verilog%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/liuqdev/8-bits-RISC-CPU-Verilog/star":{"post":"HpYuUSjgSg2eBYa3wCg3zxVVNPPpyc58n8QHYbaAUmS_J1772F5coR0rWr58YQikzrr_P2GwFSXju4eBi7MLOg"},"/liuqdev/8-bits-RISC-CPU-Verilog/unstar":{"post":"jiNRuUgOQPmvcQxH85GQalgC5-e9vv2D4dDXcNCz0gCdV99l5uPzI9-jlZcWeAZXseCN7zrwWElNf7PO9pcvkg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"op764QwUCL6ufQ3yn_dvKQPA7nsojCUO_26YCdFBL29JvSlm88WsxekX93h5BnojEBGgyliKMtjNzbOXy6icww"}}},"title":"Repository search results"}