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Merge pull request #130 from yrrebnarg/support-mod

DCPU16: support for unsigned mod; tests
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2 parents bcda71c + ae0b774 commit f01055e350921f8f862d6f0c8e2f9999b79131de @hasenbanck hasenbanck committed Apr 17, 2012
Showing with 19 additions and 1 deletion.
  1. +0 −1 lib/Target/DCPU16/DCPU16ISelLowering.cpp
  2. +1 −0 lib/Target/DCPU16/DCPU16InstrInfo.td
  3. +18 −0 test/CodeGen/DCPU16/mod.ll
@@ -98,7 +98,6 @@ DCPU16TargetLowering::DCPU16TargetLowering(DCPU16TargetMachine &tm) :
setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::UREM, MVT::i16, Expand);
setOperationAction(ISD::SDIV, MVT::i16, Expand);
setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
setOperationAction(ISD::SREM, MVT::i16, Expand);
@@ -364,6 +364,7 @@ let Defs = [RO] in {
defm SUB16 : BASIC_RR_NON_COM<0x0, "SUB", sub>, BASIC_NORMAL<0x0, "SUB", sub>;
defm MUL16 : BASIC_RR_IS_COM <0x0, "MUL", mul>, BASIC_NORMAL<0x0, "MUL", mul>;
defm DIV16 : BASIC_RR_NON_COM<0x0, "DIV", udiv>, BASIC_NORMAL<0x0, "DIV", udiv>;
+ defm MOD16 : BASIC_RR_NON_COM<0x0, "MOD", urem>, BASIC_NORMAL<0x0, "MOD", urem>;
defm SRL16 : BASIC_RR_NON_COM<0x0, "SHR", srl>, BASIC_NORMAL<0x0, "SHR", srl>;
// FIXME: replace this instruction with the correct arithmetic shift once
View
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=dcpu16 | FileCheck %s
+target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-i64:64:64-n8:16"
+target triple = "dcpu16"
+
+define i16 @mod(i16 %a, i16 %b, i16* nocapture %c) nounwind readonly {
+entry:
+ %mod = urem i16 %a, %b
+ %0 = load i16* %c, align 2
+ %mod1 = urem i16 %a, %0
+ %mod2 = urem i16 %a, 17
+ %add = add i16 %mod1, %mod
+ %add3 = add i16 %add, %mod2
+ ret i16 %add3
+}
+; CHECK: :mod
+; CHECK: MOD X, B
+; CHECK: MOD B, [C]
+; CHECK: MOD A, 0x11

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