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Remove the cellspu port.

Approved by Chris Lattner.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@167983 91177308-0d34-0410-b5e6-96231b3b80d8
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1 parent 5a95d46 commit 825d386c1d66c2444117c0142c4d79246aaaa9bd @echristo echristo committed Nov 14, 2012
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@@ -384,13 +384,13 @@ class OpenBSDTargetInfo : public OSTargetInfo<Target> {
case llvm::Triple::x86:
case llvm::Triple::x86_64:
case llvm::Triple::arm:
- case llvm::Triple::sparc:
+ case llvm::Triple::sparc:
this->MCountName = "__mcount";
break;
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::ppc:
- case llvm::Triple::sparcv9:
+ case llvm::Triple::sparcv9:
this->MCountName = "_mcount";
break;
}
@@ -1647,7 +1647,7 @@ class X86TargetInfo : public TargetInfo {
NumAliases = 0;
}
virtual void getGCCAddlRegNames(const AddlRegName *&Names,
- unsigned &NumNames) const {
+ unsigned &NumNames) const {
Names = AddlRegNames;
NumNames = llvm::array_lengthof(AddlRegNames);
}
@@ -3325,11 +3325,11 @@ class ARMTargetInfo : public TargetInfo {
case 'v': // ...VFP load/store (reg+constant offset)
case 'y': // ...iWMMXt load/store
case 't': // address valid for load/store opaque types wider
- // than 128-bits
+ // than 128-bits
case 'n': // valid address for Neon doubleword vector load/store
case 'm': // valid address for Neon element and structure load/store
case 's': // valid address for non-offset loads/stores of quad-word
- // values in four ARM registers
+ // values in four ARM registers
Info.setAllowsMemory();
Name++;
return true;
@@ -4580,10 +4580,6 @@ static TargetInfo *AllocateTarget(const std::string &T) {
return new SparcV8TargetInfo(T);
}
- // FIXME: Need a real SPU target.
- case llvm::Triple::cellspu:
- return new PS3SPUTargetInfo<PPC64TargetInfo>(T);
-
case llvm::Triple::tce:
return new TCETargetInfo(T);
@@ -1,7 +1,6 @@
// RUN: %clang_cc1 -triple i686 %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple x86_64 %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple arm %s -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -triple cellspu %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple mblaze %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple mips %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple mipsel %s -emit-llvm -o - | FileCheck %s
@@ -17,7 +17,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
'-I%s/include' % root.llvm_src_root,
'-I%s/include' % root.llvm_obj_root,
'-I%s/lib/Target/ARM' % root.llvm_src_root,
- '-I%s/lib/Target/CellSPU' % root.llvm_src_root,
'-I%s/lib/Target/CppBackend' % root.llvm_src_root,
'-I%s/lib/Target/Mips' % root.llvm_src_root,
'-I%s/lib/Target/MSIL' % root.llvm_src_root,
@@ -28,7 +27,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
'-I%s/lib/Target/X86' % root.llvm_src_root,
'-I%s/lib/Target/XCore' % root.llvm_src_root,
'-I%s/lib/Target/ARM' % target_obj_root,
- '-I%s/lib/Target/CellSPU' % target_obj_root,
'-I%s/lib/Target/CppBackend' % target_obj_root,
'-I%s/lib/Target/Mips' % target_obj_root,
'-I%s/lib/Target/MSIL' % target_obj_root,
@@ -17,7 +17,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
'-I%s/include' % root.llvm_src_root,
'-I%s/include' % root.llvm_obj_root,
'-I%s/lib/Target/ARM' % root.llvm_src_root,
- '-I%s/lib/Target/CellSPU' % root.llvm_src_root,
'-I%s/lib/Target/CppBackend' % root.llvm_src_root,
'-I%s/lib/Target/Mips' % root.llvm_src_root,
'-I%s/lib/Target/MSIL' % root.llvm_src_root,
@@ -28,7 +27,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
'-I%s/lib/Target/X86' % root.llvm_src_root,
'-I%s/lib/Target/XCore' % root.llvm_src_root,
'-I%s/lib/Target/ARM' % target_obj_root,
- '-I%s/lib/Target/CellSPU' % target_obj_root,
'-I%s/lib/Target/CppBackend' % target_obj_root,
'-I%s/lib/Target/Mips' % target_obj_root,
'-I%s/lib/Target/MSIL' % target_obj_root,
@@ -16,7 +16,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
'-I%s/include' % root.llvm_src_root,
'-I%s/include' % root.llvm_obj_root,
'-I%s/lib/Target/ARM' % root.llvm_src_root,
- '-I%s/lib/Target/CellSPU' % root.llvm_src_root,
'-I%s/lib/Target/CppBackend' % root.llvm_src_root,
'-I%s/lib/Target/Mips' % root.llvm_src_root,
'-I%s/lib/Target/MSIL' % root.llvm_src_root,
@@ -27,7 +26,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
'-I%s/lib/Target/X86' % root.llvm_src_root,
'-I%s/lib/Target/XCore' % root.llvm_src_root,
'-I%s/lib/Target/ARM' % target_obj_root,
- '-I%s/lib/Target/CellSPU' % target_obj_root,
'-I%s/lib/Target/CppBackend' % target_obj_root,
'-I%s/lib/Target/Mips' % target_obj_root,
'-I%s/lib/Target/MSIL' % target_obj_root,

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