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[ARM] Add support for nest attribute using r12

Register r12 ('ip') is used by GCC for this purpose
and hence is used here. As discussed on the GCC mailing
list, the register choice is an ABI issue and so
choosing the same register as GCC means
__builtin_call_with_static_chain is compatible.

A similar patch has just gone in the AArch64 backend,
so this is just the ARM counterpart, following the same

Patch by Stephen Cross.

git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
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rengolin committed Jul 12, 2015
1 parent 07c08a6 commit 4173058d07bb369942b4aa3003d09dd2e8e096ea
Showing with 24 additions and 0 deletions.
  1. +3 −0 lib/Target/ARM/
  2. +21 −0 test/CodeGen/ARM/nest-register.ll
@@ -142,6 +142,9 @@ def CC_ARM_AAPCS : CallingConv<[
// Handles byval parameters.
CCIfByVal<CCPassByVal<4, 4>>,
// The 'nest' parameter, if any, is passed in R12.
// Handle all vector types as either f64 or v2f64.
CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
@@ -0,0 +1,21 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register.
define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver:
; CHECK: @ BB#0:
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov pc, lr
ret i8* %arg
define i8* @nest_caller(i8* %arg) nounwind {
; CHECK-LABEL: nest_caller:
; CHECK: mov r12, r0
; CHECK-NEXT: bl nest_receiver
; CHECK: mov pc, lr
%result = call i8* @nest_receiver(i8* nest %arg)
ret i8* %result

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