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Remove the code that emits MIPS' .cprestore directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157493 91177308-0d34-0410-b5e6-96231b3b80d8
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1 parent 65d5629 commit 6a1a2b139562bb2b17771a88f68dcb7dd006b4d4 Akira Hatanaka committed May 25, 2012
Showing with 0 additions and 50 deletions.
  1. +0 −22 lib/Target/Mips/MipsAsmPrinter.cpp
  2. +0 −27 lib/Target/Mips/MipsMCInstLower.cpp
  3. +0 −1 lib/Target/Mips/MipsMCInstLower.h
@@ -112,28 +112,6 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return;
}
- case Mips::CPRESTORE: {
- const MachineOperand &MO = MI->getOperand(0);
- assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
- int64_t Offset = MO.getImm();
-
- if (OutStreamer.hasRawTextSupport()) {
- if (!isInt<16>(Offset)) {
- EmitInstrWithMacroNoAT(MI);
- return;
- }
- } else {
- MCInstLowering.LowerCPRESTORE(Offset, MCInsts);
-
- for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
- I != MCInsts.end(); ++I)
- OutStreamer.EmitInstruction(*I);
-
- return;
- }
-
- break;
- }
default:
break;
}
@@ -140,33 +140,6 @@ void MipsMCInstLower::LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts) {
CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg);
}
-// Lower ".cprestore offset" to "sw $gp, offset($sp)".
-void MipsMCInstLower::LowerCPRESTORE(int64_t Offset,
- SmallVector<MCInst, 4>& MCInsts) {
- assert(isInt<32>(Offset) && (Offset >= 0) &&
- "Imm operand of .cprestore must be a non-negative 32-bit value.");
-
- MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
- MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
-
- if (!isInt<16>(Offset)) {
- unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff;
- Offset &= 0xffff;
- MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
- BaseReg = ATReg;
-
- // lui at,hi
- // addu at,at,sp
- MCInsts.resize(2);
- CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi));
- CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg);
- }
-
- MCInst Sw;
- CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
- MCInsts.push_back(Sw);
-}
-
MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
unsigned offset) const {
MachineOperandType MOTy = MO.getType();
@@ -34,7 +34,6 @@ class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
void Initialize(Mangler *mang, MCContext* C);
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
void LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts);
- void LowerCPRESTORE(int64_t Offset, SmallVector<MCInst, 4>& MCInsts);
void LowerUnalignedLoadStore(const MachineInstr *MI,
SmallVector<MCInst, 4>& MCInsts);
void LowerSETGP01(SmallVector<MCInst, 4>& MCInsts);

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