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Add AArch64 as an experimental target.

This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.

This initial commit should have support for:
    + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
      (except the late addition CRC instructions).
    + CodeGen features required for C++03 and C99.
    + Compilation for the "small" memory model: code+static data <
      4GB.
    + Absolute and position-independent code.
    + GNU-style (i.e. "__thread") TLS.
    + Debugging information.

The principal omission, currently, is performance tuning.

This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.

Further reviews would be gratefully received.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information...
Tim Northover Tim Northover
Tim Northover authored and Tim Northover committed Jan 31, 2013
1 parent d72b4d3 commit 72062f5744557e270a38192554c3126ea5f97434
Showing with 45,628 additions and 13 deletions.
  1. +3 −1 autoconf/config.sub
  2. +4 −1 autoconf/configure.ac
  3. +7 −3 configure
  4. +7 −0 docs/CompilerWriterInfo.rst
  5. +1 −0 include/llvm/ADT/Triple.h
  6. +2 −0 include/llvm/MC/MCExpr.h
  7. +1 −0 include/llvm/MC/MCObjectWriter.h
  8. +85 −0 include/llvm/Object/ELF.h
  9. +91 −0 include/llvm/Support/ELF.h
  10. +3 −1 lib/MC/MCELFStreamer.cpp
  11. +19 −0 lib/MC/MCObjectFileInfo.cpp
  12. +8 −0 lib/Support/Triple.cpp
  13. +42 −0 lib/Target/AArch64/AArch64.h
  14. +68 −0 lib/Target/AArch64/AArch64.td
  15. +361 −0 lib/Target/AArch64/AArch64AsmPrinter.cpp
  16. +85 −0 lib/Target/AArch64/AArch64AsmPrinter.h
  17. +196 −0 lib/Target/AArch64/AArch64CallingConv.td
  18. +1,420 −0 lib/Target/AArch64/AArch64ConstantIslandPass.cpp
  19. +644 −0 lib/Target/AArch64/AArch64FrameLowering.cpp
  20. +103 −0 lib/Target/AArch64/AArch64FrameLowering.h
  21. +422 −0 lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  22. +2,957 −0 lib/Target/AArch64/AArch64ISelLowering.cpp
  23. +247 −0 lib/Target/AArch64/AArch64ISelLowering.h
  24. +1,011 −0 lib/Target/AArch64/AArch64InstrFormats.td
  25. +805 −0 lib/Target/AArch64/AArch64InstrInfo.cpp
  26. +110 −0 lib/Target/AArch64/AArch64InstrInfo.h
  27. +5,298 −0 lib/Target/AArch64/AArch64InstrInfo.td
  28. +140 −0 lib/Target/AArch64/AArch64MCInstLower.cpp
  29. +14 −0 lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
  30. +158 −0 lib/Target/AArch64/AArch64MachineFunctionInfo.h
  31. +211 −0 lib/Target/AArch64/AArch64RegisterInfo.cpp
  32. +79 −0 lib/Target/AArch64/AArch64RegisterInfo.h
  33. +205 −0 lib/Target/AArch64/AArch64RegisterInfo.td
  34. +10 −0 lib/Target/AArch64/AArch64Schedule.td
  35. +25 −0 lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
  36. +32 −0 lib/Target/AArch64/AArch64SelectionDAGInfo.h
  37. +43 −0 lib/Target/AArch64/AArch64Subtarget.cpp
  38. +54 −0 lib/Target/AArch64/AArch64Subtarget.h
  39. +78 −0 lib/Target/AArch64/AArch64TargetMachine.cpp
  40. +69 −0 lib/Target/AArch64/AArch64TargetMachine.h
  41. +19 −0 lib/Target/AArch64/AArch64TargetObjectFile.cpp
  42. +27 −0 lib/Target/AArch64/AArch64TargetObjectFile.h
  43. +2,025 −0 lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  44. +7 −0 lib/Target/AArch64/AsmParser/CMakeLists.txt
  45. +24 −0 lib/Target/AArch64/AsmParser/LLVMBuild.txt
  46. +15 −0 lib/Target/AArch64/AsmParser/Makefile
  47. +35 −0 lib/Target/AArch64/CMakeLists.txt
  48. +791 −0 lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  49. +7 −0 lib/Target/AArch64/Disassembler/CMakeLists.txt
  50. +24 −0 lib/Target/AArch64/Disassembler/LLVMBuild.txt
  51. +16 −0 lib/Target/AArch64/Disassembler/Makefile
  52. +408 −0 lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
  53. +171 −0 lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
  54. +8 −0 lib/Target/AArch64/InstPrinter/CMakeLists.txt
  55. +24 −0 lib/Target/AArch64/InstPrinter/LLVMBuild.txt
  56. +15 −0 lib/Target/AArch64/InstPrinter/Makefile
  57. +36 −0 lib/Target/AArch64/LLVMBuild.txt
  58. +580 −0 lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
  59. +779 −0 lib/Target/AArch64/MCTargetDesc/AArch64BaseInfo.h
  60. +287 −0 lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
  61. +160 −0 lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
  62. +27 −0 lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h
  63. +108 −0 lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
  64. +41 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
  65. +27 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
  66. +517 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  67. +173 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
  68. +161 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
  69. +991 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  70. +65 −0 lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
  71. +13 −0 lib/Target/AArch64/MCTargetDesc/CMakeLists.txt
  72. +24 −0 lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt
  73. +16 −0 lib/Target/AArch64/MCTargetDesc/Makefile
  74. +30 −0 lib/Target/AArch64/Makefile
  75. +2 −0 lib/Target/AArch64/README.txt
  76. +20 −0 lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
  77. +7 −0 lib/Target/AArch64/TargetInfo/CMakeLists.txt
  78. +24 −0 lib/Target/AArch64/TargetInfo/LLVMBuild.txt
  79. +15 −0 lib/Target/AArch64/TargetInfo/Makefile
  80. +3 −0 lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
  81. +1 −1 lib/Target/LLVMBuild.txt
  82. +3 −1 projects/sample/autoconf/config.sub
  83. +5 −1 projects/sample/autoconf/configure.ac
  84. +7 −2 projects/sample/configure
  85. +54 −0 test/CodeGen/AArch64/adc.ll
  86. +295 −0 test/CodeGen/AArch64/addsub-shifted.ll
  87. +127 −0 test/CodeGen/AArch64/addsub.ll
  88. +189 −0 test/CodeGen/AArch64/addsub_ext.ll
  89. +35 −0 test/CodeGen/AArch64/adrp-relocation.ll
  90. +134 −0 test/CodeGen/AArch64/alloca.ll
  91. +231 −0 test/CodeGen/AArch64/analyze-branch.ll
  92. +24 −0 test/CodeGen/AArch64/atomic-ops-not-barriers.ll
  93. +1,099 −0 test/CodeGen/AArch64/atomic-ops.ll
  94. +70 −0 test/CodeGen/AArch64/basic-pic.ll
  95. +19 −0 test/CodeGen/AArch64/bitfield-insert-0.ll
  96. +193 −0 test/CodeGen/AArch64/bitfield-insert.ll
  97. +218 −0 test/CodeGen/AArch64/bitfield.ll
  98. +18 −0 test/CodeGen/AArch64/blockaddress.ll
  99. +55 −0 test/CodeGen/AArch64/bool-loads.ll
  100. +17 −0 test/CodeGen/AArch64/breg.ll
  101. +86 −0 test/CodeGen/AArch64/callee-save.ll
  102. +38 −0 test/CodeGen/AArch64/compare-branch.ll
  103. +213 −0 test/CodeGen/AArch64/cond-sel.ll
  104. +84 −0 test/CodeGen/AArch64/directcond.ll
  105. +163 −0 test/CodeGen/AArch64/dp-3source.ll
  106. +152 −0 test/CodeGen/AArch64/dp1.ll
  107. +169 −0 test/CodeGen/AArch64/dp2.ll
  108. +21 −0 test/CodeGen/AArch64/elf-extern.ll
  109. +57 −0 test/CodeGen/AArch64/extract.ll
  110. +58 −0 test/CodeGen/AArch64/fastcc-reserved.ll
  111. +123 −0 test/CodeGen/AArch64/fastcc.ll
  112. +81 −0 test/CodeGen/AArch64/fcmp.ll
  113. +191 −0 test/CodeGen/AArch64/fcvt-fixed.ll
  114. +151 −0 test/CodeGen/AArch64/fcvt-int.ll
  115. +35 −0 test/CodeGen/AArch64/flags-multiuse.ll
  116. +138 −0 test/CodeGen/AArch64/floatdp_1source.ll
  117. +60 −0 test/CodeGen/AArch64/floatdp_2source.ll
  118. +26 −0 test/CodeGen/AArch64/fp-cond-sel.ll
  119. +102 −0 test/CodeGen/AArch64/fp-dp3.ll
  120. +17 −0 test/CodeGen/AArch64/fp128-folding.ll
  121. +280 −0 test/CodeGen/AArch64/fp128.ll
  122. +34 −0 test/CodeGen/AArch64/fpimm.ll
  123. +192 −0 test/CodeGen/AArch64/func-argpassing.ll
  124. +140 −0 test/CodeGen/AArch64/func-calls.ll
  125. +69 −0 test/CodeGen/AArch64/global-alignment.ll
  126. +23 −0 test/CodeGen/AArch64/got-abuse.ll
  127. +29 −0 test/CodeGen/AArch64/i128-align.ll
  128. +221 −0 test/CodeGen/AArch64/illegal-float-ops.ll
  129. +9 −0 test/CodeGen/AArch64/init-array.ll
  130. +7 −0 test/CodeGen/AArch64/inline-asm-constraints-badI.ll
  131. +7 −0 test/CodeGen/AArch64/inline-asm-constraints-badK.ll
  132. +7 −0 test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
  133. +7 −0 test/CodeGen/AArch64/inline-asm-constraints-badL.ll
  134. +117 −0 test/CodeGen/AArch64/inline-asm-constraints.ll
  135. +125 −0 test/CodeGen/AArch64/inline-asm-modifiers.ll
  136. +56 −0 test/CodeGen/AArch64/jump-table.ll
  137. +117 −0 test/CodeGen/AArch64/large-frame.ll
  138. +333 −0 test/CodeGen/AArch64/ldst-regoffset.ll
  139. +218 −0 test/CodeGen/AArch64/ldst-unscaledimm.ll
  140. +251 −0 test/CodeGen/AArch64/ldst-unsignedimm.ll
  141. +6 −0 test/CodeGen/AArch64/lit.local.cfg
  142. +49 −0 test/CodeGen/AArch64/literal_pools.ll
  143. +57 −0 test/CodeGen/AArch64/local_vars.ll
  144. +84 −0 test/CodeGen/AArch64/logical-imm.ll
  145. +224 −0 test/CodeGen/AArch64/logical_shifted_reg.ll
  146. +208 −0 test/CodeGen/AArch64/logical_shifted_reg.s
  147. +124 −0 test/CodeGen/AArch64/movw-consts.ll
  148. +60 −0 test/CodeGen/AArch64/pic-eh-stubs.ll
  149. +11 −0 test/CodeGen/AArch64/regress-bitcast-formals.ll
  150. +27 −0 test/CodeGen/AArch64/regress-f128csel-flags.ll
  151. +19 −0 test/CodeGen/AArch64/regress-tail-livereg.ll
  152. +36 −0 test/CodeGen/AArch64/regress-tblgen-chains.ll
  153. +37 −0 test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
  154. +41 −0 test/CodeGen/AArch64/regress-wzr-allocatable.ll
  155. +22 −0 test/CodeGen/AArch64/setcc-takes-i32.ll
  156. +97 −0 test/CodeGen/AArch64/sibling-call.ll
  157. +94 −0 test/CodeGen/AArch64/tail-call.ll
  158. +18 −0 test/CodeGen/AArch64/tls-dynamic-together.ll
  159. +121 −0 test/CodeGen/AArch64/tls-dynamics.ll
  160. +63 −0 test/CodeGen/AArch64/tls-execs.ll
  161. +48 −0 test/CodeGen/AArch64/tst-br.ll
  162. +144 −0 test/CodeGen/AArch64/variadic.ll
  163. +31 −0 test/CodeGen/AArch64/zero-reg.ll
  164. +58 −0 test/DebugInfo/AArch64/cfi-frame.ll
  165. +51 −0 test/DebugInfo/AArch64/eh_frame.ll
  166. +46 −0 test/DebugInfo/AArch64/eh_frame_personality.ll
  167. +6 −0 test/DebugInfo/AArch64/lit.local.cfg
  168. +87 −0 test/DebugInfo/AArch64/variable-loc.ll
  169. +3,709 −0 test/MC/AArch64/basic-a64-diagnostics.s
  170. +4,790 −0 test/MC/AArch64/basic-a64-instructions.s
  171. +111 −0 test/MC/AArch64/elf-globaladdress.ll
  172. +5 −0 test/MC/AArch64/elf-objdump.s
  173. +13 −0 test/MC/AArch64/elf-reloc-addsubimm.s
  174. +13 −0 test/MC/AArch64/elf-reloc-condbr.s
  175. +28 −0 test/MC/AArch64/elf-reloc-ldrlit.s
  176. +34 −0 test/MC/AArch64/elf-reloc-ldstunsimm.s
  177. +98 −0 test/MC/AArch64/elf-reloc-movw.s
  178. +29 −0 test/MC/AArch64/elf-reloc-pcreladdressing.s
  179. +18 −0 test/MC/AArch64/elf-reloc-tstb.s
  180. +18 −0 test/MC/AArch64/elf-reloc-uncondbrimm.s
  181. +5 −0 test/MC/AArch64/lit.local.cfg
  182. +28 −0 test/MC/AArch64/mapping-across-sections.s
  183. +23 −0 test/MC/AArch64/mapping-within-section.s
  184. +662 −0 test/MC/AArch64/tls-relocs.s
  185. +4,145 −0 test/MC/Disassembler/AArch64/basic-a64-instructions.txt
  186. +43 −0 test/MC/Disassembler/AArch64/basic-a64-undefined.txt
  187. +96 −0 test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt
  188. +7 −0 test/MC/Disassembler/AArch64/ldp-offset-predictable.txt
  189. +17 −0 test/MC/Disassembler/AArch64/ldp-postind.predictable.txt
  190. +17 −0 test/MC/Disassembler/AArch64/ldp-preind.predictable.txt
  191. +6 −0 test/MC/Disassembler/AArch64/lit.local.cfg
  192. +3 −2 utils/TableGen/DisassemblerEmitter.cpp
@@ -251,7 +251,8 @@ case $basic_machine in
| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
| am33_2.0 \
| arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \
| be32 | be64 \
| aarch64 \
| be32 | be64 \
| bfin \
| c4x | clipper \
| d10v | d30v | dlx | dsp16xx \
@@ -359,6 +360,7 @@ case $basic_machine in
| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
| alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
| arm-* | armbe-* | armle-* | armeb-* | armv*-* \
| aarch64-* \
| avr-* | avr32-* \
| be32-* | be64-* \
| bfin-* | bs2000-* \
@@ -389,6 +389,7 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
aarch64*-*) llvm_cv_target_arch="AArch64" ;;
mips-* | mips64-*) llvm_cv_target_arch="Mips" ;;
mipsel-* | mips64el-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -422,6 +423,7 @@ case $host in
sparc*-*) host_arch="Sparc" ;;
powerpc*-*) host_arch="PowerPC" ;;
arm*-*) host_arch="ARM" ;;
aarch64*-*) host_arch="AArch64" ;;
mips-* | mips64-*) host_arch="Mips" ;;
mipsel-* | mips64el-*) host_arch="Mips" ;;
xcore-*) host_arch="XCore" ;;
@@ -640,6 +642,7 @@ else
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
AArch64) AC_SUBST(TARGET_HAS_JIT,0) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
MSP430) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -771,7 +774,7 @@ dnl Allow specific targets to be specified for building (or not)
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
host, x86, x86_64, sparc, powerpc, arm, mips, hexagon,
host, x86, x86_64, sparc, powerpc, arm, aarch64, mips, hexagon,
xcore, msp430, nvptx, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
@@ -1438,8 +1438,8 @@ Optional Features:
YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
x86_64, sparc, powerpc, arm, mips, hexagon, xcore,
msp430, nvptx, and cpp (default=all)
x86_64, sparc, powerpc, arm, aarch64, mips, hexagon,
xcore, msp430, nvptx, and cpp (default=all)
--enable-experimental-targets
Build experimental host targets: disable or
target1,target2,... (default=disable)
@@ -4008,6 +4008,7 @@ else
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
aarch64*-*) llvm_cv_target_arch="AArch64" ;;
mips-* | mips64-*) llvm_cv_target_arch="Mips" ;;
mipsel-* | mips64el-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -4041,6 +4042,7 @@ case $host in
sparc*-*) host_arch="Sparc" ;;
powerpc*-*) host_arch="PowerPC" ;;
arm*-*) host_arch="ARM" ;;
aarch64*-*) host_arch="AArch64" ;;
mips-* | mips64-*) host_arch="Mips" ;;
mipsel-* | mips64el-*) host_arch="Mips" ;;
xcore-*) host_arch="XCore" ;;
@@ -5372,6 +5374,8 @@ else
x86_64) TARGET_HAS_JIT=1
;;
ARM) TARGET_HAS_JIT=1
;;
AArch64) TARGET_HAS_JIT=0
;;
Mips) TARGET_HAS_JIT=1
;;
@@ -10489,7 +10493,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 10492 "configure"
#line 10496 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -22,6 +22,11 @@ ARM

* `ABI <http://www.arm.com/products/DevTools/ABI.html>`_

AArch64
-------

* `ARMv8 Instruction Set Overview <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html>`_

Itanium (ia64)
--------------

@@ -99,6 +104,8 @@ Linux
-----

* `PowerPC 64-bit ELF ABI Supplement <http://www.linuxbase.org/spec/ELF/ppc64/>`_
* `Procedure Call Standard for the AArch64 Architecture <http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055a/IHI0055A_aapcs64.pdf>`_
* `ELF for the ARM 64-bit Architecture (AArch64) <http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056a/IHI0056A_aaelf64.pdf>`_

OS X
----
@@ -44,6 +44,7 @@ class Triple {
UnknownArch,

arm, // ARM; arm, armv.*, xscale
aarch64, // AArch64: aarch64
hexagon, // Hexagon: hexagon
mips, // MIPS: mips, mipsallegrex
mipsel, // MIPSEL: mipsel, mipsallegrexel
@@ -472,6 +472,8 @@ class MCTargetExpr : public MCExpr {
virtual void AddValueSymbols(MCAssembler *) const = 0;
virtual const MCSection *FindAssociatedSection() const = 0;

virtual void fixELFSymbolsInTLSFixups(MCAssembler &) const = 0;

static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;
}
@@ -10,6 +10,7 @@
#ifndef LLVM_MC_MCOBJECTWRITER_H
#define LLVM_MC_MCOBJECTWRITER_H

#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/raw_ostream.h"
@@ -1624,6 +1624,86 @@ error_code ELFObjectFile<ELFT>::getRelocationTypeName(
res = "Unknown";
}
break;
case ELF::EM_AARCH64:
switch (type) {
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_NONE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ABS64);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ABS32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ABS16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_PREL64);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_PREL32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_PREL16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G1_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G2_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G3);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_SABS_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_SABS_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_SABS_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LD_PREL_LO19);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_PREL_LO21);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_PREL_PG_HI21);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADD_ABS_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST8_ABS_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TSTBR14);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_CONDBR19);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_JUMP26);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_CALL26);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST16_ABS_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST32_ABS_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST64_ABS_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST128_ABS_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_GOT_PAGE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LD64_GOT_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_ADD_DTPREL_HI12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_ADD_DTPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST8_DTPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST16_DTPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST32_DTPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST64_DTPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_MOVW_GOTTPREL_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_LD_GOTTPREL_PREL19);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G1_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_ADD_TPREL_HI12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_ADD_TPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_ADD_TPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST8_TPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST16_TPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST32_TPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST64_TPREL_LO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_ADR_PAGE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_LD64_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_ADD_LO12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_CALL);

default:
res = "Unknown";
}
break;
case ELF::EM_ARM:
switch (type) {
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_NONE);
@@ -1937,6 +2017,7 @@ error_code ELFObjectFile<ELFT>::getRelocationValueString(
res = "Unknown";
}
break;
case ELF::EM_AARCH64:
case ELF::EM_ARM:
case ELF::EM_HEXAGON:
res = symname;
@@ -2356,6 +2437,8 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
return "ELF64-i386";
case ELF::EM_X86_64:
return "ELF64-x86-64";
case ELF::EM_AARCH64:
return "ELF64-aarch64";
case ELF::EM_PPC64:
return "ELF64-ppc64";
default:
@@ -2374,6 +2457,8 @@ unsigned ELFObjectFile<ELFT>::getArch() const {
return Triple::x86;
case ELF::EM_X86_64:
return Triple::x86_64;
case ELF::EM_AARCH64:
return Triple::aarch64;
case ELF::EM_ARM:
return Triple::arm;
case ELF::EM_HEXAGON:
@@ -271,6 +271,7 @@ enum {
EM_SLE9X = 179, // Infineon Technologies SLE9X core
EM_L10M = 180, // Intel L10M
EM_K10M = 181, // Intel K10M
EM_AARCH64 = 183, // ARM AArch64
EM_AVR32 = 185, // Atmel Corporation 32-bit microprocessor family
EM_STM8 = 186, // STMicroeletronics STM8 8-bit microcontroller
EM_TILE64 = 187, // Tilera TILE64 multicore architecture family
@@ -494,6 +495,96 @@ enum {
R_PPC64_TLSLD = 108
};

// ELF Relocation types for AArch64

enum {
R_AARCH64_NONE = 0x100,

R_AARCH64_ABS64 = 0x101,
R_AARCH64_ABS32 = 0x102,
R_AARCH64_ABS16 = 0x103,
R_AARCH64_PREL64 = 0x104,
R_AARCH64_PREL32 = 0x105,
R_AARCH64_PREL16 = 0x106,

R_AARCH64_MOVW_UABS_G0 = 0x107,
R_AARCH64_MOVW_UABS_G0_NC = 0x108,
R_AARCH64_MOVW_UABS_G1 = 0x109,
R_AARCH64_MOVW_UABS_G1_NC = 0x10a,
R_AARCH64_MOVW_UABS_G2 = 0x10b,
R_AARCH64_MOVW_UABS_G2_NC = 0x10c,
R_AARCH64_MOVW_UABS_G3 = 0x10d,
R_AARCH64_MOVW_SABS_G0 = 0x10e,
R_AARCH64_MOVW_SABS_G1 = 0x10f,
R_AARCH64_MOVW_SABS_G2 = 0x110,

R_AARCH64_LD_PREL_LO19 = 0x111,
R_AARCH64_ADR_PREL_LO21 = 0x112,
R_AARCH64_ADR_PREL_PG_HI21 = 0x113,
R_AARCH64_ADD_ABS_LO12_NC = 0x115,
R_AARCH64_LDST8_ABS_LO12_NC = 0x116,

R_AARCH64_TSTBR14 = 0x117,
R_AARCH64_CONDBR19 = 0x118,
R_AARCH64_JUMP26 = 0x11a,
R_AARCH64_CALL26 = 0x11b,

R_AARCH64_LDST16_ABS_LO12_NC = 0x11c,
R_AARCH64_LDST32_ABS_LO12_NC = 0x11d,
R_AARCH64_LDST64_ABS_LO12_NC = 0x11e,

R_AARCH64_LDST128_ABS_LO12_NC = 0x12b,

R_AARCH64_ADR_GOT_PAGE = 0x137,
R_AARCH64_LD64_GOT_LO12_NC = 0x138,

R_AARCH64_TLSLD_MOVW_DTPREL_G2 = 0x20b,
R_AARCH64_TLSLD_MOVW_DTPREL_G1 = 0x20c,
R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC = 0x20d,
R_AARCH64_TLSLD_MOVW_DTPREL_G0 = 0x20e,
R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC = 0x20f,
R_AARCH64_TLSLD_ADD_DTPREL_HI12 = 0x210,
R_AARCH64_TLSLD_ADD_DTPREL_LO12 = 0x211,
R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC = 0x212,
R_AARCH64_TLSLD_LDST8_DTPREL_LO12 = 0x213,
R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC = 0x214,
R_AARCH64_TLSLD_LDST16_DTPREL_LO12 = 0x215,
R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC = 0x216,
R_AARCH64_TLSLD_LDST32_DTPREL_LO12 = 0x217,
R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC = 0x218,
R_AARCH64_TLSLD_LDST64_DTPREL_LO12 = 0x219,
R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC = 0x21a,

R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 = 0x21b,
R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC = 0x21c,
R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 = 0x21d,
R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC = 0x21e,
R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 = 0x21f,

R_AARCH64_TLSLE_MOVW_TPREL_G2 = 0x220,
R_AARCH64_TLSLE_MOVW_TPREL_G1 = 0x221,
R_AARCH64_TLSLE_MOVW_TPREL_G1_NC = 0x222,
R_AARCH64_TLSLE_MOVW_TPREL_G0 = 0x223,
R_AARCH64_TLSLE_MOVW_TPREL_G0_NC = 0x224,
R_AARCH64_TLSLE_ADD_TPREL_HI12 = 0x225,
R_AARCH64_TLSLE_ADD_TPREL_LO12 = 0x226,
R_AARCH64_TLSLE_ADD_TPREL_LO12_NC = 0x227,
R_AARCH64_TLSLE_LDST8_TPREL_LO12 = 0x228,
R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC = 0x229,
R_AARCH64_TLSLE_LDST16_TPREL_LO12 = 0x22a,
R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC = 0x22b,
R_AARCH64_TLSLE_LDST32_TPREL_LO12 = 0x22c,
R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 0x22d,
R_AARCH64_TLSLE_LDST64_TPREL_LO12 = 0x22e,
R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC = 0x22f,

R_AARCH64_TLSDESC_ADR_PAGE = 0x232,
R_AARCH64_TLSDESC_LD64_LO12_NC = 0x233,
R_AARCH64_TLSDESC_ADD_LO12_NC = 0x234,

R_AARCH64_TLSDESC_CALL = 0x239
};

// ARM Specific e_flags
enum {
EF_ARM_EABI_UNKNOWN = 0x00000000U,
@@ -300,7 +300,9 @@ void MCELFStreamer::EmitFileDirective(StringRef Filename) {

void MCELFStreamer::fixSymbolsInTLSFixups(const MCExpr *expr) {
switch (expr->getKind()) {
case MCExpr::Target: llvm_unreachable("Can't handle target exprs yet!");
case MCExpr::Target:
cast<MCTargetExpr>(expr)->fixELFSymbolsInTLSFixups(getAssembler());
break;
case MCExpr::Constant:
break;

@@ -256,6 +256,25 @@ void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) {
TTypeEncoding = (CMModel == CodeModel::Small)
? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr;
}
} else if (T.getArch() == Triple::aarch64) {
FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;

// The small model guarantees static code/data size < 4GB, but not where it
// will be in memory. Most of these could end up >2GB away so even a signed
// pc-relative 32-bit address is insufficient, theoretically.
if (RelocM == Reloc::PIC_) {
PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
dwarf::DW_EH_PE_sdata8;
LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8;
FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
dwarf::DW_EH_PE_sdata8;
} else {
PersonalityEncoding = dwarf::DW_EH_PE_absptr;
LSDAEncoding = dwarf::DW_EH_PE_absptr;
FDEEncoding = dwarf::DW_EH_PE_udata4;
TTypeEncoding = dwarf::DW_EH_PE_absptr;
}
} else if (T.getArch() == Triple::ppc64) {
PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
dwarf::DW_EH_PE_udata8;
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