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Annotate shifts and rotates with SchedRW lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177935 91177308-0d34-0410-b5e6-96231b3b80d8
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commit 8a9db4f9adfc29a7721123ddb382c612cf408912 1 parent 1cd1d02
Jakob Stoklund Olesen authored

Showing 1 changed file with 37 additions and 17 deletions. Show diff stats Hide diff stats

  1. +37 17 lib/Target/X86/X86InstrShiftRotate.td
54 lib/Target/X86/X86InstrShiftRotate.td
@@ -15,7 +15,7 @@
15 15
16 16 let Defs = [EFLAGS] in {
17 17
18   -let Constraints = "$src1 = $dst" in {
  18 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
19 19 let Uses = [CL] in {
20 20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 21 "shl{b}\t{%cl, $dst|$dst, CL}",
@@ -62,9 +62,10 @@ def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
62 62 "shl{q}\t$dst", [], IIC_SR>;
63 63 } // hasSideEffects = 0
64 64 } // isConvertibleToThreeAddress = 1
65   -} // Constraints = "$src = $dst"
  65 +} // Constraints = "$src = $dst", SchedRW
66 66
67 67
  68 +let SchedRW = [WriteShiftLd, WriteRMW] in {
68 69 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
69 70 // using CL?
70 71 let Uses = [CL] in {
@@ -118,8 +119,9 @@ def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
118 119 "shl{q}\t$dst",
119 120 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
120 121 IIC_SR>;
  122 +} // SchedRW
121 123
122   -let Constraints = "$src1 = $dst" in {
  124 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
123 125 let Uses = [CL] in {
124 126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
125 127 "shr{b}\t{%cl, $dst|$dst, CL}",
@@ -163,9 +165,10 @@ def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
163 165 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
164 166 "shr{q}\t$dst",
165 167 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
166   -} // Constraints = "$src = $dst"
  168 +} // Constraints = "$src = $dst", SchedRW
167 169
168 170
  171 +let SchedRW = [WriteShiftLd, WriteRMW] in {
169 172 let Uses = [CL] in {
170 173 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
171 174 "shr{b}\t{%cl, $dst|$dst, CL}",
@@ -216,8 +219,9 @@ def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
216 219 "shr{q}\t$dst",
217 220 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
218 221 IIC_SR>;
  222 +} // SchedRW
219 223
220   -let Constraints = "$src1 = $dst" in {
  224 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
221 225 let Uses = [CL] in {
222 226 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
223 227 "sar{b}\t{%cl, $dst|$dst, CL}",
@@ -273,9 +277,10 @@ def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
273 277 "sar{q}\t$dst",
274 278 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
275 279 IIC_SR>;
276   -} // Constraints = "$src = $dst"
  280 +} // Constraints = "$src = $dst", SchedRW
277 281
278 282
  283 +let SchedRW = [WriteShiftLd, WriteRMW] in {
279 284 let Uses = [CL] in {
280 285 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
281 286 "sar{b}\t{%cl, $dst|$dst, CL}",
@@ -330,13 +335,14 @@ def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
330 335 "sar{q}\t$dst",
331 336 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
332 337 IIC_SR>;
  338 +} // SchedRW
333 339
334 340 //===----------------------------------------------------------------------===//
335 341 // Rotate instructions
336 342 //===----------------------------------------------------------------------===//
337 343
338 344 let hasSideEffects = 0 in {
339   -let Constraints = "$src1 = $dst" in {
  345 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
340 346 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
341 347 "rcl{b}\t$dst", [], IIC_SR>;
342 348 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
@@ -405,6 +411,7 @@ def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
405 411
406 412 } // Constraints = "$src = $dst"
407 413
  414 +let SchedRW = [WriteShiftLd, WriteRMW] in {
408 415 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
409 416 "rcl{b}\t$dst", [], IIC_SR>;
410 417 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
@@ -458,9 +465,10 @@ def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
458 465 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
459 466 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
460 467 }
  468 +} // SchedRW
461 469 } // hasSideEffects = 0
462 470
463   -let Constraints = "$src1 = $dst" in {
  471 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
464 472 // FIXME: provide shorter instructions when imm8 == 1
465 473 let Uses = [CL] in {
466 474 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
@@ -512,8 +520,9 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
512 520 "rol{q}\t$dst",
513 521 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
514 522 IIC_SR>;
515   -} // Constraints = "$src = $dst"
  523 +} // Constraints = "$src = $dst", SchedRW
516 524
  525 +let SchedRW = [WriteShiftLd, WriteRMW] in {
517 526 let Uses = [CL] in {
518 527 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
519 528 "rol{b}\t{%cl, $dst|$dst, CL}",
@@ -568,8 +577,9 @@ def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
568 577 "rol{q}\t$dst",
569 578 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
570 579 IIC_SR>;
  580 +} // SchedRW
571 581
572   -let Constraints = "$src1 = $dst" in {
  582 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
573 583 let Uses = [CL] in {
574 584 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
575 585 "ror{b}\t{%cl, $dst|$dst, CL}",
@@ -620,8 +630,9 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
620 630 "ror{q}\t$dst",
621 631 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
622 632 IIC_SR>;
623   -} // Constraints = "$src = $dst"
  633 +} // Constraints = "$src = $dst", SchedRW
624 634
  635 +let SchedRW = [WriteShiftLd, WriteRMW] in {
625 636 let Uses = [CL] in {
626 637 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
627 638 "ror{b}\t{%cl, $dst|$dst, CL}",
@@ -676,13 +687,14 @@ def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
676 687 "ror{q}\t$dst",
677 688 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
678 689 IIC_SR>;
  690 +} // SchedRW
679 691
680 692
681 693 //===----------------------------------------------------------------------===//
682 694 // Double shift instructions (generalizations of rotate)
683 695 //===----------------------------------------------------------------------===//
684 696
685   -let Constraints = "$src1 = $dst" in {
  697 +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
686 698
687 699 let Uses = [CL] in {
688 700 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
@@ -765,8 +777,9 @@ def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
765 777 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
766 778 TB;
767 779 }
768   -} // Constraints = "$src = $dst"
  780 +} // Constraints = "$src = $dst", SchedRW
769 781
  782 +let SchedRW = [WriteShiftLd, WriteRMW] in {
770 783 let Uses = [CL] in {
771 784 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
772 785 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
@@ -840,6 +853,7 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
840 853 (i8 imm:$src3)), addr:$dst)],
841 854 IIC_SHD64_MEM_IM>,
842 855 TB;
  856 +} // SchedRW
843 857
844 858 } // Defs = [EFLAGS]
845 859
@@ -857,12 +871,12 @@ multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
857 871 let neverHasSideEffects = 1 in {
858 872 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
859 873 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
860   - []>, TAXD, VEX;
  874 + []>, TAXD, VEX, Sched<[WriteShift]>;
861 875 let mayLoad = 1 in
862 876 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
863 877 (ins x86memop:$src1, i8imm:$src2),
864 878 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
865   - []>, TAXD, VEX;
  879 + []>, TAXD, VEX, Sched<[WriteShiftLd]>;
866 880 }
867 881 }
868 882
@@ -870,11 +884,17 @@ multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
870 884 let neverHasSideEffects = 1 in {
871 885 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
872 886 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
873   - VEX_4VOp3;
  887 + VEX_4VOp3, Sched<[WriteShift]>;
874 888 let mayLoad = 1 in
875 889 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
876 890 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
877   - VEX_4VOp3;
  891 + VEX_4VOp3,
  892 + Sched<[WriteShiftLd,
  893 + // x86memop:$src1
  894 + ReadDefault, ReadDefault, ReadDefault, ReadDefault,
  895 + ReadDefault,
  896 + // RC:$src1
  897 + ReadAfterLd]>;
878 898 }
879 899 }
880 900

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