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[SystemZ] Add support for IBM z14 processor (1/3)

This patch series adds support for the IBM z14 processor.  This part includes:
- Basic support for the new processor and its features.
- Support for new instructions (except vector 32-bit float and 128-bit float).
- CodeGen for new instructions, including new LLVM intrinsics.
- Scheduler description for the new processor.
- Detection of z14 as host processor.

Support for the new 32-bit vector float and 128-bit vector float
instructions is provided by separate patches.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308194 91177308-0d34-0410-b5e6-96231b3b80d8
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uweigand committed Jul 17, 2017
1 parent 02972a4 commit 8ab242ce954d3dfec4d07bb436aee26e38d48553
Showing with 7,249 additions and 15 deletions.
  1. +27 −0 include/llvm/IR/IntrinsicsSystemZ.td
  2. +2 −0 lib/Support/Host.cpp
  3. +56 −1 lib/Target/SystemZ/SystemZFeatures.td
  4. +24 −1 lib/Target/SystemZ/SystemZISelLowering.cpp
  5. +1 −0 lib/Target/SystemZ/SystemZISelLowering.h
  6. +316 −10 lib/Target/SystemZ/SystemZInstrFormats.td
  7. +1 −0 lib/Target/SystemZ/SystemZInstrInfo.cpp
  8. +60 −2 lib/Target/SystemZ/SystemZInstrInfo.td
  9. +4 −0 lib/Target/SystemZ/SystemZInstrSystem.td
  10. +158 −0 lib/Target/SystemZ/SystemZInstrVector.td
  11. +20 −0 lib/Target/SystemZ/SystemZOperators.td
  12. +7 −0 lib/Target/SystemZ/SystemZPatterns.td
  13. +3 −0 lib/Target/SystemZ/SystemZProcessors.td
  14. +2 −1 lib/Target/SystemZ/SystemZSchedule.td
  15. +1,573 −0 lib/Target/SystemZ/SystemZScheduleZ14.td
  16. +4 −0 lib/Target/SystemZ/SystemZSubtarget.cpp
  17. +34 −0 lib/Target/SystemZ/SystemZSubtarget.h
  18. +56 −0 test/CodeGen/SystemZ/branch-11.ll
  19. +23 −0 test/CodeGen/SystemZ/fp-mul-10.ll
  20. +95 −0 test/CodeGen/SystemZ/int-add-17.ll
  21. +95 −0 test/CodeGen/SystemZ/int-mul-09.ll
  22. +165 −0 test/CodeGen/SystemZ/int-mul-10.ll
  23. +32 −0 test/CodeGen/SystemZ/int-mul-11.ll
  24. +95 −0 test/CodeGen/SystemZ/int-sub-10.ll
  25. +47 −0 test/CodeGen/SystemZ/vec-and-04.ll
  26. +45 −0 test/CodeGen/SystemZ/vec-ctpop-02.ll
  27. 0 test/CodeGen/SystemZ/{vec-intrinsics.ll → vec-intrinsics-01.ll}
  28. +212 −0 test/CodeGen/SystemZ/vec-intrinsics-02.ll
  29. +58 −0 test/CodeGen/SystemZ/vec-max-05.ll
  30. +58 −0 test/CodeGen/SystemZ/vec-min-05.ll
  31. +24 −0 test/CodeGen/SystemZ/vec-move-18.ll
  32. +32 −0 test/CodeGen/SystemZ/vec-mul-05.ll
  33. +91 −0 test/CodeGen/SystemZ/vec-or-03.ll
  34. +47 −0 test/CodeGen/SystemZ/vec-xor-02.ll
  35. +1,594 −0 test/MC/Disassembler/SystemZ/insns-z14.txt
  36. +344 −0 test/MC/SystemZ/insn-bad-z13.s
  37. +562 −0 test/MC/SystemZ/insn-bad-z14.s
  38. +1,282 −0 test/MC/SystemZ/insn-good-z14.s
@@ -373,6 +373,33 @@ let TargetPrefix = "s390" in {
def int_s390_vfidb : Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
// Instructions from the Vector Enhancements Facility 1
def int_s390_vbperm : SystemZBinaryConv<"vbperm", llvm_v2i64_ty,
llvm_v16i8_ty>;
def int_s390_vmslg : GCCBuiltin<"__builtin_s390_vmslg">,
Intrinsic<[llvm_v16i8_ty],
[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v16i8_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_s390_vfmaxdb : Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_s390_vfmindb : Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty],
[IntrNoMem]>;
// Instructions from the Vector Packed Decimal Facility
def int_s390_vlrl : GCCBuiltin<"__builtin_s390_vlrl">,
Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty],
[IntrReadMem, IntrArgMemOnly]>;
def int_s390_vstrl : GCCBuiltin<"__builtin_s390_vstrl">,
Intrinsic<[], [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty],
// In fact write-only but there's no property
// for that.
[IntrArgMemOnly]>;
}
//===----------------------------------------------------------------------===//
View
@@ -250,6 +250,8 @@ StringRef sys::detail::getHostCPUNameForS390x(
Pos += sizeof("machine = ") - 1;
unsigned int Id;
if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
if (Id >= 3906 && HaveVectorSupport)
return "z14";
if (Id >= 2964 && HaveVectorSupport)
return "z13";
if (Id >= 2827)
@@ -187,6 +187,57 @@ def Arch11NewFeatures : SystemZFeatureList<[
FeatureVector
]>;
//===----------------------------------------------------------------------===//
//
// New features added in the Twelvth Edition of the z/Architecture
//
//===----------------------------------------------------------------------===//
def FeatureMiscellaneousExtensions2 : SystemZFeature<
"miscellaneous-extensions-2", "MiscellaneousExtensions2",
"Assume that the miscellaneous-extensions facility 2 is installed"
>;
def FeatureGuardedStorage : SystemZFeature<
"guarded-storage", "GuardedStorage",
"Assume that the guarded-storage facility is installed"
>;
def FeatureMessageSecurityAssist7 : SystemZFeature<
"message-security-assist-extension7", "MessageSecurityAssist7",
"Assume that the message-security-assist extension facility 7 is installed"
>;
def FeatureMessageSecurityAssist8 : SystemZFeature<
"message-security-assist-extension8", "MessageSecurityAssist8",
"Assume that the message-security-assist extension facility 8 is installed"
>;
def FeatureVectorEnhancements1 : SystemZFeature<
"vector-enhancements-1", "VectorEnhancements1",
"Assume that the vector enhancements facility 1 is installed"
>;
def FeatureVectorPackedDecimal : SystemZFeature<
"vector-packed-decimal", "VectorPackedDecimal",
"Assume that the vector packed decimal facility is installed"
>;
def FeatureInsertReferenceBitsMultiple : SystemZFeature<
"insert-reference-bits-multiple", "InsertReferenceBitsMultiple",
"Assume that the insert-reference-bits-multiple facility is installed"
>;
def Arch12NewFeatures : SystemZFeatureList<[
FeatureMiscellaneousExtensions2,
FeatureGuardedStorage,
FeatureMessageSecurityAssist7,
FeatureMessageSecurityAssist8,
FeatureVectorEnhancements1,
FeatureVectorPackedDecimal,
FeatureInsertReferenceBitsMultiple
]>;
//===----------------------------------------------------------------------===//
//
// Cumulative supported and unsupported feature sets
@@ -201,9 +252,13 @@ def Arch10SupportedFeatures
: SystemZFeatureAdd<Arch9SupportedFeatures.List, Arch10NewFeatures.List>;
def Arch11SupportedFeatures
: SystemZFeatureAdd<Arch10SupportedFeatures.List, Arch11NewFeatures.List>;
def Arch12SupportedFeatures
: SystemZFeatureAdd<Arch11SupportedFeatures.List, Arch12NewFeatures.List>;
def Arch11UnsupportedFeatures
def Arch12UnsupportedFeatures
: SystemZFeatureList<[]>;
def Arch11UnsupportedFeatures
: SystemZFeatureAdd<Arch12UnsupportedFeatures.List, Arch12NewFeatures.List>;
def Arch10UnsupportedFeatures
: SystemZFeatureAdd<Arch11UnsupportedFeatures.List, Arch11NewFeatures.List>;
def Arch9UnsupportedFeatures
@@ -316,7 +316,10 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::AND, VT, Legal);
setOperationAction(ISD::OR, VT, Legal);
setOperationAction(ISD::XOR, VT, Legal);
setOperationAction(ISD::CTPOP, VT, Custom);
if (Subtarget.hasVectorEnhancements1())
setOperationAction(ISD::CTPOP, VT, Legal);
else
setOperationAction(ISD::CTPOP, VT, Custom);
setOperationAction(ISD::CTTZ, VT, Legal);
setOperationAction(ISD::CTLZ, VT, Legal);
@@ -414,6 +417,19 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
}
// The vector enhancements facility 1 has instructions for these.
if (Subtarget.hasVectorEnhancements1()) {
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXNAN, MVT::f64, Legal);
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMINNAN, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal);
setOperationAction(ISD::FMAXNAN, MVT::v2f64, Legal);
setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
setOperationAction(ISD::FMINNAN, MVT::v2f64, Legal);
}
// We have fused multiply-addition for f32 and f64 but not f128.
setOperationAction(ISD::FMA, MVT::f32, Legal);
setOperationAction(ISD::FMA, MVT::f64, Legal);
@@ -2960,6 +2976,12 @@ SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
// We define this so that it can be used for constant division.
lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
Op.getOperand(1), Ops[1], Ops[0]);
else if (Subtarget.hasMiscellaneousExtensions2())
// SystemZISD::SMUL_LOHI returns the low result in the odd register and
// the high result in the even register. ISD::SMUL_LOHI is defined to
// return the low half first, so the results are in reverse order.
lowerGR128Binary(DAG, DL, VT, SystemZISD::SMUL_LOHI,
Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
else {
// Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
//
@@ -4658,6 +4680,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
OPCODE(SELECT_CCMASK);
OPCODE(ADJDYNALLOC);
OPCODE(POPCNT);
OPCODE(SMUL_LOHI);
OPCODE(UMUL_LOHI);
OPCODE(SDIVREM);
OPCODE(UDIVREM);
@@ -88,6 +88,7 @@ enum NodeType : unsigned {
// Wrappers around the ISD opcodes of the same name. The output is GR128.
// Input operands may be GR64 or GR32, depending on the instruction.
SMUL_LOHI,
UMUL_LOHI,
SDIVREM,
UDIVREM,
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