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Add LLVM support for Swift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
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bob-wilson committed Sep 29, 2012
1 parent 154418c commit eb1641d54a7eda7717304bc4d55d059208d8ebed
Showing with 2,038 additions and 99 deletions.
  1. +4 −1 include/llvm/Object/MachOFormat.h
  2. +19 −3 lib/Target/ARM/ARM.td
  3. +458 −9 lib/Target/ARM/ARMBaseInstrInfo.cpp
  4. +7 −0 lib/Target/ARM/ARMBaseInstrInfo.h
  5. +13 −8 lib/Target/ARM/ARMISelDAGToDAG.cpp
  6. +3 −3 lib/Target/ARM/ARMISelLowering.cpp
  7. +21 −0 lib/Target/ARM/ARMInstrFormats.td
  8. +49 −19 lib/Target/ARM/ARMInstrInfo.td
  9. +28 −4 lib/Target/ARM/ARMInstrNEON.td
  10. +14 −12 lib/Target/ARM/ARMInstrThumb2.td
  11. +3 −1 lib/Target/ARM/ARMInstrVFP.td
  12. +7 −2 lib/Target/ARM/ARMRegisterInfo.td
  13. +2 −0 lib/Target/ARM/ARMSchedule.td
  14. +1,085 −0 lib/Target/ARM/ARMScheduleSwift.td
  15. +6 −0 lib/Target/ARM/ARMSubtarget.cpp
  16. +11 −1 lib/Target/ARM/ARMSubtarget.h
  17. +9 −0 lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  18. +8 −0 lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  19. +67 −1 lib/Target/ARM/MLxExpansionPass.cpp
  20. +1 −1 test/CodeGen/ARM/2010-12-07-PEIBug.ll
  21. +11 −0 test/CodeGen/ARM/2012-05-04-vmov.ll
  22. +14 −0 test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll
  23. +1 −0 test/CodeGen/ARM/avoid-cpsr-rmw.ll
  24. +39 −0 test/CodeGen/ARM/call-noret.ll
  25. +16 −1 test/CodeGen/ARM/div.ll
  26. +2 −2 test/CodeGen/ARM/fabss.ll
  27. +4 −4 test/CodeGen/ARM/fadds.ll
  28. +4 −4 test/CodeGen/ARM/fdivs.ll
  29. +4 −4 test/CodeGen/ARM/fmuls.ll
  30. +2 −2 test/CodeGen/ARM/fp_convert.ll
  31. +3 −3 test/CodeGen/ARM/fsubs.ll
  32. +8 −4 test/CodeGen/ARM/ifcvt1.ll
  33. +15 −0 test/CodeGen/ARM/ifcvt12.ll
  34. +9 −3 test/CodeGen/ARM/ifcvt5.ll
  35. +1 −0 test/CodeGen/ARM/ldr_post.ll
  36. +1 −0 test/CodeGen/ARM/ldr_pre.ll
  37. +12 −0 test/CodeGen/ARM/mls.ll
  38. +22 −0 test/CodeGen/ARM/neon-fma.ll
  39. +27 −0 test/CodeGen/ARM/neon_ld2.ll
  40. +2 −2 test/CodeGen/ARM/opt-shuff-tstore.ll
  41. +2 −2 test/CodeGen/ARM/subreg-remat.ll
  42. +3 −3 test/CodeGen/Thumb2/cortex-fp.ll
  43. +10 −0 test/CodeGen/Thumb2/div.ll
  44. +7 −0 test/CodeGen/Thumb2/thumb2-mla.ll
  45. +4 −0 test/CodeGen/Thumb2/thumb2-smla.ll
@@ -61,7 +61,10 @@ namespace mach {
CSARM_V6 = 6,
CSARM_V5TEJ = 7,
CSARM_XSCALE = 8,
CSARM_V7 = 9
CSARM_V7 = 9,
CSARM_V7F = 10,
CSARM_V7S = 11,
CSARM_V7K = 12
};
/// \brief PowerPC Machine Subtypes.
View
@@ -32,9 +32,6 @@ def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
"Enable VFP3 instructions",
[FeatureVFP2]>;
def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
"Enable VFP4 instructions",
[FeatureVFP3]>;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable NEON instructions",
[FeatureVFP3]>;
@@ -44,10 +41,16 @@ def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
"Does not support ARM mode execution">;
def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
"Enable half-precision floating point">;
def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
"Enable VFP4 instructions",
[FeatureVFP3, FeatureFP16]>;
def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
"Restrict VFP3 to 16 double registers">;
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
"Enable divide instructions">;
def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
"HasHardwareDivideInARM", "true",
"Enable divide instructions in ARM mode">;
def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
"Enable Thumb2 extract and pack instructions">;
def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
@@ -139,6 +142,13 @@ def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
[FeatureVMLxForwarding,
FeatureT2XtPk, FeatureFP16,
FeatureAvoidPartialCPSR]>;
def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
"Swift ARM processors",
[FeatureNEONForFP, FeatureT2XtPk,
FeatureVFP4, FeatureMP, FeatureHWDiv,
FeatureHWDivARM, FeatureAvoidPartialCPSR,
FeatureHasSlowFPVMLx]>;
// FIXME: It has not been determined if A15 has these features.
def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
"Cortex-A15 ARM processors",
@@ -236,6 +246,12 @@ def : ProcNoItin<"cortex-m4", [HasV7Ops,
FeatureT2XtPk, FeatureVFP4,
FeatureVFPOnlySP, FeatureMClass]>;
// Swift uArch Processors.
def : ProcessorModel<"swift", SwiftModel,
[ProcSwift, HasV7Ops, FeatureNEON,
FeatureDB, FeatureDSPThumb2,
FeatureHasRAS]>;
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
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