From 1b09056a3aa850e3dd04a4dcf33f5bf6e0e65d3c Mon Sep 17 00:00:00 2001
From: AmrDeveloper <amr96@programmer.net>
Date: Tue, 11 Nov 2025 19:08:26 +0100
Subject: [PATCH] [CIR] Backport logical not for VectorType

---
 clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp |  8 ++++++-
 clang/test/CIR/CodeGen/vectype.cpp         | 25 ++++++++++++++++++++++
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
index 2ae8c0d10703..ea7707633f4b 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
@@ -2062,7 +2062,13 @@ mlir::Value ScalarExprEmitter::VisitUnaryLNot(const UnaryOperator *E) {
   if (E->getType()->isVectorType() &&
       E->getType()->castAs<VectorType>()->getVectorKind() ==
           VectorKind::Generic) {
-    llvm_unreachable("NYI");
+    mlir::Value oper = Visit(E->getSubExpr());
+    mlir::Location loc = CGF.getLoc(E->getExprLoc());
+    auto operVecTy = mlir::cast<cir::VectorType>(oper.getType());
+    auto exprVecTy = mlir::cast<cir::VectorType>(CGF.convertType(E->getType()));
+    mlir::Value zeroVec = Builder.getNullValue(operVecTy, loc);
+    return cir::VecCmpOp::create(Builder, loc, exprVecTy, cir::CmpOpKind::eq,
+                                 oper, zeroVec);
   }
 
   // Compare operand to zero.
diff --git a/clang/test/CIR/CodeGen/vectype.cpp b/clang/test/CIR/CodeGen/vectype.cpp
index 3b449b694da0..1f2defbc15cd 100644
--- a/clang/test/CIR/CodeGen/vectype.cpp
+++ b/clang/test/CIR/CodeGen/vectype.cpp
@@ -5,6 +5,7 @@ typedef unsigned int uvi4 __attribute__((vector_size(16)));
 typedef double vd2 __attribute__((vector_size(16)));
 typedef long long vll2 __attribute__((vector_size(16)));
 typedef unsigned short vus2 __attribute__((vector_size(4)));
+typedef float vf4 __attribute__((vector_size(16)));
 
 vi4 vec_a;
 // CHECK: cir.global external @[[VEC_A:.*]] = #cir.zero : !cir.vector<!s32i x 4>
@@ -221,3 +222,27 @@ void vector_integers_shifts_test() {
   uvi4 shr = b >> a;
   // CHECK: %{{[0-9]+}} = cir.shift(right, %{{[0-9]+}} : !cir.vector<!u32i x 4>, %{{[0-9]+}} : !cir.vector<!s32i x 4>) -> !cir.vector<!u32i x 4>
 }
+
+void logical_not() {
+   vi4 a;
+   vi4 b = !a;
+}
+
+// CHECK: %[[A_ADDR:.*]] = cir.alloca !cir.vector<!s32i x 4>, !cir.ptr<!cir.vector<!s32i x 4>>, ["a"]
+// CHECK: %[[B_ADDR:.*]] = cir.alloca !cir.vector<!s32i x 4>, !cir.ptr<!cir.vector<!s32i x 4>>, ["b", init]
+// CHECK: %[[TMP_A:.*]] = cir.load{{.*}}) %[[A_ADDR]] : !cir.ptr<!cir.vector<!s32i x 4>>, !cir.vector<!s32i x 4>
+// CHECK: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<!s32i x 4>
+// CHECK: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<!s32i x 4>, !cir.vector<!s32i x 4>
+// CHECK: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<!s32i x 4>, !cir.ptr<!cir.vector<!s32i x 4>>
+
+void logical_not_float() {
+  vf4 a;
+  vi4 b = !a;
+}
+
+// CHECK: %[[A_ADDR:.*]] = cir.alloca !cir.vector<!cir.float x 4>, !cir.ptr<!cir.vector<!cir.float x 4>>, ["a"]
+// CHECK: %[[B_ADDR:.*]] = cir.alloca !cir.vector<!s32i x 4>, !cir.ptr<!cir.vector<!s32i x 4>>, ["b", init]
+// CHECK: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<!cir.float x 4>>, !cir.vector<!cir.float x 4>
+// CHECK: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<!cir.float x 4>
+// CHECK: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<!cir.float x 4>, !cir.vector<!s32i x 4>
+// CHECK: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<!s32i x 4>, !cir.ptr<!cir.vector<!s32i x 4>>