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X86Disassembler.cpp
2339 lines (2119 loc) · 79.8 KB
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X86Disassembler.cpp
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//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file is part of the X86 Disassembler.
// It contains code to translate the data produced by the decoder into
// MCInsts.
//
//
// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
// 64-bit X86 instruction sets. The main decode sequence for an assembly
// instruction in this disassembler is:
//
// 1. Read the prefix bytes and determine the attributes of the instruction.
// These attributes, recorded in enum attributeBits
// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
// provides a mapping from bitmasks to contexts, which are represented by
// enum InstructionContext (ibid.).
//
// 2. Read the opcode, and determine what kind of opcode it is. The
// disassembler distinguishes four kinds of opcodes, which are enumerated in
// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
//
// 3. Depending on the opcode type, look in one of four ClassDecision structures
// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
// a ModRMDecision (ibid.).
//
// 4. Some instructions, such as escape opcodes or extended opcodes, or even
// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
// ModR/M byte to complete decode. The ModRMDecision's type is an entry from
// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
// ModR/M byte is required and how to interpret it.
//
// 5. After resolving the ModRMDecision, the disassembler has a unique ID
// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
// meanings of its operands.
//
// 6. For each operand, its encoding is an entry from OperandEncoding
// (X86DisassemblerDecoderCommon.h) and its type is an entry from
// OperandType (ibid.). The encoding indicates how to read it from the
// instruction; the type indicates how to interpret the value once it has
// been read. For example, a register operand could be stored in the R/M
// field of the ModR/M byte, the REG field of the ModR/M byte, or added to
// the main opcode. This is orthogonal from its meaning (an GPR or an XMM
// register, for instance). Given this information, the operands can be
// extracted and interpreted.
//
// 7. As the last step, the disassembler translates the instruction information
// and operands into a format understandable by the client - in this case, an
// MCInst for use by the MC infrastructure.
//
// The disassembler is broken broadly into two parts: the table emitter that
// emits the instruction decode tables discussed above during compilation, and
// the disassembler itself. The table emitter is documented in more detail in
// utils/TableGen/X86DisassemblerEmitter.h.
//
// X86Disassembler.cpp contains the code responsible for step 7, and for
// invoking the decoder to execute steps 1-6.
// X86DisassemblerDecoderCommon.h contains the definitions needed by both the
// table emitter and the disassembler.
// X86DisassemblerDecoder.h contains the public interface of the decoder,
// factored out into C for possible use by other projects.
// X86DisassemblerDecoder.c contains the source code of the decoder, which is
// responsible for steps 1-6.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/X86BaseInfo.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "TargetInfo/X86TargetInfo.h"
#include "X86DisassemblerDecoder.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
using namespace llvm::X86Disassembler;
#define DEBUG_TYPE "x86-disassembler"
#define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s);
// Specifies whether a ModR/M byte is needed and (if so) which
// instruction each possible value of the ModR/M byte corresponds to. Once
// this information is known, we have narrowed down to a single instruction.
struct ModRMDecision {
uint8_t modrm_type;
uint16_t instructionIDs;
};
// Specifies which set of ModR/M->instruction tables to look at
// given a particular opcode.
struct OpcodeDecision {
ModRMDecision modRMDecisions[256];
};
// Specifies which opcode->instruction tables to look at given
// a particular context (set of attributes). Since there are many possible
// contexts, the decoder first uses CONTEXTS_SYM to determine which context
// applies given a specific set of attributes. Hence there are only IC_max
// entries in this table, rather than 2^(ATTR_max).
struct ContextDecision {
OpcodeDecision opcodeDecisions[IC_max];
};
#include "X86GenDisassemblerTables.inc"
static InstrUID decode(OpcodeType type, InstructionContext insnContext,
uint8_t opcode, uint8_t modRM) {
const struct ModRMDecision *dec;
switch (type) {
case ONEBYTE:
dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case TWOBYTE:
dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case THREEBYTE_38:
dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case THREEBYTE_3A:
dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case XOP8_MAP:
dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case XOP9_MAP:
dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case XOPA_MAP:
dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case THREEDNOW_MAP:
dec =
&THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
}
switch (dec->modrm_type) {
default:
llvm_unreachable("Corrupt table! Unknown modrm_type");
return 0;
case MODRM_ONEENTRY:
return modRMTable[dec->instructionIDs];
case MODRM_SPLITRM:
if (modFromModRM(modRM) == 0x3)
return modRMTable[dec->instructionIDs + 1];
return modRMTable[dec->instructionIDs];
case MODRM_SPLITREG:
if (modFromModRM(modRM) == 0x3)
return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8];
return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
case MODRM_SPLITMISC:
if (modFromModRM(modRM) == 0x3)
return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8];
return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
case MODRM_FULL:
return modRMTable[dec->instructionIDs + modRM];
}
}
static bool peek(struct InternalInstruction *insn, uint8_t &byte) {
uint64_t offset = insn->readerCursor - insn->startLocation;
if (offset >= insn->bytes.size())
return true;
byte = insn->bytes[offset];
return false;
}
template <typename T> static bool consume(InternalInstruction *insn, T &ptr) {
auto r = insn->bytes;
uint64_t offset = insn->readerCursor - insn->startLocation;
if (offset + sizeof(T) > r.size())
return true;
T ret = 0;
for (unsigned i = 0; i < sizeof(T); ++i)
ret |= (uint64_t)r[offset + i] << (i * 8);
ptr = ret;
insn->readerCursor += sizeof(T);
return false;
}
static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f;
}
// Consumes all of an instruction's prefix bytes, and marks the
// instruction as having them. Also sets the instruction's default operand,
// address, and other relevant data sizes to report operands correctly.
static int readPrefixes(struct InternalInstruction *insn) {
bool isPrefix = true;
uint8_t byte = 0;
uint8_t nextByte;
LLVM_DEBUG(dbgs() << "readPrefixes()");
while (isPrefix) {
// If we fail reading prefixes, just stop here and let the opcode reader
// deal with it.
if (consume(insn, byte))
break;
// If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
// break and let it be disassembled as a normal "instruction".
if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
break;
if ((byte == 0xf2 || byte == 0xf3) && !peek(insn, nextByte)) {
// If the byte is 0xf2 or 0xf3, and any of the following conditions are
// met:
// - it is followed by a LOCK (0xf0) prefix
// - it is followed by an xchg instruction
// then it should be disassembled as a xacquire/xrelease not repne/rep.
if (((nextByte == 0xf0) ||
((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
insn->xAcquireRelease = true;
if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
break;
}
// Also if the byte is 0xf3, and the following condition is met:
// - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
// "mov mem, imm" (opcode 0xc6/0xc7) instructions.
// then it should be disassembled as an xrelease not rep.
if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
nextByte == 0xc6 || nextByte == 0xc7)) {
insn->xAcquireRelease = true;
break;
}
if (isREX(insn, nextByte)) {
uint8_t nnextByte;
// Go to REX prefix after the current one
if (consume(insn, nnextByte))
return -1;
// We should be able to read next byte after REX prefix
if (peek(insn, nnextByte))
return -1;
--insn->readerCursor;
}
}
switch (byte) {
case 0xf0: // LOCK
insn->hasLockPrefix = true;
break;
case 0xf2: // REPNE/REPNZ
case 0xf3: { // REP or REPE/REPZ
uint8_t nextByte;
if (peek(insn, nextByte))
break;
// TODO:
// 1. There could be several 0x66
// 2. if (nextByte == 0x66) and nextNextByte != 0x0f then
// it's not mandatory prefix
// 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
// 0x0f exactly after it to be mandatory prefix
if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
// The last of 0xf2 /0xf3 is mandatory prefix
insn->mandatoryPrefix = byte;
insn->repeatPrefix = byte;
break;
}
case 0x2e: // CS segment override -OR- Branch not taken
insn->segmentOverride = SEG_OVERRIDE_CS;
break;
case 0x36: // SS segment override -OR- Branch taken
insn->segmentOverride = SEG_OVERRIDE_SS;
break;
case 0x3e: // DS segment override
insn->segmentOverride = SEG_OVERRIDE_DS;
break;
case 0x26: // ES segment override
insn->segmentOverride = SEG_OVERRIDE_ES;
break;
case 0x64: // FS segment override
insn->segmentOverride = SEG_OVERRIDE_FS;
break;
case 0x65: // GS segment override
insn->segmentOverride = SEG_OVERRIDE_GS;
break;
case 0x66: { // Operand-size override {
uint8_t nextByte;
insn->hasOpSize = true;
if (peek(insn, nextByte))
break;
// 0x66 can't overwrite existing mandatory prefix and should be ignored
if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
insn->mandatoryPrefix = byte;
break;
}
case 0x67: // Address-size override
insn->hasAdSize = true;
break;
default: // Not a prefix byte
isPrefix = false;
break;
}
if (isPrefix)
LLVM_DEBUG(dbgs() << format("Found prefix 0x%hhx", byte));
}
insn->vectorExtensionType = TYPE_NO_VEX_XOP;
if (byte == 0x62) {
uint8_t byte1, byte2;
if (consume(insn, byte1)) {
LLVM_DEBUG(dbgs() << "Couldn't read second byte of EVEX prefix");
return -1;
}
if (peek(insn, byte2)) {
LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
return -1;
}
if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
insn->vectorExtensionType = TYPE_EVEX;
} else {
--insn->readerCursor; // unconsume byte1
--insn->readerCursor; // unconsume byte
}
if (insn->vectorExtensionType == TYPE_EVEX) {
insn->vectorExtensionPrefix[0] = byte;
insn->vectorExtensionPrefix[1] = byte1;
if (consume(insn, insn->vectorExtensionPrefix[2])) {
LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
return -1;
}
if (consume(insn, insn->vectorExtensionPrefix[3])) {
LLVM_DEBUG(dbgs() << "Couldn't read fourth byte of EVEX prefix");
return -1;
}
// We simulate the REX prefix for simplicity's sake
if (insn->mode == MODE_64BIT) {
insn->rexPrefix = 0x40 |
(wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) |
(rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) |
(xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) |
(bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
}
LLVM_DEBUG(
dbgs() << format(
"Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]));
}
} else if (byte == 0xc4) {
uint8_t byte1;
if (peek(insn, byte1)) {
LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
return -1;
}
if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
insn->vectorExtensionType = TYPE_VEX_3B;
else
--insn->readerCursor;
if (insn->vectorExtensionType == TYPE_VEX_3B) {
insn->vectorExtensionPrefix[0] = byte;
consume(insn, insn->vectorExtensionPrefix[1]);
consume(insn, insn->vectorExtensionPrefix[2]);
// We simulate the REX prefix for simplicity's sake
if (insn->mode == MODE_64BIT)
insn->rexPrefix = 0x40 |
(wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) |
(rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) |
(xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) |
(bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
insn->vectorExtensionPrefix[0],
insn->vectorExtensionPrefix[1],
insn->vectorExtensionPrefix[2]));
}
} else if (byte == 0xc5) {
uint8_t byte1;
if (peek(insn, byte1)) {
LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
return -1;
}
if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
insn->vectorExtensionType = TYPE_VEX_2B;
else
--insn->readerCursor;
if (insn->vectorExtensionType == TYPE_VEX_2B) {
insn->vectorExtensionPrefix[0] = byte;
consume(insn, insn->vectorExtensionPrefix[1]);
if (insn->mode == MODE_64BIT)
insn->rexPrefix =
0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
default:
break;
case VEX_PREFIX_66:
insn->hasOpSize = true;
break;
}
LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx",
insn->vectorExtensionPrefix[0],
insn->vectorExtensionPrefix[1]));
}
} else if (byte == 0x8f) {
uint8_t byte1;
if (peek(insn, byte1)) {
LLVM_DEBUG(dbgs() << "Couldn't read second byte of XOP");
return -1;
}
if ((byte1 & 0x38) != 0x0) // 0 in these 3 bits is a POP instruction.
insn->vectorExtensionType = TYPE_XOP;
else
--insn->readerCursor;
if (insn->vectorExtensionType == TYPE_XOP) {
insn->vectorExtensionPrefix[0] = byte;
consume(insn, insn->vectorExtensionPrefix[1]);
consume(insn, insn->vectorExtensionPrefix[2]);
// We simulate the REX prefix for simplicity's sake
if (insn->mode == MODE_64BIT)
insn->rexPrefix = 0x40 |
(wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) |
(rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) |
(xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) |
(bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
default:
break;
case VEX_PREFIX_66:
insn->hasOpSize = true;
break;
}
LLVM_DEBUG(dbgs() << format("Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
insn->vectorExtensionPrefix[0],
insn->vectorExtensionPrefix[1],
insn->vectorExtensionPrefix[2]));
}
} else if (isREX(insn, byte)) {
if (peek(insn, nextByte))
return -1;
insn->rexPrefix = byte;
LLVM_DEBUG(dbgs() << format("Found REX prefix 0x%hhx", byte));
} else
--insn->readerCursor;
if (insn->mode == MODE_16BIT) {
insn->registerSize = (insn->hasOpSize ? 4 : 2);
insn->addressSize = (insn->hasAdSize ? 4 : 2);
insn->displacementSize = (insn->hasAdSize ? 4 : 2);
insn->immediateSize = (insn->hasOpSize ? 4 : 2);
} else if (insn->mode == MODE_32BIT) {
insn->registerSize = (insn->hasOpSize ? 2 : 4);
insn->addressSize = (insn->hasAdSize ? 2 : 4);
insn->displacementSize = (insn->hasAdSize ? 2 : 4);
insn->immediateSize = (insn->hasOpSize ? 2 : 4);
} else if (insn->mode == MODE_64BIT) {
if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
insn->registerSize = 8;
insn->addressSize = (insn->hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
} else {
insn->registerSize = (insn->hasOpSize ? 2 : 4);
insn->addressSize = (insn->hasAdSize ? 4 : 8);
insn->displacementSize = (insn->hasOpSize ? 2 : 4);
insn->immediateSize = (insn->hasOpSize ? 2 : 4);
}
}
return 0;
}
// Consumes the SIB byte to determine addressing information.
static int readSIB(struct InternalInstruction *insn) {
SIBBase sibBaseBase = SIB_BASE_NONE;
uint8_t index, base;
LLVM_DEBUG(dbgs() << "readSIB()");
switch (insn->addressSize) {
case 2:
default:
llvm_unreachable("SIB-based addressing doesn't work in 16-bit mode");
case 4:
insn->sibIndexBase = SIB_INDEX_EAX;
sibBaseBase = SIB_BASE_EAX;
break;
case 8:
insn->sibIndexBase = SIB_INDEX_RAX;
sibBaseBase = SIB_BASE_RAX;
break;
}
if (consume(insn, insn->sib))
return -1;
index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
if (index == 0x4) {
insn->sibIndex = SIB_INDEX_NONE;
} else {
insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
}
insn->sibScale = 1 << scaleFromSIB(insn->sib);
base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
switch (base) {
case 0x5:
case 0xd:
switch (modFromModRM(insn->modRM)) {
case 0x0:
insn->eaDisplacement = EA_DISP_32;
insn->sibBase = SIB_BASE_NONE;
break;
case 0x1:
insn->eaDisplacement = EA_DISP_8;
insn->sibBase = (SIBBase)(sibBaseBase + base);
break;
case 0x2:
insn->eaDisplacement = EA_DISP_32;
insn->sibBase = (SIBBase)(sibBaseBase + base);
break;
default:
llvm_unreachable("Cannot have Mod = 0b11 and a SIB byte");
}
break;
default:
insn->sibBase = (SIBBase)(sibBaseBase + base);
break;
}
return 0;
}
static int readDisplacement(struct InternalInstruction *insn) {
int8_t d8;
int16_t d16;
int32_t d32;
LLVM_DEBUG(dbgs() << "readDisplacement()");
insn->displacementOffset = insn->readerCursor - insn->startLocation;
switch (insn->eaDisplacement) {
case EA_DISP_NONE:
break;
case EA_DISP_8:
if (consume(insn, d8))
return -1;
insn->displacement = d8;
break;
case EA_DISP_16:
if (consume(insn, d16))
return -1;
insn->displacement = d16;
break;
case EA_DISP_32:
if (consume(insn, d32))
return -1;
insn->displacement = d32;
break;
}
return 0;
}
// Consumes all addressing information (ModR/M byte, SIB byte, and displacement.
static int readModRM(struct InternalInstruction *insn) {
uint8_t mod, rm, reg, evexrm;
LLVM_DEBUG(dbgs() << "readModRM()");
if (insn->consumedModRM)
return 0;
if (consume(insn, insn->modRM))
return -1;
insn->consumedModRM = true;
mod = modFromModRM(insn->modRM);
rm = rmFromModRM(insn->modRM);
reg = regFromModRM(insn->modRM);
// This goes by insn->registerSize to pick the correct register, which messes
// up if we're using (say) XMM or 8-bit register operands. That gets fixed in
// fixupReg().
switch (insn->registerSize) {
case 2:
insn->regBase = MODRM_REG_AX;
insn->eaRegBase = EA_REG_AX;
break;
case 4:
insn->regBase = MODRM_REG_EAX;
insn->eaRegBase = EA_REG_EAX;
break;
case 8:
insn->regBase = MODRM_REG_RAX;
insn->eaRegBase = EA_REG_RAX;
break;
}
reg |= rFromREX(insn->rexPrefix) << 3;
rm |= bFromREX(insn->rexPrefix) << 3;
evexrm = 0;
if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) {
reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
evexrm = xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
}
insn->reg = (Reg)(insn->regBase + reg);
switch (insn->addressSize) {
case 2: {
EABase eaBaseBase = EA_BASE_BX_SI;
switch (mod) {
case 0x0:
if (rm == 0x6) {
insn->eaBase = EA_BASE_NONE;
insn->eaDisplacement = EA_DISP_16;
if (readDisplacement(insn))
return -1;
} else {
insn->eaBase = (EABase)(eaBaseBase + rm);
insn->eaDisplacement = EA_DISP_NONE;
}
break;
case 0x1:
insn->eaBase = (EABase)(eaBaseBase + rm);
insn->eaDisplacement = EA_DISP_8;
insn->displacementSize = 1;
if (readDisplacement(insn))
return -1;
break;
case 0x2:
insn->eaBase = (EABase)(eaBaseBase + rm);
insn->eaDisplacement = EA_DISP_16;
if (readDisplacement(insn))
return -1;
break;
case 0x3:
insn->eaBase = (EABase)(insn->eaRegBase + rm);
if (readDisplacement(insn))
return -1;
break;
}
break;
}
case 4:
case 8: {
EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
switch (mod) {
case 0x0:
insn->eaDisplacement = EA_DISP_NONE; // readSIB may override this
// In determining whether RIP-relative mode is used (rm=5),
// or whether a SIB byte is present (rm=4),
// the extension bits (REX.b and EVEX.x) are ignored.
switch (rm & 7) {
case 0x4: // SIB byte is present
insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64);
if (readSIB(insn) || readDisplacement(insn))
return -1;
break;
case 0x5: // RIP-relative
insn->eaBase = EA_BASE_NONE;
insn->eaDisplacement = EA_DISP_32;
if (readDisplacement(insn))
return -1;
break;
default:
insn->eaBase = (EABase)(eaBaseBase + rm);
break;
}
break;
case 0x1:
insn->displacementSize = 1;
LLVM_FALLTHROUGH;
case 0x2:
insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
switch (rm & 7) {
case 0x4: // SIB byte is present
insn->eaBase = EA_BASE_sib;
if (readSIB(insn) || readDisplacement(insn))
return -1;
break;
default:
insn->eaBase = (EABase)(eaBaseBase + rm);
if (readDisplacement(insn))
return -1;
break;
}
break;
case 0x3:
insn->eaDisplacement = EA_DISP_NONE;
insn->eaBase = (EABase)(insn->eaRegBase + rm + evexrm);
break;
}
break;
}
} // switch (insn->addressSize)
return 0;
}
#define GENERIC_FIXUP_FUNC(name, base, prefix, mask) \
static uint16_t name(struct InternalInstruction *insn, OperandType type, \
uint8_t index, uint8_t *valid) { \
*valid = 1; \
switch (type) { \
default: \
debug("Unhandled register type"); \
*valid = 0; \
return 0; \
case TYPE_Rv: \
return base + index; \
case TYPE_R8: \
index &= mask; \
if (index > 0xf) \
*valid = 0; \
if (insn->rexPrefix && index >= 4 && index <= 7) { \
return prefix##_SPL + (index - 4); \
} else { \
return prefix##_AL + index; \
} \
case TYPE_R16: \
index &= mask; \
if (index > 0xf) \
*valid = 0; \
return prefix##_AX + index; \
case TYPE_R32: \
index &= mask; \
if (index > 0xf) \
*valid = 0; \
return prefix##_EAX + index; \
case TYPE_R64: \
index &= mask; \
if (index > 0xf) \
*valid = 0; \
return prefix##_RAX + index; \
case TYPE_ZMM: \
return prefix##_ZMM0 + index; \
case TYPE_YMM: \
return prefix##_YMM0 + index; \
case TYPE_XMM: \
return prefix##_XMM0 + index; \
case TYPE_VK: \
index &= 0xf; \
if (index > 7) \
*valid = 0; \
return prefix##_K0 + index; \
case TYPE_VK_PAIR: \
if (index > 7) \
*valid = 0; \
return prefix##_K0_K1 + (index / 2); \
case TYPE_MM64: \
return prefix##_MM0 + (index & 0x7); \
case TYPE_SEGMENTREG: \
if ((index & 7) > 5) \
*valid = 0; \
return prefix##_ES + (index & 7); \
case TYPE_DEBUGREG: \
return prefix##_DR0 + index; \
case TYPE_CONTROLREG: \
return prefix##_CR0 + index; \
case TYPE_BNDR: \
if (index > 3) \
*valid = 0; \
return prefix##_BND0 + index; \
case TYPE_MVSIBX: \
return prefix##_XMM0 + index; \
case TYPE_MVSIBY: \
return prefix##_YMM0 + index; \
case TYPE_MVSIBZ: \
return prefix##_ZMM0 + index; \
} \
}
// Consult an operand type to determine the meaning of the reg or R/M field. If
// the operand is an XMM operand, for example, an operand would be XMM0 instead
// of AX, which readModRM() would otherwise misinterpret it as.
//
// @param insn - The instruction containing the operand.
// @param type - The operand type.
// @param index - The existing value of the field as reported by readModRM().
// @param valid - The address of a uint8_t. The target is set to 1 if the
// field is valid for the register class; 0 if not.
// @return - The proper value.
GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG, 0x1f)
GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG, 0xf)
// Consult an operand specifier to determine which of the fixup*Value functions
// to use in correcting readModRM()'ss interpretation.
//
// @param insn - See fixup*Value().
// @param op - The operand specifier.
// @return - 0 if fixup was successful; -1 if the register returned was
// invalid for its class.
static int fixupReg(struct InternalInstruction *insn,
const struct OperandSpecifier *op) {
uint8_t valid;
LLVM_DEBUG(dbgs() << "fixupReg()");
switch ((OperandEncoding)op->encoding) {
default:
debug("Expected a REG or R/M encoding in fixupReg");
return -1;
case ENCODING_VVVV:
insn->vvvv =
(Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid);
if (!valid)
return -1;
break;
case ENCODING_REG:
insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type,
insn->reg - insn->regBase, &valid);
if (!valid)
return -1;
break;
CASE_ENCODING_RM:
if (insn->eaBase >= insn->eaRegBase) {
insn->eaBase = (EABase)fixupRMValue(
insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid);
if (!valid)
return -1;
}
break;
}
return 0;
}
// Read the opcode (except the ModR/M byte in the case of extended or escape
// opcodes).
static bool readOpcode(struct InternalInstruction *insn) {
uint8_t current;
LLVM_DEBUG(dbgs() << "readOpcode()");
insn->opcodeType = ONEBYTE;
if (insn->vectorExtensionType == TYPE_EVEX) {
switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
default:
LLVM_DEBUG(
dbgs() << format("Unhandled mm field for instruction (0x%hhx)",
mmFromEVEX2of4(insn->vectorExtensionPrefix[1])));
return true;
case VEX_LOB_0F:
insn->opcodeType = TWOBYTE;
return consume(insn, insn->opcode);
case VEX_LOB_0F38:
insn->opcodeType = THREEBYTE_38;
return consume(insn, insn->opcode);
case VEX_LOB_0F3A:
insn->opcodeType = THREEBYTE_3A;
return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
default:
LLVM_DEBUG(
dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])));
return true;
case VEX_LOB_0F:
insn->opcodeType = TWOBYTE;
return consume(insn, insn->opcode);
case VEX_LOB_0F38:
insn->opcodeType = THREEBYTE_38;
return consume(insn, insn->opcode);
case VEX_LOB_0F3A:
insn->opcodeType = THREEBYTE_3A;
return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_2B) {
insn->opcodeType = TWOBYTE;
return consume(insn, insn->opcode);
} else if (insn->vectorExtensionType == TYPE_XOP) {
switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
default:
LLVM_DEBUG(
dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])));
return true;
case XOP_MAP_SELECT_8:
insn->opcodeType = XOP8_MAP;
return consume(insn, insn->opcode);
case XOP_MAP_SELECT_9:
insn->opcodeType = XOP9_MAP;
return consume(insn, insn->opcode);
case XOP_MAP_SELECT_A:
insn->opcodeType = XOPA_MAP;
return consume(insn, insn->opcode);
}
}
if (consume(insn, current))
return true;
if (current == 0x0f) {
LLVM_DEBUG(
dbgs() << format("Found a two-byte escape prefix (0x%hhx)", current));
if (consume(insn, current))
return true;
if (current == 0x38) {
LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
current));
if (consume(insn, current))
return -1;
insn->opcodeType = THREEBYTE_38;
} else if (current == 0x3a) {
LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
current));
if (consume(insn, current))
return -1;
insn->opcodeType = THREEBYTE_3A;
} else if (current == 0x0f) {
LLVM_DEBUG(
dbgs() << format("Found a 3dnow escape prefix (0x%hhx)", current));
// Consume operands before the opcode to comply with the 3DNow encoding
if (readModRM(insn))
return true;
if (consume(insn, current))
return true;
insn->opcodeType = THREEDNOW_MAP;
} else {
LLVM_DEBUG(dbgs() << "Didn't find a three-byte escape prefix");
insn->opcodeType = TWOBYTE;
}
} else if (insn->mandatoryPrefix)
// The opcode with mandatory prefix must start with opcode escape.
// If not it's legacy repeat prefix
insn->mandatoryPrefix = 0;
// At this point we have consumed the full opcode.
// Anything we consume from here on must be unconsumed.
insn->opcode = current;
return false;
}
// Determine whether equiv is the 16-bit equivalent of orig (32-bit or 64-bit).
static bool is16BitEquivalent(const char *orig, const char *equiv) {
for (int i = 0;; i++) {
if (orig[i] == '\0' && equiv[i] == '\0')
return true;
if (orig[i] == '\0' || equiv[i] == '\0')
return false;
if (orig[i] != equiv[i]) {
if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
continue;
if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
continue;
if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
continue;
return false;
}
}
}
// Determine whether this instruction is a 64-bit instruction.
static bool is64Bit(const char *name) {
for (int i = 0;; ++i) {
if (name[i] == '\0')
return false;