From 0131498402acbae4cfb445a5a98fcf93b3a0e676 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 1 Mar 2021 15:29:56 -0500 Subject: [PATCH] GlobalISel: Remove dead code Generic code should probably not introduce G_INSERT/G_EXTRACT. The mirror unpackRegs should also be removed, but AMDGPU still has a use remaining which needs to be fixed. --- .../llvm/CodeGen/GlobalISel/CallLowering.h | 10 -------- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 25 ------------------- 2 files changed, 35 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h index 5e5530508a4ab..f876022b1697e 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -251,16 +251,6 @@ class CallLowering { SmallVectorImpl &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv) const; - /// Generate instructions for packing \p SrcRegs into one big register - /// corresponding to the aggregate type \p PackedTy. - /// - /// \param SrcRegs should contain one virtual register for each base type in - /// \p PackedTy, as returned by computeValueLLTs. - /// - /// \return The packed register. - Register packRegs(ArrayRef SrcRegs, Type *PackedTy, - MachineIRBuilder &MIRBuilder) const; - /// Generate instructions for unpacking \p SrcReg into the \p DstRegs /// corresponding to the aggregate type \p PackedTy. /// diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index d0e8188cf5559..864df28d1ff1d 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -224,31 +224,6 @@ void CallLowering::splitToValueTypes(const ArgInfo &OrigArg, SplitArgs.back().Flags[0].setInConsecutiveRegsLast(); } -Register CallLowering::packRegs(ArrayRef SrcRegs, Type *PackedTy, - MachineIRBuilder &MIRBuilder) const { - assert(SrcRegs.size() > 1 && "Nothing to pack"); - - const DataLayout &DL = MIRBuilder.getMF().getDataLayout(); - MachineRegisterInfo *MRI = MIRBuilder.getMRI(); - - LLT PackedLLT = getLLTForType(*PackedTy, DL); - - SmallVector LLTs; - SmallVector Offsets; - computeValueLLTs(DL, *PackedTy, LLTs, &Offsets); - assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); - - Register Dst = MRI->createGenericVirtualRegister(PackedLLT); - MIRBuilder.buildUndef(Dst); - for (unsigned i = 0; i < SrcRegs.size(); ++i) { - Register NewDst = MRI->createGenericVirtualRegister(PackedLLT); - MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); - Dst = NewDst; - } - - return Dst; -} - void CallLowering::unpackRegs(ArrayRef DstRegs, Register SrcReg, Type *PackedTy, MachineIRBuilder &MIRBuilder) const {