From 027516553da4d380a9a7ea673342dba61318cc47 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames@rivosinc.com>
Date: Thu, 6 Oct 2022 15:11:34 -0700
Subject: [PATCH] [RISCV] Verify that policy operands only exist on
 instructions with tied passthru operands

This is a non-trivial property relied upon by D135396. I wrote this to convince myself it was true.

Differential Revision: https://reviews.llvm.org/D135403
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 4ab53925799bc..05b0c016c943c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1266,6 +1266,15 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
       ErrInfo = "policy operand w/o VL operand?";
       return false;
     }
+
+    // VecPolicy operands can only exist on instructions with passthru/merge
+    // arguments. Note that not all arguments with passthru have vec policy
+    // operands- some instructions have implicit policies.
+    unsigned UseOpIdx;
+    if (!MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+      ErrInfo = "policy operand w/o tied operand?";
+      return false;
+    }
   }
 
   return true;