diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
index 6527aa4199110..a5da99a9e6e8d 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; i8
-define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind #0 {
+define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI0_0
@@ -17,7 +17,7 @@ define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind #0 {
  ret <4 x i8> %c
 }
 
-define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind #0 {
+define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
@@ -30,7 +30,7 @@ define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind #0 {
  ret <8 x i8> %c
 }
 
-define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind #0 {
+define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
@@ -43,7 +43,7 @@ define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind #0 {
  ret <16 x i8> %c
 }
 
-define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind #0 {
+define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind {
 ; CHECK-LABEL: vls_sve_and_32xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
@@ -61,7 +61,7 @@ define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind #0 {
 }
 
 ; i16
-define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind #0 {
+define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_2xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -76,7 +76,7 @@ define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind #0 {
  ret <2 x i16> %c
 }
 
-define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind #0 {
+define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI5_0
@@ -89,7 +89,7 @@ define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind #0 {
  ret <4 x i16> %c
 }
 
-define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind #0 {
+define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI6_0
@@ -102,7 +102,7 @@ define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind #0 {
  ret <8 x i16> %c
 }
 
-define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind #0 {
+define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_16xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI7_0
@@ -119,7 +119,7 @@ define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind #0 {
 }
 
 ; i32
-define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind #0 {
+define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -131,7 +131,7 @@ define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind #0 {
  ret <2 x i32> %c
 }
 
-define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind #0 {
+define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI9_0
@@ -144,7 +144,7 @@ define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind #0 {
  ret <4 x i32> %c
 }
 
-define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind #0 {
+define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_8xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI10_0
@@ -161,7 +161,7 @@ define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind #0 {
 }
 
 ; i64
-define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind #0 {
+define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_2xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -173,7 +173,7 @@ define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind #0 {
  ret <2 x i64> %c
 }
 
-define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind #0 {
+define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind {
 ; CHECK-LABEL: vls_sve_and_4xi64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -187,5 +187,3 @@ define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind #0 {
  %c = and <4 x i64> %b, <i64 0, i64 18446744073709551615, i64 0, i64 18446744073709551615>
  ret <4 x i64> %c
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
index fe177ddb5fff5..8f36a9673b821 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; CLZ
 ;
 
-define <4 x i8> @ctlz_v4i8(<4 x i8> %op) #0 {
+define <4 x i8> @ctlz_v4i8(<4 x i8> %op) {
 ; CHECK-LABEL: ctlz_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -21,7 +21,7 @@ define <4 x i8> @ctlz_v4i8(<4 x i8> %op) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @ctlz_v8i8(<8 x i8> %op) #0 {
+define <8 x i8> @ctlz_v8i8(<8 x i8> %op) {
 ; CHECK-LABEL: ctlz_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -33,7 +33,7 @@ define <8 x i8> @ctlz_v8i8(<8 x i8> %op) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @ctlz_v16i8(<16 x i8> %op) #0 {
+define <16 x i8> @ctlz_v16i8(<16 x i8> %op) {
 ; CHECK-LABEL: ctlz_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -45,7 +45,7 @@ define <16 x i8> @ctlz_v16i8(<16 x i8> %op) #0 {
   ret <16 x i8> %res
 }
 
-define void @ctlz_v32i8(ptr %a) #0 {
+define void @ctlz_v32i8(ptr %a) {
 ; CHECK-LABEL: ctlz_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -60,7 +60,7 @@ define void @ctlz_v32i8(ptr %a) #0 {
   ret void
 }
 
-define <2 x i16> @ctlz_v2i16(<2 x i16> %op) #0 {
+define <2 x i16> @ctlz_v2i16(<2 x i16> %op) {
 ; CHECK-LABEL: ctlz_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -74,7 +74,7 @@ define <2 x i16> @ctlz_v2i16(<2 x i16> %op) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @ctlz_v4i16(<4 x i16> %op) #0 {
+define <4 x i16> @ctlz_v4i16(<4 x i16> %op) {
 ; CHECK-LABEL: ctlz_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -86,7 +86,7 @@ define <4 x i16> @ctlz_v4i16(<4 x i16> %op) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @ctlz_v8i16(<8 x i16> %op) #0 {
+define <8 x i16> @ctlz_v8i16(<8 x i16> %op) {
 ; CHECK-LABEL: ctlz_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -98,7 +98,7 @@ define <8 x i16> @ctlz_v8i16(<8 x i16> %op) #0 {
   ret <8 x i16> %res
 }
 
-define void @ctlz_v16i16(ptr %a) #0 {
+define void @ctlz_v16i16(ptr %a) {
 ; CHECK-LABEL: ctlz_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -113,7 +113,7 @@ define void @ctlz_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @ctlz_v2i32(<2 x i32> %op) #0 {
+define <2 x i32> @ctlz_v2i32(<2 x i32> %op) {
 ; CHECK-LABEL: ctlz_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -125,7 +125,7 @@ define <2 x i32> @ctlz_v2i32(<2 x i32> %op) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @ctlz_v4i32(<4 x i32> %op) #0 {
+define <4 x i32> @ctlz_v4i32(<4 x i32> %op) {
 ; CHECK-LABEL: ctlz_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -137,7 +137,7 @@ define <4 x i32> @ctlz_v4i32(<4 x i32> %op) #0 {
   ret <4 x i32> %res
 }
 
-define void @ctlz_v8i32(ptr %a) #0 {
+define void @ctlz_v8i32(ptr %a) {
 ; CHECK-LABEL: ctlz_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -152,7 +152,7 @@ define void @ctlz_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @ctlz_v1i64(<1 x i64> %op) #0 {
+define <1 x i64> @ctlz_v1i64(<1 x i64> %op) {
 ; CHECK-LABEL: ctlz_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -164,7 +164,7 @@ define <1 x i64> @ctlz_v1i64(<1 x i64> %op) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @ctlz_v2i64(<2 x i64> %op) #0 {
+define <2 x i64> @ctlz_v2i64(<2 x i64> %op) {
 ; CHECK-LABEL: ctlz_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -176,7 +176,7 @@ define <2 x i64> @ctlz_v2i64(<2 x i64> %op) #0 {
   ret <2 x i64> %res
 }
 
-define void @ctlz_v4i64(ptr %a) #0 {
+define void @ctlz_v4i64(ptr %a) {
 ; CHECK-LABEL: ctlz_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -195,7 +195,7 @@ define void @ctlz_v4i64(ptr %a) #0 {
 ; CNT
 ;
 
-define <4 x i8> @ctpop_v4i8(<4 x i8> %op) #0 {
+define <4 x i8> @ctpop_v4i8(<4 x i8> %op) {
 ; CHECK-LABEL: ctpop_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -208,7 +208,7 @@ define <4 x i8> @ctpop_v4i8(<4 x i8> %op) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @ctpop_v8i8(<8 x i8> %op) #0 {
+define <8 x i8> @ctpop_v8i8(<8 x i8> %op) {
 ; CHECK-LABEL: ctpop_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -220,7 +220,7 @@ define <8 x i8> @ctpop_v8i8(<8 x i8> %op) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @ctpop_v16i8(<16 x i8> %op) #0 {
+define <16 x i8> @ctpop_v16i8(<16 x i8> %op) {
 ; CHECK-LABEL: ctpop_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -232,7 +232,7 @@ define <16 x i8> @ctpop_v16i8(<16 x i8> %op) #0 {
   ret <16 x i8> %res
 }
 
-define void @ctpop_v32i8(ptr %a) #0 {
+define void @ctpop_v32i8(ptr %a) {
 ; CHECK-LABEL: ctpop_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -247,7 +247,7 @@ define void @ctpop_v32i8(ptr %a) #0 {
   ret void
 }
 
-define <2 x i16> @ctpop_v2i16(<2 x i16> %op) #0 {
+define <2 x i16> @ctpop_v2i16(<2 x i16> %op) {
 ; CHECK-LABEL: ctpop_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -260,7 +260,7 @@ define <2 x i16> @ctpop_v2i16(<2 x i16> %op) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @ctpop_v4i16(<4 x i16> %op) #0 {
+define <4 x i16> @ctpop_v4i16(<4 x i16> %op) {
 ; CHECK-LABEL: ctpop_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -272,7 +272,7 @@ define <4 x i16> @ctpop_v4i16(<4 x i16> %op) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @ctpop_v8i16(<8 x i16> %op) #0 {
+define <8 x i16> @ctpop_v8i16(<8 x i16> %op) {
 ; CHECK-LABEL: ctpop_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -284,7 +284,7 @@ define <8 x i16> @ctpop_v8i16(<8 x i16> %op) #0 {
   ret <8 x i16> %res
 }
 
-define void @ctpop_v16i16(ptr %a) #0 {
+define void @ctpop_v16i16(ptr %a) {
 ; CHECK-LABEL: ctpop_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -299,7 +299,7 @@ define void @ctpop_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @ctpop_v2i32(<2 x i32> %op) #0 {
+define <2 x i32> @ctpop_v2i32(<2 x i32> %op) {
 ; CHECK-LABEL: ctpop_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -311,7 +311,7 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %op) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @ctpop_v4i32(<4 x i32> %op) #0 {
+define <4 x i32> @ctpop_v4i32(<4 x i32> %op) {
 ; CHECK-LABEL: ctpop_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -323,7 +323,7 @@ define <4 x i32> @ctpop_v4i32(<4 x i32> %op) #0 {
   ret <4 x i32> %res
 }
 
-define void @ctpop_v8i32(ptr %a) #0 {
+define void @ctpop_v8i32(ptr %a) {
 ; CHECK-LABEL: ctpop_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -338,7 +338,7 @@ define void @ctpop_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @ctpop_v1i64(<1 x i64> %op) #0 {
+define <1 x i64> @ctpop_v1i64(<1 x i64> %op) {
 ; CHECK-LABEL: ctpop_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -350,7 +350,7 @@ define <1 x i64> @ctpop_v1i64(<1 x i64> %op) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @ctpop_v2i64(<2 x i64> %op) #0 {
+define <2 x i64> @ctpop_v2i64(<2 x i64> %op) {
 ; CHECK-LABEL: ctpop_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -362,7 +362,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %op) #0 {
   ret <2 x i64> %res
 }
 
-define void @ctpop_v4i64(ptr %a) #0 {
+define void @ctpop_v4i64(ptr %a) {
 ; CHECK-LABEL: ctpop_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -381,7 +381,7 @@ define void @ctpop_v4i64(ptr %a) #0 {
 ; Count trailing zeros
 ;
 
-define <4 x i8> @cttz_v4i8(<4 x i8> %op) #0 {
+define <4 x i8> @cttz_v4i8(<4 x i8> %op) {
 ; CHECK-LABEL: cttz_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -395,7 +395,7 @@ define <4 x i8> @cttz_v4i8(<4 x i8> %op) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @cttz_v8i8(<8 x i8> %op) #0 {
+define <8 x i8> @cttz_v8i8(<8 x i8> %op) {
 ; CHECK-LABEL: cttz_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -408,7 +408,7 @@ define <8 x i8> @cttz_v8i8(<8 x i8> %op) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @cttz_v16i8(<16 x i8> %op) #0 {
+define <16 x i8> @cttz_v16i8(<16 x i8> %op) {
 ; CHECK-LABEL: cttz_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -421,7 +421,7 @@ define <16 x i8> @cttz_v16i8(<16 x i8> %op) #0 {
   ret <16 x i8> %res
 }
 
-define void @cttz_v32i8(ptr %a) #0 {
+define void @cttz_v32i8(ptr %a) {
 ; CHECK-LABEL: cttz_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -438,7 +438,7 @@ define void @cttz_v32i8(ptr %a) #0 {
   ret void
 }
 
-define <2 x i16> @cttz_v2i16(<2 x i16> %op) #0 {
+define <2 x i16> @cttz_v2i16(<2 x i16> %op) {
 ; CHECK-LABEL: cttz_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -452,7 +452,7 @@ define <2 x i16> @cttz_v2i16(<2 x i16> %op) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @cttz_v4i16(<4 x i16> %op) #0 {
+define <4 x i16> @cttz_v4i16(<4 x i16> %op) {
 ; CHECK-LABEL: cttz_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -465,7 +465,7 @@ define <4 x i16> @cttz_v4i16(<4 x i16> %op) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @cttz_v8i16(<8 x i16> %op) #0 {
+define <8 x i16> @cttz_v8i16(<8 x i16> %op) {
 ; CHECK-LABEL: cttz_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -478,7 +478,7 @@ define <8 x i16> @cttz_v8i16(<8 x i16> %op) #0 {
   ret <8 x i16> %res
 }
 
-define void @cttz_v16i16(ptr %a) #0 {
+define void @cttz_v16i16(ptr %a) {
 ; CHECK-LABEL: cttz_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -495,7 +495,7 @@ define void @cttz_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @cttz_v2i32(<2 x i32> %op) #0 {
+define <2 x i32> @cttz_v2i32(<2 x i32> %op) {
 ; CHECK-LABEL: cttz_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -508,7 +508,7 @@ define <2 x i32> @cttz_v2i32(<2 x i32> %op) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @cttz_v4i32(<4 x i32> %op) #0 {
+define <4 x i32> @cttz_v4i32(<4 x i32> %op) {
 ; CHECK-LABEL: cttz_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -521,7 +521,7 @@ define <4 x i32> @cttz_v4i32(<4 x i32> %op) #0 {
   ret <4 x i32> %res
 }
 
-define void @cttz_v8i32(ptr %a) #0 {
+define void @cttz_v8i32(ptr %a) {
 ; CHECK-LABEL: cttz_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -538,7 +538,7 @@ define void @cttz_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @cttz_v1i64(<1 x i64> %op) #0 {
+define <1 x i64> @cttz_v1i64(<1 x i64> %op) {
 ; CHECK-LABEL: cttz_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -551,7 +551,7 @@ define <1 x i64> @cttz_v1i64(<1 x i64> %op) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @cttz_v2i64(<2 x i64> %op) #0 {
+define <2 x i64> @cttz_v2i64(<2 x i64> %op) {
 ; CHECK-LABEL: cttz_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -564,7 +564,7 @@ define <2 x i64> @cttz_v2i64(<2 x i64> %op) #0 {
   ret <2 x i64> %res
 }
 
-define void @cttz_v4i64(ptr %a) #0 {
+define void @cttz_v4i64(ptr %a) {
 ; CHECK-LABEL: cttz_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -581,7 +581,6 @@ define void @cttz_v4i64(ptr %a) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
 
 declare <4 x i8> @llvm.ctlz.v4i8(<4 x i8>)
 declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
index 33a134ecee969..9fee61cd0d833 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @bitcast_v4i8(ptr %a, ptr %b) #0 {
+define void @bitcast_v4i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -16,7 +16,7 @@ define void @bitcast_v4i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v8i8(ptr %a, ptr %b) #0 {
+define void @bitcast_v8i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -28,7 +28,7 @@ define void @bitcast_v8i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v16i8(ptr %a, ptr %b) #0 {
+define void @bitcast_v16i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -40,7 +40,7 @@ define void @bitcast_v16i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v32i8(ptr %a, ptr %b) #0 {
+define void @bitcast_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -54,7 +54,7 @@ define void @bitcast_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v2i16(ptr %a, ptr %b) #0 {
+define void @bitcast_v2i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -80,7 +80,7 @@ define void @bitcast_v2i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v4i16(ptr %a, ptr %b) #0 {
+define void @bitcast_v4i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -92,7 +92,7 @@ define void @bitcast_v4i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v8i16(ptr %a, ptr %b) #0 {
+define void @bitcast_v8i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -104,7 +104,7 @@ define void @bitcast_v8i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v16i16(ptr %a, ptr %b) #0 {
+define void @bitcast_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -118,7 +118,7 @@ define void @bitcast_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v2i32(ptr %a, ptr %b) #0 {
+define void @bitcast_v2i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -130,7 +130,7 @@ define void @bitcast_v2i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v4i32(ptr %a, ptr %b) #0 {
+define void @bitcast_v4i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -142,7 +142,7 @@ define void @bitcast_v4i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v8i32(ptr %a, ptr %b) #0 {
+define void @bitcast_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -156,7 +156,7 @@ define void @bitcast_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v1i64(ptr %a, ptr %b) #0 {
+define void @bitcast_v1i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -168,7 +168,7 @@ define void @bitcast_v1i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v2i64(ptr %a, ptr %b) #0 {
+define void @bitcast_v2i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -180,7 +180,7 @@ define void @bitcast_v2i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @bitcast_v4i64(ptr %a, ptr %b) #0 {
+define void @bitcast_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: bitcast_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -194,4 +194,3 @@ define void @bitcast_v4i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
index 5ef230dd5c9a5..9ffd05b799b24 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64"
 
@@ -9,7 +9,7 @@ target triple = "aarch64"
 ;       this is implemented, this test will be fleshed out.
 ;
 
-define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) #0 {
+define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) {
 ; CHECK-LABEL: fixed_bitselect_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q3, q2, [x0]
@@ -41,4 +41,3 @@ define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %r
   ret <8 x i32> %bsl0000
 }
 
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
index c9b42e1651c8f..745ba26d92ca0 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @build_vector_7_inc1_v4i1(ptr %a) #0 {
+define void @build_vector_7_inc1_v4i1(ptr %a) {
 ; CHECK-LABEL: build_vector_7_inc1_v4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #5 // =0x5
@@ -13,7 +13,7 @@ define void @build_vector_7_inc1_v4i1(ptr %a) #0 {
   ret void
 }
 
-define void @build_vector_7_inc1_v32i8(ptr %a) #0 {
+define void @build_vector_7_inc1_v32i8(ptr %a) {
 ; CHECK-LABEL: build_vector_7_inc1_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    index z0.b, #0, #1
@@ -26,7 +26,7 @@ define void @build_vector_7_inc1_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @build_vector_0_inc2_v16i16(ptr %a) #0 {
+define void @build_vector_0_inc2_v16i16(ptr %a) {
 ; CHECK-LABEL: build_vector_0_inc2_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    index z0.h, #0, #2
@@ -39,7 +39,7 @@ define void @build_vector_0_inc2_v16i16(ptr %a) #0 {
 }
 
 ; Negative const stride.
-define void @build_vector_0_dec3_v8i32(ptr %a) #0 {
+define void @build_vector_0_dec3_v8i32(ptr %a) {
 ; CHECK-LABEL: build_vector_0_dec3_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    index z0.s, #0, #-3
@@ -52,7 +52,7 @@ define void @build_vector_0_dec3_v8i32(ptr %a) #0 {
 }
 
 ; Constant stride that's too big to be directly encoded into the index.
-define void @build_vector_minus2_dec32_v4i64(ptr %a) #0 {
+define void @build_vector_minus2_dec32_v4i64(ptr %a) {
 ; CHECK-LABEL: build_vector_minus2_dec32_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-32 // =0xffffffffffffffe0
@@ -68,7 +68,7 @@ define void @build_vector_minus2_dec32_v4i64(ptr %a) #0 {
 }
 
 ; Constant but not a sequence.
-define void @build_vector_no_stride_v4i64(ptr %a) #0 {
+define void @build_vector_no_stride_v4i64(ptr %a) {
 ; CHECK-LABEL: build_vector_no_stride_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    index z0.d, #1, #7
@@ -79,7 +79,7 @@ define void @build_vector_no_stride_v4i64(ptr %a) #0 {
   ret void
 }
 
-define void @build_vector_0_inc2_v16f16(ptr %a) #0 {
+define void @build_vector_0_inc2_v16f16(ptr %a) {
 ; CHECK-LABEL: build_vector_0_inc2_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI6_0
@@ -93,7 +93,7 @@ define void @build_vector_0_inc2_v16f16(ptr %a) #0 {
 }
 
 ; Negative const stride.
-define void @build_vector_0_dec3_v8f32(ptr %a) #0 {
+define void @build_vector_0_dec3_v8f32(ptr %a) {
 ; CHECK-LABEL: build_vector_0_dec3_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI7_0
@@ -107,7 +107,7 @@ define void @build_vector_0_dec3_v8f32(ptr %a) #0 {
 }
 
 ; Constant stride that's too big to be directly encoded into the index.
-define void @build_vector_minus2_dec32_v4f64(ptr %a) #0 {
+define void @build_vector_minus2_dec32_v4f64(ptr %a) {
 ; CHECK-LABEL: build_vector_minus2_dec32_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI8_0
@@ -121,7 +121,7 @@ define void @build_vector_minus2_dec32_v4f64(ptr %a) #0 {
 }
 
 ; Constant but not a sequence.
-define void @build_vector_no_stride_v4f64(ptr %a) #0 {
+define void @build_vector_no_stride_v4f64(ptr %a) {
 ; CHECK-LABEL: build_vector_no_stride_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI9_0
@@ -133,6 +133,3 @@ define void @build_vector_no_stride_v4f64(ptr %a) #0 {
   store <4 x double> <double 0.0, double 4.0, double 1.0, double 8.0>, ptr %a, align 8
   ret void
 }
-
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
index c40c13d23da1d..767d7c0fa4a02 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; i8
 ;
 
-define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2)  #0 {
+define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2)  {
 ; CHECK-LABEL: concat_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -43,7 +43,7 @@ define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2)  #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2)  #0 {
+define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2)  {
 ; CHECK-LABEL: concat_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -57,7 +57,7 @@ define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2)  #0 {
   ret <16 x i8> %res
 }
 
-define void @concat_v32i8(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v32i8(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -74,7 +74,7 @@ define void @concat_v32i8(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v64i8(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v64i8(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v64i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -100,7 +100,7 @@ define void @concat_v64i8(ptr %a, ptr %b, ptr %c) #0 {
 ; i16
 ;
 
-define <4 x i16> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2)  #0 {
+define <4 x i16> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2)  {
 ; CHECK-LABEL: concat_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -125,7 +125,7 @@ define <4 x i16> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2)  #0 {
 }
 
 ; Don't use SVE for 128-bit vectors.
-define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2)  #0 {
+define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2)  {
 ; CHECK-LABEL: concat_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -138,7 +138,7 @@ define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2)  #0 {
   ret <8 x i16> %res
 }
 
-define void @concat_v16i16(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v16i16(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -153,7 +153,7 @@ define void @concat_v16i16(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v32i16(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v32i16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -176,7 +176,7 @@ define void @concat_v32i16(ptr %a, ptr %b, ptr %c) #0 {
 ;
 
 ; Don't use SVE for 64-bit vectors.
-define <2 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2)  #0 {
+define <2 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2)  {
 ; CHECK-LABEL: concat_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -189,7 +189,7 @@ define <2 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2)  #0 {
 }
 
 ; Don't use SVE for 128-bit vectors.
-define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2)  #0 {
+define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2)  {
 ; CHECK-LABEL: concat_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -202,7 +202,7 @@ define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2)  #0 {
   ret <4 x i32> %res
 }
 
-define void @concat_v8i32(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v8i32(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -216,7 +216,7 @@ define void @concat_v8i32(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v16i32(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v16i32(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -237,7 +237,7 @@ define void @concat_v16i32(ptr %a, ptr %b, ptr %c) #0 {
 ;
 
 ; Don't use SVE for 128-bit vectors.
-define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2)  #0 {
+define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2)  {
 ; CHECK-LABEL: concat_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -250,7 +250,7 @@ define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2)  #0 {
   ret <2 x i64> %res
 }
 
-define void @concat_v4i64(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v4i64(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -264,7 +264,7 @@ define void @concat_v4i64(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v8i64(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v8i64(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -283,7 +283,7 @@ define void @concat_v8i64(ptr %a, ptr %b, ptr %c) #0 {
 ; f16
 ;
 
-define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2)  #0 {
+define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2)  {
 ; CHECK-LABEL: concat_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -303,7 +303,7 @@ define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2)  #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2)  #0 {
+define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2)  {
 ; CHECK-LABEL: concat_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -316,7 +316,7 @@ define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2)  #0 {
   ret <8 x half> %res
 }
 
-define void @concat_v16f16(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v16f16(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -331,7 +331,7 @@ define void @concat_v16f16(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v32f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v32f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v32f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -354,7 +354,7 @@ define void @concat_v32f16(ptr %a, ptr %b, ptr %c) #0 {
 ;
 
 ; Don't use SVE for 64-bit vectors.
-define <2 x float> @concat_v2f32(<1 x float> %op1, <1 x float> %op2)  #0 {
+define <2 x float> @concat_v2f32(<1 x float> %op1, <1 x float> %op2)  {
 ; CHECK-LABEL: concat_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -367,7 +367,7 @@ define <2 x float> @concat_v2f32(<1 x float> %op1, <1 x float> %op2)  #0 {
 }
 
 ; Don't use SVE for 128-bit vectors.
-define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2)  #0 {
+define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2)  {
 ; CHECK-LABEL: concat_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -380,7 +380,7 @@ define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2)  #0 {
   ret <4 x float> %res
 }
 
-define void @concat_v8f32(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v8f32(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -394,7 +394,7 @@ define void @concat_v8f32(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v16f32(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v16f32(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -415,7 +415,7 @@ define void @concat_v16f32(ptr %a, ptr %b, ptr %c) #0 {
 ;
 
 ; Don't use SVE for 128-bit vectors.
-define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2)  #0 {
+define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2)  {
 ; CHECK-LABEL: concat_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -428,7 +428,7 @@ define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2)  #0 {
   ret <2 x double> %res
 }
 
-define void @concat_v4f64(ptr %a, ptr %b, ptr %c)  #0 {
+define void @concat_v4f64(ptr %a, ptr %b, ptr %c)  {
 ; CHECK-LABEL: concat_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x1]
@@ -442,7 +442,7 @@ define void @concat_v4f64(ptr %a, ptr %b, ptr %c)  #0 {
   ret void
 }
 
-define void @concat_v8f64(ptr %a, ptr %b, ptr %c) #0 {
+define void @concat_v8f64(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: concat_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -461,7 +461,7 @@ define void @concat_v8f64(ptr %a, ptr %b, ptr %c) #0 {
 ; undef
 ;
 
-define void @concat_v32i8_undef(ptr %a, ptr %b)  #0 {
+define void @concat_v32i8_undef(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v32i8_undef:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -476,7 +476,7 @@ define void @concat_v32i8_undef(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @concat_v16i16_undef(ptr %a, ptr %b)  #0 {
+define void @concat_v16i16_undef(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v16i16_undef:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -489,7 +489,7 @@ define void @concat_v16i16_undef(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @concat_v8i32_undef(ptr %a, ptr %b)  #0 {
+define void @concat_v8i32_undef(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v8i32_undef:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -501,7 +501,7 @@ define void @concat_v8i32_undef(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @concat_v4i64_undef(ptr %a, ptr %b)  #0 {
+define void @concat_v4i64_undef(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v4i64_undef:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -517,7 +517,7 @@ define void @concat_v4i64_undef(ptr %a, ptr %b)  #0 {
 ; > 2 operands
 ;
 
-define void @concat_v32i8_4op(ptr %a, ptr %b)  #0 {
+define void @concat_v32i8_4op(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v32i8_4op:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -534,7 +534,7 @@ define void @concat_v32i8_4op(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @concat_v16i16_4op(ptr %a, ptr %b)  #0 {
+define void @concat_v16i16_4op(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v16i16_4op:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -548,7 +548,7 @@ define void @concat_v16i16_4op(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @concat_v8i32_4op(ptr %a, ptr %b)  #0 {
+define void @concat_v8i32_4op(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v8i32_4op:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -561,7 +561,7 @@ define void @concat_v8i32_4op(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @concat_v4i64_4op(ptr %a, ptr %b)  #0 {
+define void @concat_v4i64_4op(ptr %a, ptr %b)  {
 ; CHECK-LABEL: concat_v4i64_4op:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -573,5 +573,3 @@ define void @concat_v4i64_4op(ptr %a, ptr %b)  #0 {
   store <4 x i64> %res, ptr %b
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
index cc0d76dcbbf43..c4082142ada78 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <8 x i16> @load_zext_v8i8i16(ptr %ap)  #0 {
+define <8 x i16> @load_zext_v8i8i16(ptr %ap)  {
 ; CHECK-LABEL: load_zext_v8i8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl8
@@ -15,7 +15,7 @@ define <8 x i16> @load_zext_v8i8i16(ptr %ap)  #0 {
   ret <8 x i16> %val
 }
 
-define <4 x i32> @load_zext_v4i16i32(ptr %ap)  #0 {
+define <4 x i32> @load_zext_v4i16i32(ptr %ap)  {
 ; CHECK-LABEL: load_zext_v4i16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl4
@@ -27,7 +27,7 @@ define <4 x i32> @load_zext_v4i16i32(ptr %ap)  #0 {
   ret <4 x i32> %val
 }
 
-define <2 x i64> @load_zext_v2i32i64(ptr %ap) #0 {
+define <2 x i64> @load_zext_v2i32i64(ptr %ap) {
 ; CHECK-LABEL: load_zext_v2i32i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -39,7 +39,7 @@ define <2 x i64> @load_zext_v2i32i64(ptr %ap) #0 {
   ret <2 x i64> %val
 }
 
-define <2 x i256> @load_zext_v2i64i256(ptr %ap) #0 {
+define <2 x i256> @load_zext_v2i64i256(ptr %ap) {
 ; CHECK-LABEL: load_zext_v2i64i256:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -58,7 +58,7 @@ define <2 x i256> @load_zext_v2i64i256(ptr %ap) #0 {
   ret <2 x i256> %val
 }
 
-define <16 x i32> @load_sext_v16i8i32(ptr %ap)  #0 {
+define <16 x i32> @load_sext_v16i8i32(ptr %ap)  {
 ; CHECK-LABEL: load_sext_v16i8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #4 // =0x4
@@ -79,7 +79,7 @@ define <16 x i32> @load_sext_v16i8i32(ptr %ap)  #0 {
   ret <16 x i32> %val
 }
 
-define <8 x i32> @load_sext_v8i16i32(ptr %ap)  #0 {
+define <8 x i32> @load_sext_v8i16i32(ptr %ap)  {
 ; CHECK-LABEL: load_sext_v8i16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #4 // =0x4
@@ -94,7 +94,7 @@ define <8 x i32> @load_sext_v8i16i32(ptr %ap)  #0 {
   ret <8 x i32> %val
 }
 
-define <4 x i256> @load_sext_v4i32i256(ptr %ap) #0 {
+define <4 x i256> @load_sext_v4i32i256(ptr %ap) {
 ; CHECK-LABEL: load_sext_v4i32i256:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -125,7 +125,7 @@ define <4 x i256> @load_sext_v4i32i256(ptr %ap) #0 {
   ret <4 x i256> %val
 }
 
-define <2 x i256> @load_sext_v2i64i256(ptr %ap) #0 {
+define <2 x i256> @load_sext_v2i64i256(ptr %ap) {
 ; CHECK-LABEL: load_sext_v2i64i256:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -158,7 +158,7 @@ define <2 x i256> @load_sext_v2i64i256(ptr %ap) #0 {
   ret <2 x i256> %val
 }
 
-define <16 x i64> @load_zext_v16i16i64(ptr %ap)  #0 {
+define <16 x i64> @load_zext_v16i16i64(ptr %ap)  {
 ; CHECK-LABEL: load_zext_v16i16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #2 // =0x2
@@ -190,5 +190,3 @@ define <16 x i64> @load_zext_v16i16i64(ptr %ap)  #0 {
   %val = zext <16 x i16> %a to <16 x i64>
   ret <16 x i64> %val
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
index 9e4c1862bcb06..cc046e57b5996 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; i1
 
-define <4 x i1> @extract_subvector_v8i1(<8 x i1> %op) #0 {
+define <4 x i1> @extract_subvector_v8i1(<8 x i1> %op) {
 ; CHECK-LABEL: extract_subvector_v8i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -32,7 +32,7 @@ define <4 x i1> @extract_subvector_v8i1(<8 x i1> %op) #0 {
 
 ; i8
 
-define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) #0 {
+define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) {
 ; CHECK-LABEL: extract_subvector_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -57,7 +57,7 @@ define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) #0 {
   ret <4 x i8> %ret
 }
 
-define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) #0 {
+define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) {
 ; CHECK-LABEL: extract_subvector_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -68,7 +68,7 @@ define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) #0 {
   ret <8 x i8> %ret
 }
 
-define void @extract_subvector_v32i8(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -82,7 +82,7 @@ define void @extract_subvector_v32i8(ptr %a, ptr %b) #0 {
 
 ; i16
 
-define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) #0 {
+define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) {
 ; CHECK-LABEL: extract_subvector_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -94,7 +94,7 @@ define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) #0 {
   ret <2 x i16> %ret
 }
 
-define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) #0 {
+define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) {
 ; CHECK-LABEL: extract_subvector_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -105,7 +105,7 @@ define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) #0 {
   ret <4 x i16> %ret
 }
 
-define void @extract_subvector_v16i16(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -119,7 +119,7 @@ define void @extract_subvector_v16i16(ptr %a, ptr %b) #0 {
 
 ; i32
 
-define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) #0 {
+define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) {
 ; CHECK-LABEL: extract_subvector_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -130,7 +130,7 @@ define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) #0 {
   ret <1 x i32> %ret
 }
 
-define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) #0 {
+define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) {
 ; CHECK-LABEL: extract_subvector_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -141,7 +141,7 @@ define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) #0 {
   ret <2 x i32> %ret
 }
 
-define void @extract_subvector_v8i32(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -155,7 +155,7 @@ define void @extract_subvector_v8i32(ptr %a, ptr %b) #0 {
 
 ; i64
 
-define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) #0 {
+define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) {
 ; CHECK-LABEL: extract_subvector_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -166,7 +166,7 @@ define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) #0 {
   ret <1 x i64> %ret
 }
 
-define void @extract_subvector_v4i64(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -180,7 +180,7 @@ define void @extract_subvector_v4i64(ptr %a, ptr %b) #0 {
 
 ; f16
 
-define <2 x half> @extract_subvector_v4f16(<4 x half> %op) #0 {
+define <2 x half> @extract_subvector_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: extract_subvector_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -197,7 +197,7 @@ define <2 x half> @extract_subvector_v4f16(<4 x half> %op) #0 {
   ret <2 x half> %ret
 }
 
-define <4 x half> @extract_subvector_v8f16(<8 x half> %op) #0 {
+define <4 x half> @extract_subvector_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: extract_subvector_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -208,7 +208,7 @@ define <4 x half> @extract_subvector_v8f16(<8 x half> %op) #0 {
   ret <4 x half> %ret
 }
 
-define void @extract_subvector_v16f16(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -222,7 +222,7 @@ define void @extract_subvector_v16f16(ptr %a, ptr %b) #0 {
 
 ; f32
 
-define <1 x float> @extract_subvector_v2f32(<2 x float> %op) #0 {
+define <1 x float> @extract_subvector_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: extract_subvector_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -233,7 +233,7 @@ define <1 x float> @extract_subvector_v2f32(<2 x float> %op) #0 {
   ret <1 x float> %ret
 }
 
-define <2 x float> @extract_subvector_v4f32(<4 x float> %op) #0 {
+define <2 x float> @extract_subvector_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: extract_subvector_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -244,7 +244,7 @@ define <2 x float> @extract_subvector_v4f32(<4 x float> %op) #0 {
   ret <2 x float> %ret
 }
 
-define void @extract_subvector_v8f32(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -258,7 +258,7 @@ define void @extract_subvector_v8f32(ptr %a, ptr %b) #0 {
 
 ; f64
 
-define <1 x double> @extract_subvector_v2f64(<2 x double> %op) #0 {
+define <1 x double> @extract_subvector_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: extract_subvector_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -269,7 +269,7 @@ define <1 x double> @extract_subvector_v2f64(<2 x double> %op) #0 {
   ret <1 x double> %ret
 }
 
-define void @extract_subvector_v4f64(ptr %a, ptr %b) #0 {
+define void @extract_subvector_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: extract_subvector_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -315,5 +315,3 @@ declare <8 x float> @llvm.vector.extract.v8f32.v16f32(<16 x float>, i64)
 declare <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double>, i64)
 declare <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double>, i64)
 declare <4 x double> @llvm.vector.extract.v4f64.v8f64(<8 x double>, i64)
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
index 4bb9e565746cb..053db68b58644 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; extractelement
 ;
 
-define half @extractelement_v2f16(<2 x half> %op1) #0 {
+define half @extractelement_v2f16(<2 x half> %op1) {
 ; CHECK-LABEL: extractelement_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -18,7 +18,7 @@ define half @extractelement_v2f16(<2 x half> %op1) #0 {
   ret half %r
 }
 
-define half @extractelement_v4f16(<4 x half> %op1) #0 {
+define half @extractelement_v4f16(<4 x half> %op1) {
 ; CHECK-LABEL: extractelement_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -29,7 +29,7 @@ define half @extractelement_v4f16(<4 x half> %op1) #0 {
   ret half %r
 }
 
-define half @extractelement_v8f16(<8 x half> %op1) #0 {
+define half @extractelement_v8f16(<8 x half> %op1) {
 ; CHECK-LABEL: extractelement_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -40,7 +40,7 @@ define half @extractelement_v8f16(<8 x half> %op1) #0 {
   ret half %r
 }
 
-define half @extractelement_v16f16(ptr %a) #0 {
+define half @extractelement_v16f16(ptr %a) {
 ; CHECK-LABEL: extractelement_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -52,7 +52,7 @@ define half @extractelement_v16f16(ptr %a) #0 {
   ret half %r
 }
 
-define float @extractelement_v2f32(<2 x float> %op1) #0 {
+define float @extractelement_v2f32(<2 x float> %op1) {
 ; CHECK-LABEL: extractelement_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -63,7 +63,7 @@ define float @extractelement_v2f32(<2 x float> %op1) #0 {
   ret float %r
 }
 
-define float @extractelement_v4f32(<4 x float> %op1) #0 {
+define float @extractelement_v4f32(<4 x float> %op1) {
 ; CHECK-LABEL: extractelement_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -74,7 +74,7 @@ define float @extractelement_v4f32(<4 x float> %op1) #0 {
   ret float %r
 }
 
-define float @extractelement_v8f32(ptr %a) #0 {
+define float @extractelement_v8f32(ptr %a) {
 ; CHECK-LABEL: extractelement_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -86,7 +86,7 @@ define float @extractelement_v8f32(ptr %a) #0 {
   ret float %r
 }
 
-define double @extractelement_v1f64(<1 x double> %op1) #0 {
+define double @extractelement_v1f64(<1 x double> %op1) {
 ; CHECK-LABEL: extractelement_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -95,7 +95,7 @@ define double @extractelement_v1f64(<1 x double> %op1) #0 {
   %r = extractelement <1 x double> %op1, i64 0
   ret double %r
 }
-define double @extractelement_v2f64(<2 x double> %op1) #0 {
+define double @extractelement_v2f64(<2 x double> %op1) {
 ; CHECK-LABEL: extractelement_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -106,7 +106,7 @@ define double @extractelement_v2f64(<2 x double> %op1) #0 {
   ret double %r
 }
 
-define double @extractelement_v4f64(ptr %a) #0 {
+define double @extractelement_v4f64(ptr %a) {
 ; CHECK-LABEL: extractelement_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -117,5 +117,3 @@ define double @extractelement_v4f64(ptr %a) #0 {
   %r = extractelement <4 x double> %op1, i64 3
   ret double %r
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
index 9d59c4a0dd528..fd9dd17d17c2d 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE2
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
@@ -7,16 +8,25 @@ target triple = "aarch64-unknown-linux-gnu"
 
 ;============ f16
 
-define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f16_v4f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    ldr d1, [x1]
-; CHECK-NEXT:    and z0.h, z0.h, #0x7fff
-; CHECK-NEXT:    and z1.h, z1.h, #0x8000
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    str d0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f16_v4f16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr d0, [x0]
+; SVE-NEXT:    ldr d1, [x1]
+; SVE-NEXT:    and z0.h, z0.h, #0x7fff
+; SVE-NEXT:    and z1.h, z1.h, #0x8000
+; SVE-NEXT:    orr z0.d, z0.d, z1.d
+; SVE-NEXT:    str d0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f16_v4f16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr d0, [x0]
+; SVE2-NEXT:    mov z2.h, #32767 // =0x7fff
+; SVE2-NEXT:    ldr d1, [x1]
+; SVE2-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT:    str d0, [x0]
+; SVE2-NEXT:    ret
   %a = load <4 x half>, ptr %ap
   %b = load <4 x half>, ptr %bp
   %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b)
@@ -24,16 +34,25 @@ define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) #0 {
   ret void
 }
 
-define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v8f16_v8f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    and z0.h, z0.h, #0x7fff
-; CHECK-NEXT:    and z1.h, z1.h, #0x8000
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v8f16_v8f16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr q0, [x0]
+; SVE-NEXT:    ldr q1, [x1]
+; SVE-NEXT:    and z0.h, z0.h, #0x7fff
+; SVE-NEXT:    and z1.h, z1.h, #0x8000
+; SVE-NEXT:    orr z0.d, z0.d, z1.d
+; SVE-NEXT:    str q0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v8f16_v8f16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr q0, [x0]
+; SVE2-NEXT:    mov z2.h, #32767 // =0x7fff
+; SVE2-NEXT:    ldr q1, [x1]
+; SVE2-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT:    str q0, [x0]
+; SVE2-NEXT:    ret
   %a = load <8 x half>, ptr %ap
   %b = load <8 x half>, ptr %bp
   %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)
@@ -41,19 +60,29 @@ define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) #0 {
   ret void
 }
 
-define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v16f16_v16f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
-; CHECK-NEXT:    and z0.h, z0.h, #0x8000
-; CHECK-NEXT:    ldp q2, q3, [x0]
-; CHECK-NEXT:    and z1.h, z1.h, #0x8000
-; CHECK-NEXT:    and z2.h, z2.h, #0x7fff
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    and z3.h, z3.h, #0x7fff
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v16f16_v16f16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x1]
+; SVE-NEXT:    and z0.h, z0.h, #0x8000
+; SVE-NEXT:    ldp q2, q3, [x0]
+; SVE-NEXT:    and z1.h, z1.h, #0x8000
+; SVE-NEXT:    and z2.h, z2.h, #0x7fff
+; SVE-NEXT:    orr z0.d, z2.d, z0.d
+; SVE-NEXT:    and z3.h, z3.h, #0x7fff
+; SVE-NEXT:    orr z1.d, z3.d, z1.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v16f16_v16f16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q1, q2, [x0]
+; SVE2-NEXT:    mov z0.h, #32767 // =0x7fff
+; SVE2-NEXT:    ldp q3, q4, [x1]
+; SVE2-NEXT:    bsl z1.d, z1.d, z3.d, z0.d
+; SVE2-NEXT:    bsl z2.d, z2.d, z4.d, z0.d
+; SVE2-NEXT:    stp q1, q2, [x0]
+; SVE2-NEXT:    ret
   %a = load <16 x half>, ptr %ap
   %b = load <16 x half>, ptr %bp
   %r = call <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b)
@@ -63,16 +92,25 @@ define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) #0 {
 
 ;============ f32
 
-define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v2f32_v2f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    ldr d1, [x1]
-; CHECK-NEXT:    and z0.s, z0.s, #0x7fffffff
-; CHECK-NEXT:    and z1.s, z1.s, #0x80000000
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    str d0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v2f32_v2f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr d0, [x0]
+; SVE-NEXT:    ldr d1, [x1]
+; SVE-NEXT:    and z0.s, z0.s, #0x7fffffff
+; SVE-NEXT:    and z1.s, z1.s, #0x80000000
+; SVE-NEXT:    orr z0.d, z0.d, z1.d
+; SVE-NEXT:    str d0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v2f32_v2f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr d0, [x0]
+; SVE2-NEXT:    mov z2.s, #0x7fffffff
+; SVE2-NEXT:    ldr d1, [x1]
+; SVE2-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT:    str d0, [x0]
+; SVE2-NEXT:    ret
   %a = load <2 x float>, ptr %ap
   %b = load <2 x float>, ptr %bp
   %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b)
@@ -80,16 +118,25 @@ define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) #0 {
   ret void
 }
 
-define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f32_v4f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    and z0.s, z0.s, #0x7fffffff
-; CHECK-NEXT:    and z1.s, z1.s, #0x80000000
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f32_v4f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr q0, [x0]
+; SVE-NEXT:    ldr q1, [x1]
+; SVE-NEXT:    and z0.s, z0.s, #0x7fffffff
+; SVE-NEXT:    and z1.s, z1.s, #0x80000000
+; SVE-NEXT:    orr z0.d, z0.d, z1.d
+; SVE-NEXT:    str q0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f32_v4f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr q0, [x0]
+; SVE2-NEXT:    mov z2.s, #0x7fffffff
+; SVE2-NEXT:    ldr q1, [x1]
+; SVE2-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT:    str q0, [x0]
+; SVE2-NEXT:    ret
   %a = load <4 x float>, ptr %ap
   %b = load <4 x float>, ptr %bp
   %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)
@@ -97,19 +144,29 @@ define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) #0 {
   ret void
 }
 
-define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v8f32_v8f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
-; CHECK-NEXT:    and z0.s, z0.s, #0x80000000
-; CHECK-NEXT:    ldp q2, q3, [x0]
-; CHECK-NEXT:    and z1.s, z1.s, #0x80000000
-; CHECK-NEXT:    and z2.s, z2.s, #0x7fffffff
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    and z3.s, z3.s, #0x7fffffff
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v8f32_v8f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x1]
+; SVE-NEXT:    and z0.s, z0.s, #0x80000000
+; SVE-NEXT:    ldp q2, q3, [x0]
+; SVE-NEXT:    and z1.s, z1.s, #0x80000000
+; SVE-NEXT:    and z2.s, z2.s, #0x7fffffff
+; SVE-NEXT:    orr z0.d, z2.d, z0.d
+; SVE-NEXT:    and z3.s, z3.s, #0x7fffffff
+; SVE-NEXT:    orr z1.d, z3.d, z1.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v8f32_v8f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q1, q2, [x0]
+; SVE2-NEXT:    mov z0.s, #0x7fffffff
+; SVE2-NEXT:    ldp q3, q4, [x1]
+; SVE2-NEXT:    bsl z1.d, z1.d, z3.d, z0.d
+; SVE2-NEXT:    bsl z2.d, z2.d, z4.d, z0.d
+; SVE2-NEXT:    stp q1, q2, [x0]
+; SVE2-NEXT:    ret
   %a = load <8 x float>, ptr %ap
   %b = load <8 x float>, ptr %bp
   %r = call <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b)
@@ -119,16 +176,25 @@ define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) #0 {
 
 ;============ f64
 
-define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v2f64_v2f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    and z0.d, z0.d, #0x7fffffffffffffff
-; CHECK-NEXT:    and z1.d, z1.d, #0x8000000000000000
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v2f64_v2f64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr q0, [x0]
+; SVE-NEXT:    ldr q1, [x1]
+; SVE-NEXT:    and z0.d, z0.d, #0x7fffffffffffffff
+; SVE-NEXT:    and z1.d, z1.d, #0x8000000000000000
+; SVE-NEXT:    orr z0.d, z0.d, z1.d
+; SVE-NEXT:    str q0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v2f64_v2f64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr q0, [x0]
+; SVE2-NEXT:    mov z2.d, #0x7fffffffffffffff
+; SVE2-NEXT:    ldr q1, [x1]
+; SVE2-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT:    str q0, [x0]
+; SVE2-NEXT:    ret
   %a = load <2 x double>, ptr %ap
   %b = load <2 x double>, ptr %bp
   %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)
@@ -136,19 +202,29 @@ define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) #0 {
   ret void
 }
 
-define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f64_v4f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
-; CHECK-NEXT:    and z0.d, z0.d, #0x8000000000000000
-; CHECK-NEXT:    ldp q2, q3, [x0]
-; CHECK-NEXT:    and z1.d, z1.d, #0x8000000000000000
-; CHECK-NEXT:    and z2.d, z2.d, #0x7fffffffffffffff
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    and z3.d, z3.d, #0x7fffffffffffffff
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f64_v4f64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x1]
+; SVE-NEXT:    and z0.d, z0.d, #0x8000000000000000
+; SVE-NEXT:    ldp q2, q3, [x0]
+; SVE-NEXT:    and z1.d, z1.d, #0x8000000000000000
+; SVE-NEXT:    and z2.d, z2.d, #0x7fffffffffffffff
+; SVE-NEXT:    orr z0.d, z2.d, z0.d
+; SVE-NEXT:    and z3.d, z3.d, #0x7fffffffffffffff
+; SVE-NEXT:    orr z1.d, z3.d, z1.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f64_v4f64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q1, q2, [x0]
+; SVE2-NEXT:    mov z0.d, #0x7fffffffffffffff
+; SVE2-NEXT:    ldp q3, q4, [x1]
+; SVE2-NEXT:    bsl z1.d, z1.d, z3.d, z0.d
+; SVE2-NEXT:    bsl z2.d, z2.d, z4.d, z0.d
+; SVE2-NEXT:    stp q1, q2, [x0]
+; SVE2-NEXT:    ret
   %a = load <4 x double>, ptr %ap
   %b = load <4 x double>, ptr %bp
   %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b)
@@ -158,19 +234,31 @@ define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) #0 {
 
 ;============ v2f32
 
-define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v2f32_v2f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x1]
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    ldr d1, [x0]
-; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
-; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
-; CHECK-NEXT:    and z1.s, z1.s, #0x7fffffff
-; CHECK-NEXT:    and z0.s, z0.s, #0x80000000
-; CHECK-NEXT:    orr z0.d, z1.d, z0.d
-; CHECK-NEXT:    str d0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v2f32_v2f64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr q0, [x1]
+; SVE-NEXT:    ptrue p0.d
+; SVE-NEXT:    ldr d1, [x0]
+; SVE-NEXT:    fcvt z0.s, p0/m, z0.d
+; SVE-NEXT:    uzp1 z0.s, z0.s, z0.s
+; SVE-NEXT:    and z1.s, z1.s, #0x7fffffff
+; SVE-NEXT:    and z0.s, z0.s, #0x80000000
+; SVE-NEXT:    orr z0.d, z1.d, z0.d
+; SVE-NEXT:    str d0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v2f32_v2f64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr q0, [x1]
+; SVE2-NEXT:    ptrue p0.d
+; SVE2-NEXT:    ldr d1, [x0]
+; SVE2-NEXT:    mov z2.s, #0x7fffffff
+; SVE2-NEXT:    fcvt z0.s, p0/m, z0.d
+; SVE2-NEXT:    uzp1 z0.s, z0.s, z0.s
+; SVE2-NEXT:    bsl z1.d, z1.d, z0.d, z2.d
+; SVE2-NEXT:    str d1, [x0]
+; SVE2-NEXT:    ret
   %a = load <2 x float>, ptr %ap
   %b = load <2 x double>, ptr %bp
   %tmp0 = fptrunc <2 x double> %b to <2 x float>
@@ -182,23 +270,39 @@ define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) #0 {
 ;============ v4f32
 
 ; SplitVecOp #1
-define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f32_v4f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    fcvt z1.s, p0/m, z1.d
-; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
-; CHECK-NEXT:    ldr q2, [x0]
-; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
-; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    splice z1.s, p0, z1.s, z0.s
-; CHECK-NEXT:    and z1.s, z1.s, #0x80000000
-; CHECK-NEXT:    and z2.s, z2.s, #0x7fffffff
-; CHECK-NEXT:    orr z0.d, z2.d, z1.d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f32_v4f64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q1, q0, [x1]
+; SVE-NEXT:    ptrue p0.d
+; SVE-NEXT:    fcvt z1.s, p0/m, z1.d
+; SVE-NEXT:    uzp1 z1.s, z1.s, z1.s
+; SVE-NEXT:    ldr q2, [x0]
+; SVE-NEXT:    fcvt z0.s, p0/m, z0.d
+; SVE-NEXT:    uzp1 z0.s, z0.s, z0.s
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    splice z1.s, p0, z1.s, z0.s
+; SVE-NEXT:    and z1.s, z1.s, #0x80000000
+; SVE-NEXT:    and z2.s, z2.s, #0x7fffffff
+; SVE-NEXT:    orr z0.d, z2.d, z1.d
+; SVE-NEXT:    str q0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f32_v4f64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q1, q0, [x1]
+; SVE2-NEXT:    ptrue p0.d
+; SVE2-NEXT:    fcvt z1.s, p0/m, z1.d
+; SVE2-NEXT:    uzp1 z1.s, z1.s, z1.s
+; SVE2-NEXT:    ldr q2, [x0]
+; SVE2-NEXT:    fcvt z0.s, p0/m, z0.d
+; SVE2-NEXT:    uzp1 z0.s, z0.s, z0.s
+; SVE2-NEXT:    ptrue p0.s, vl2
+; SVE2-NEXT:    splice z1.s, p0, z1.s, z0.s
+; SVE2-NEXT:    mov z0.s, #0x7fffffff
+; SVE2-NEXT:    bsl z2.d, z2.d, z1.d, z0.d
+; SVE2-NEXT:    str q2, [x0]
+; SVE2-NEXT:    ret
   %a = load <4 x float>, ptr %ap
   %b = load <4 x double>, ptr %bp
   %tmp0 = fptrunc <4 x double> %b to <4 x float>
@@ -209,18 +313,29 @@ define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) #0 {
 
 ;============ v2f64
 
-define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v2f64_v2f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    ld1w { z1.d }, p0/z, [x1]
-; CHECK-NEXT:    and z0.d, z0.d, #0x7fffffffffffffff
-; CHECK-NEXT:    fcvt z1.d, p0/m, z1.s
-; CHECK-NEXT:    and z1.d, z1.d, #0x8000000000000000
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v2f64_v2f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    ldr q0, [x0]
+; SVE-NEXT:    ld1w { z1.d }, p0/z, [x1]
+; SVE-NEXT:    and z0.d, z0.d, #0x7fffffffffffffff
+; SVE-NEXT:    fcvt z1.d, p0/m, z1.s
+; SVE-NEXT:    and z1.d, z1.d, #0x8000000000000000
+; SVE-NEXT:    orr z0.d, z0.d, z1.d
+; SVE-NEXT:    str q0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v2f64_v2f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ptrue p0.d, vl2
+; SVE2-NEXT:    ldr q0, [x0]
+; SVE2-NEXT:    ld1w { z1.d }, p0/z, [x1]
+; SVE2-NEXT:    mov z2.d, #0x7fffffffffffffff
+; SVE2-NEXT:    fcvt z1.d, p0/m, z1.s
+; SVE2-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT:    str q0, [x0]
+; SVE2-NEXT:    ret
   %a = load <2 x double>, ptr %ap
   %b = load < 2 x float>, ptr %bp
   %tmp0 = fpext <2 x float> %b to <2 x double>
@@ -232,24 +347,39 @@ define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) #0 {
 ;============ v4f64
 
 ; SplitVecRes mismatched
-define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f64_v4f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #2 // =0x2
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ld1w { z2.d }, p0/z, [x1, x8, lsl #2]
-; CHECK-NEXT:    ld1w { z3.d }, p0/z, [x1]
-; CHECK-NEXT:    and z0.d, z0.d, #0x7fffffffffffffff
-; CHECK-NEXT:    fcvt z3.d, p0/m, z3.s
-; CHECK-NEXT:    fcvt z2.d, p0/m, z2.s
-; CHECK-NEXT:    and z1.d, z1.d, #0x7fffffffffffffff
-; CHECK-NEXT:    and z3.d, z3.d, #0x8000000000000000
-; CHECK-NEXT:    and z2.d, z2.d, #0x8000000000000000
-; CHECK-NEXT:    orr z0.d, z0.d, z3.d
-; CHECK-NEXT:    orr z1.d, z1.d, z2.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f64_v4f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    mov x8, #2 // =0x2
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ld1w { z2.d }, p0/z, [x1, x8, lsl #2]
+; SVE-NEXT:    ld1w { z3.d }, p0/z, [x1]
+; SVE-NEXT:    and z0.d, z0.d, #0x7fffffffffffffff
+; SVE-NEXT:    fcvt z3.d, p0/m, z3.s
+; SVE-NEXT:    fcvt z2.d, p0/m, z2.s
+; SVE-NEXT:    and z1.d, z1.d, #0x7fffffffffffffff
+; SVE-NEXT:    and z3.d, z3.d, #0x8000000000000000
+; SVE-NEXT:    and z2.d, z2.d, #0x8000000000000000
+; SVE-NEXT:    orr z0.d, z0.d, z3.d
+; SVE-NEXT:    orr z1.d, z1.d, z2.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f64_v4f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    mov x8, #2 // =0x2
+; SVE2-NEXT:    ptrue p0.d, vl2
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    mov z4.d, #0x7fffffffffffffff
+; SVE2-NEXT:    ld1w { z2.d }, p0/z, [x1, x8, lsl #2]
+; SVE2-NEXT:    ld1w { z3.d }, p0/z, [x1]
+; SVE2-NEXT:    fcvt z3.d, p0/m, z3.s
+; SVE2-NEXT:    fcvt z2.d, p0/m, z2.s
+; SVE2-NEXT:    bsl z0.d, z0.d, z3.d, z4.d
+; SVE2-NEXT:    bsl z1.d, z1.d, z2.d, z4.d
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %a = load <4 x double>, ptr %ap
   %b = load <4 x float>, ptr %bp
   %tmp0 = fpext <4 x float> %b to <4 x double>
@@ -260,19 +390,31 @@ define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) #0 {
 
 ;============ v4f16
 
-define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f16_v4f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x1]
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    ldr d1, [x0]
-; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
-; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    and z1.h, z1.h, #0x7fff
-; CHECK-NEXT:    and z0.h, z0.h, #0x8000
-; CHECK-NEXT:    orr z0.d, z1.d, z0.d
-; CHECK-NEXT:    str d0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f16_v4f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldr q0, [x1]
+; SVE-NEXT:    ptrue p0.s
+; SVE-NEXT:    ldr d1, [x0]
+; SVE-NEXT:    fcvt z0.h, p0/m, z0.s
+; SVE-NEXT:    uzp1 z0.h, z0.h, z0.h
+; SVE-NEXT:    and z1.h, z1.h, #0x7fff
+; SVE-NEXT:    and z0.h, z0.h, #0x8000
+; SVE-NEXT:    orr z0.d, z1.d, z0.d
+; SVE-NEXT:    str d0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f16_v4f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldr q0, [x1]
+; SVE2-NEXT:    ptrue p0.s
+; SVE2-NEXT:    ldr d1, [x0]
+; SVE2-NEXT:    mov z2.h, #32767 // =0x7fff
+; SVE2-NEXT:    fcvt z0.h, p0/m, z0.s
+; SVE2-NEXT:    uzp1 z0.h, z0.h, z0.h
+; SVE2-NEXT:    bsl z1.d, z1.d, z0.d, z2.d
+; SVE2-NEXT:    str d1, [x0]
+; SVE2-NEXT:    ret
   %a = load <4 x half>, ptr %ap
   %b = load <4 x float>, ptr %bp
   %tmp0 = fptrunc <4 x float> %b to <4 x half>
@@ -281,30 +423,53 @@ define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) #0 {
   ret void
 }
 
-define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v4f16_v4f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    fcvt h3, d1
-; CHECK-NEXT:    mov z1.d, z1.d[1]
-; CHECK-NEXT:    fcvt h1, d1
-; CHECK-NEXT:    fcvt h2, d0
-; CHECK-NEXT:    mov z0.d, z0.d[1]
-; CHECK-NEXT:    fcvt h0, d0
-; CHECK-NEXT:    ldr d4, [x0]
-; CHECK-NEXT:    str h3, [sp, #8]
-; CHECK-NEXT:    str h1, [sp, #10]
-; CHECK-NEXT:    str h2, [sp, #12]
-; CHECK-NEXT:    and z4.h, z4.h, #0x7fff
-; CHECK-NEXT:    str h0, [sp, #14]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    and z0.h, z0.h, #0x8000
-; CHECK-NEXT:    orr z0.d, z4.d, z0.d
-; CHECK-NEXT:    str d0, [x0]
-; CHECK-NEXT:    add sp, sp, #16
-; CHECK-NEXT:    ret
+define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v4f16_v4f64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    sub sp, sp, #16
+; SVE-NEXT:    .cfi_def_cfa_offset 16
+; SVE-NEXT:    ldp q1, q0, [x1]
+; SVE-NEXT:    fcvt h3, d1
+; SVE-NEXT:    mov z1.d, z1.d[1]
+; SVE-NEXT:    fcvt h1, d1
+; SVE-NEXT:    fcvt h2, d0
+; SVE-NEXT:    mov z0.d, z0.d[1]
+; SVE-NEXT:    fcvt h0, d0
+; SVE-NEXT:    ldr d4, [x0]
+; SVE-NEXT:    str h3, [sp, #8]
+; SVE-NEXT:    str h1, [sp, #10]
+; SVE-NEXT:    str h2, [sp, #12]
+; SVE-NEXT:    and z4.h, z4.h, #0x7fff
+; SVE-NEXT:    str h0, [sp, #14]
+; SVE-NEXT:    ldr d0, [sp, #8]
+; SVE-NEXT:    and z0.h, z0.h, #0x8000
+; SVE-NEXT:    orr z0.d, z4.d, z0.d
+; SVE-NEXT:    str d0, [x0]
+; SVE-NEXT:    add sp, sp, #16
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v4f16_v4f64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    sub sp, sp, #16
+; SVE2-NEXT:    .cfi_def_cfa_offset 16
+; SVE2-NEXT:    ldp q1, q0, [x1]
+; SVE2-NEXT:    fcvt h3, d1
+; SVE2-NEXT:    mov z1.d, z1.d[1]
+; SVE2-NEXT:    fcvt h1, d1
+; SVE2-NEXT:    fcvt h2, d0
+; SVE2-NEXT:    mov z0.d, z0.d[1]
+; SVE2-NEXT:    fcvt h0, d0
+; SVE2-NEXT:    ldr d4, [x0]
+; SVE2-NEXT:    str h3, [sp, #8]
+; SVE2-NEXT:    str h1, [sp, #10]
+; SVE2-NEXT:    mov z1.h, #32767 // =0x7fff
+; SVE2-NEXT:    str h2, [sp, #12]
+; SVE2-NEXT:    str h0, [sp, #14]
+; SVE2-NEXT:    ldr d0, [sp, #8]
+; SVE2-NEXT:    bsl z4.d, z4.d, z0.d, z1.d
+; SVE2-NEXT:    str d4, [x0]
+; SVE2-NEXT:    add sp, sp, #16
+; SVE2-NEXT:    ret
   %a = load <4 x half>, ptr %ap
   %b = load <4 x double>, ptr %bp
   %tmp0 = fptrunc <4 x double> %b to <4 x half>
@@ -315,23 +480,39 @@ define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) #0 {
 
 ;============ v8f16
 
-define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) #0 {
-; CHECK-LABEL: test_copysign_v8f16_v8f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    fcvt z1.h, p0/m, z1.s
-; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
-; CHECK-NEXT:    ldr q2, [x0]
-; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
-; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    splice z1.h, p0, z1.h, z0.h
-; CHECK-NEXT:    and z1.h, z1.h, #0x8000
-; CHECK-NEXT:    and z2.h, z2.h, #0x7fff
-; CHECK-NEXT:    orr z0.d, z2.d, z1.d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
+define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_v8f16_v8f32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q1, q0, [x1]
+; SVE-NEXT:    ptrue p0.s
+; SVE-NEXT:    fcvt z1.h, p0/m, z1.s
+; SVE-NEXT:    uzp1 z1.h, z1.h, z1.h
+; SVE-NEXT:    ldr q2, [x0]
+; SVE-NEXT:    fcvt z0.h, p0/m, z0.s
+; SVE-NEXT:    uzp1 z0.h, z0.h, z0.h
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    splice z1.h, p0, z1.h, z0.h
+; SVE-NEXT:    and z1.h, z1.h, #0x8000
+; SVE-NEXT:    and z2.h, z2.h, #0x7fff
+; SVE-NEXT:    orr z0.d, z2.d, z1.d
+; SVE-NEXT:    str q0, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: test_copysign_v8f16_v8f32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q1, q0, [x1]
+; SVE2-NEXT:    ptrue p0.s
+; SVE2-NEXT:    fcvt z1.h, p0/m, z1.s
+; SVE2-NEXT:    uzp1 z1.h, z1.h, z1.h
+; SVE2-NEXT:    ldr q2, [x0]
+; SVE2-NEXT:    fcvt z0.h, p0/m, z0.s
+; SVE2-NEXT:    uzp1 z0.h, z0.h, z0.h
+; SVE2-NEXT:    ptrue p0.h, vl4
+; SVE2-NEXT:    splice z1.h, p0, z1.h, z0.h
+; SVE2-NEXT:    mov z0.h, #32767 // =0x7fff
+; SVE2-NEXT:    bsl z2.d, z2.d, z1.d, z0.d
+; SVE2-NEXT:    str q2, [x0]
+; SVE2-NEXT:    ret
   %a = load <8 x half>, ptr %ap
   %b = load <8 x float>, ptr %bp
   %tmp0 = fptrunc <8 x float> %b to <8 x half>
@@ -350,5 +531,5 @@ declare <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) #0
 
 declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0
 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0
-
-attributes #0 = { "target-features"="+sve" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
index cbc34e384ff9e..ccb68a808e4b4 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FADD
 ;
 
-define <2 x half> @fadd_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
+define <2 x half> @fadd_v2f16(<2 x half> %op1, <2 x half> %op2) {
 ; CHECK-LABEL: fadd_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -20,7 +20,7 @@ define <2 x half> @fadd_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fadd_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -33,7 +33,7 @@ define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fadd_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -46,7 +46,7 @@ define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fadd_v16f16(ptr %a, ptr %b) #0 {
+define void @fadd_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -63,7 +63,7 @@ define void @fadd_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fadd_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -76,7 +76,7 @@ define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fadd_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -89,7 +89,7 @@ define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fadd_v8f32(ptr %a, ptr %b) #0 {
+define void @fadd_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -106,7 +106,7 @@ define void @fadd_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fadd_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -119,7 +119,7 @@ define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fadd_v4f64(ptr %a, ptr %b) #0 {
+define void @fadd_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -140,7 +140,7 @@ define void @fadd_v4f64(ptr %a, ptr %b) #0 {
 ; FDIV
 ;
 
-define <2 x half> @fdiv_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
+define <2 x half> @fdiv_v2f16(<2 x half> %op1, <2 x half> %op2) {
 ; CHECK-LABEL: fdiv_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -153,7 +153,7 @@ define <2 x half> @fdiv_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fdiv_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -166,7 +166,7 @@ define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fdiv_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -179,7 +179,7 @@ define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fdiv_v16f16(ptr %a, ptr %b) #0 {
+define void @fdiv_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fdiv_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -196,7 +196,7 @@ define void @fdiv_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fdiv_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -209,7 +209,7 @@ define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fdiv_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -222,7 +222,7 @@ define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fdiv_v8f32(ptr %a, ptr %b) #0 {
+define void @fdiv_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fdiv_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -239,7 +239,7 @@ define void @fdiv_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fdiv_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -252,7 +252,7 @@ define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fdiv_v4f64(ptr %a, ptr %b) #0 {
+define void @fdiv_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fdiv_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -273,7 +273,7 @@ define void @fdiv_v4f64(ptr %a, ptr %b) #0 {
 ; FMA
 ;
 
-define <2 x half> @fma_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3) #0 {
+define <2 x half> @fma_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3) {
 ; CHECK-LABEL: fma_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -287,7 +287,7 @@ define <2 x half> @fma_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3)
   ret <2 x half> %res
 }
 
-define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) #0 {
+define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) {
 ; CHECK-LABEL: fma_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -301,7 +301,7 @@ define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3)
   ret <4 x half> %res
 }
 
-define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) #0 {
+define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) {
 ; CHECK-LABEL: fma_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -315,7 +315,7 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3)
   ret <8 x half> %res
 }
 
-define void @fma_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fma_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fma_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -335,7 +335,7 @@ define void @fma_v16f16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) #0 {
+define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) {
 ; CHECK-LABEL: fma_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -349,7 +349,7 @@ define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %o
   ret <2 x float> %res
 }
 
-define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) #0 {
+define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) {
 ; CHECK-LABEL: fma_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -363,7 +363,7 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o
   ret <4 x float> %res
 }
 
-define void @fma_v8f32(ptr %a, ptr %b, ptr %c) #0 {
+define void @fma_v8f32(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fma_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -383,7 +383,7 @@ define void @fma_v8f32(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) #0 {
+define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) {
 ; CHECK-LABEL: fma_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -397,7 +397,7 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double
   ret <2 x double> %res
 }
 
-define void @fma_v4f64(ptr %a, ptr %b, ptr %c) #0 {
+define void @fma_v4f64(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fma_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -421,7 +421,7 @@ define void @fma_v4f64(ptr %a, ptr %b, ptr %c) #0 {
 ; FMUL
 ;
 
-define <2 x half> @fmul_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
+define <2 x half> @fmul_v2f16(<2 x half> %op1, <2 x half> %op2) {
 ; CHECK-LABEL: fmul_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -434,7 +434,7 @@ define <2 x half> @fmul_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fmul_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -447,7 +447,7 @@ define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fmul_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -460,7 +460,7 @@ define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fmul_v16f16(ptr %a, ptr %b) #0 {
+define void @fmul_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmul_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -477,7 +477,7 @@ define void @fmul_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fmul_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -490,7 +490,7 @@ define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fmul_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -503,7 +503,7 @@ define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fmul_v8f32(ptr %a, ptr %b) #0 {
+define void @fmul_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmul_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -520,7 +520,7 @@ define void @fmul_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fmul_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -533,7 +533,7 @@ define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fmul_v4f64(ptr %a, ptr %b) #0 {
+define void @fmul_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmul_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -554,7 +554,7 @@ define void @fmul_v4f64(ptr %a, ptr %b) #0 {
 ; FNEG
 ;
 
-define <2 x half> @fneg_v2f16(<2 x half> %op) #0 {
+define <2 x half> @fneg_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: fneg_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -566,7 +566,7 @@ define <2 x half> @fneg_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fneg_v4f16(<4 x half> %op) #0 {
+define <4 x half> @fneg_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: fneg_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -578,7 +578,7 @@ define <4 x half> @fneg_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fneg_v8f16(<8 x half> %op) #0 {
+define <8 x half> @fneg_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: fneg_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -590,7 +590,7 @@ define <8 x half> @fneg_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @fneg_v16f16(ptr %a, ptr %b) #0 {
+define void @fneg_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fneg_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -605,7 +605,7 @@ define void @fneg_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fneg_v2f32(<2 x float> %op) #0 {
+define <2 x float> @fneg_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: fneg_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -617,7 +617,7 @@ define <2 x float> @fneg_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fneg_v4f32(<4 x float> %op) #0 {
+define <4 x float> @fneg_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: fneg_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -629,7 +629,7 @@ define <4 x float> @fneg_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @fneg_v8f32(ptr %a) #0 {
+define void @fneg_v8f32(ptr %a) {
 ; CHECK-LABEL: fneg_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -644,7 +644,7 @@ define void @fneg_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <2 x double> @fneg_v2f64(<2 x double> %op) #0 {
+define <2 x double> @fneg_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: fneg_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -656,7 +656,7 @@ define <2 x double> @fneg_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @fneg_v4f64(ptr %a) #0 {
+define void @fneg_v4f64(ptr %a) {
 ; CHECK-LABEL: fneg_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -675,7 +675,7 @@ define void @fneg_v4f64(ptr %a) #0 {
 ; FSQRT
 ;
 
-define <2 x half> @fsqrt_v2f16(<2 x half> %op) #0 {
+define <2 x half> @fsqrt_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: fsqrt_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -687,7 +687,7 @@ define <2 x half> @fsqrt_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fsqrt_v4f16(<4 x half> %op) #0 {
+define <4 x half> @fsqrt_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: fsqrt_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -699,7 +699,7 @@ define <4 x half> @fsqrt_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fsqrt_v8f16(<8 x half> %op) #0 {
+define <8 x half> @fsqrt_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: fsqrt_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -711,7 +711,7 @@ define <8 x half> @fsqrt_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @fsqrt_v16f16(ptr %a, ptr %b) #0 {
+define void @fsqrt_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fsqrt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -726,7 +726,7 @@ define void @fsqrt_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fsqrt_v2f32(<2 x float> %op) #0 {
+define <2 x float> @fsqrt_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: fsqrt_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -738,7 +738,7 @@ define <2 x float> @fsqrt_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fsqrt_v4f32(<4 x float> %op) #0 {
+define <4 x float> @fsqrt_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: fsqrt_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -750,7 +750,7 @@ define <4 x float> @fsqrt_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @fsqrt_v8f32(ptr %a) #0 {
+define void @fsqrt_v8f32(ptr %a) {
 ; CHECK-LABEL: fsqrt_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -765,7 +765,7 @@ define void @fsqrt_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <2 x double> @fsqrt_v2f64(<2 x double> %op) #0 {
+define <2 x double> @fsqrt_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: fsqrt_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -777,7 +777,7 @@ define <2 x double> @fsqrt_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @fsqrt_v4f64(ptr %a) #0 {
+define void @fsqrt_v4f64(ptr %a) {
 ; CHECK-LABEL: fsqrt_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -796,7 +796,7 @@ define void @fsqrt_v4f64(ptr %a) #0 {
 ; FSUB
 ;
 
-define <2 x half> @fsub_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
+define <2 x half> @fsub_v2f16(<2 x half> %op1, <2 x half> %op2) {
 ; CHECK-LABEL: fsub_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -809,7 +809,7 @@ define <2 x half> @fsub_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fsub_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -822,7 +822,7 @@ define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fsub_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -835,7 +835,7 @@ define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fsub_v16f16(ptr %a, ptr %b) #0 {
+define void @fsub_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fsub_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -852,7 +852,7 @@ define void @fsub_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fsub_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -865,7 +865,7 @@ define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fsub_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -878,7 +878,7 @@ define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fsub_v8f32(ptr %a, ptr %b) #0 {
+define void @fsub_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fsub_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -895,7 +895,7 @@ define void @fsub_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fsub_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -908,7 +908,7 @@ define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fsub_v4f64(ptr %a, ptr %b) #0 {
+define void @fsub_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fsub_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -929,7 +929,7 @@ define void @fsub_v4f64(ptr %a, ptr %b) #0 {
 ; FABS
 ;
 
-define <2 x half> @fabs_v2f16(<2 x half> %op) #0 {
+define <2 x half> @fabs_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: fabs_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -941,7 +941,7 @@ define <2 x half> @fabs_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @fabs_v4f16(<4 x half> %op) #0 {
+define <4 x half> @fabs_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: fabs_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -953,7 +953,7 @@ define <4 x half> @fabs_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fabs_v8f16(<8 x half> %op) #0 {
+define <8 x half> @fabs_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: fabs_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -965,7 +965,7 @@ define <8 x half> @fabs_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @fabs_v16f16(ptr %a) #0 {
+define void @fabs_v16f16(ptr %a) {
 ; CHECK-LABEL: fabs_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -980,7 +980,7 @@ define void @fabs_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @fabs_v2f32(<2 x float> %op) #0 {
+define <2 x float> @fabs_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: fabs_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -992,7 +992,7 @@ define <2 x float> @fabs_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fabs_v4f32(<4 x float> %op) #0 {
+define <4 x float> @fabs_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: fabs_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1004,7 +1004,7 @@ define <4 x float> @fabs_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @fabs_v8f32(ptr %a) #0 {
+define void @fabs_v8f32(ptr %a) {
 ; CHECK-LABEL: fabs_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1019,7 +1019,7 @@ define void @fabs_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <2 x double> @fabs_v2f64(<2 x double> %op) #0 {
+define <2 x double> @fabs_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: fabs_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1031,7 +1031,7 @@ define <2 x double> @fabs_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @fabs_v4f64(ptr %a) #0 {
+define void @fabs_v4f64(ptr %a) {
 ; CHECK-LABEL: fabs_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1046,8 +1046,6 @@ define void @fabs_v4f64(ptr %a) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare <2 x half> @llvm.fma.v2f16(<2 x half>, <2 x half>, <2 x half>)
 declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
index c4f4eef630688..cba2c82558e11 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FCMP OEQ
 ;
 
-define <2 x i16> @fcmp_oeq_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
+define <2 x i16> @fcmp_oeq_v2f16(<2 x half> %op1, <2 x half> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -23,7 +23,7 @@ define <2 x i16> @fcmp_oeq_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
   ret <2 x i16> %sext
 }
 
-define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -38,7 +38,7 @@ define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x i16> %sext
 }
 
-define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl8
@@ -53,7 +53,7 @@ define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x i16> %sext
 }
 
-define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_oeq_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -73,7 +73,7 @@ define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl2
@@ -88,7 +88,7 @@ define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x i32> %sext
 }
 
-define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl4
@@ -103,7 +103,7 @@ define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x i32> %sext
 }
 
-define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_oeq_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -123,7 +123,7 @@ define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl1
@@ -138,7 +138,7 @@ define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
   ret <1 x i64> %sext
 }
 
-define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fcmp_oeq_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -153,7 +153,7 @@ define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x i64> %sext
 }
 
-define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_oeq_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -177,7 +177,7 @@ define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP UEQ
 ;
 
-define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ueq_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -205,7 +205,7 @@ define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP ONE
 ;
 
-define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_one_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -233,7 +233,7 @@ define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP UNE
 ;
 
-define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_une_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -257,7 +257,7 @@ define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP OGT
 ;
 
-define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ogt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -281,7 +281,7 @@ define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP UGT
 ;
 
-define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ugt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -308,7 +308,7 @@ define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP OLT
 ;
 
-define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_olt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -332,7 +332,7 @@ define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP ULT
 ;
 
-define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ult_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -359,7 +359,7 @@ define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP OGE
 ;
 
-define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_oge_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -383,7 +383,7 @@ define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP UGE
 ;
 
-define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_uge_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -410,7 +410,7 @@ define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP OLE
 ;
 
-define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ole_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -434,7 +434,7 @@ define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP ULE
 ;
 
-define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ule_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -461,7 +461,7 @@ define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP UNO
 ;
 
-define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_uno_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -485,7 +485,7 @@ define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP ORD
 ;
 
-define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ord_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -512,7 +512,7 @@ define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP EQ
 ;
 
-define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_eq_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -536,7 +536,7 @@ define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP NE
 ;
 
-define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ne_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -560,7 +560,7 @@ define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP GT
 ;
 
-define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_gt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -584,7 +584,7 @@ define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP LT
 ;
 
-define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_lt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -608,7 +608,7 @@ define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP GE
 ;
 
-define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_ge_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -632,7 +632,7 @@ define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; FCMP LE
 ;
 
-define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fcmp_le_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -651,5 +651,3 @@ define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) #0 {
   store <16 x i16> %sext, ptr %c
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
index 3215802062f28..8e2805ad8fbbd 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; Ensure we don't crash when trying to combine fp<->int conversions
-define void @fp_convert_combine_crash(ptr %a, ptr %b) #0 {
+define void @fp_convert_combine_crash(ptr %a, ptr %b) {
 ; CHECK-LABEL: fp_convert_combine_crash:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -23,5 +23,3 @@ define void @fp_convert_combine_crash(ptr %a, ptr %b) #0 {
   store <8 x i32> %vcvt.i, ptr %b
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
index ec6448f60227e..549d09f15122d 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FCVT H -> S; Without load instr
 ;
 
-define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) #0 {
+define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f16_to_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -21,7 +21,7 @@ define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) #0 {
+define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f16_to_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -35,7 +35,7 @@ define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) #0 {
+define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v8f16_to_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -52,7 +52,7 @@ define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) #0 {
+define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v16f16_to_v16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -82,7 +82,7 @@ define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) #0 {
 ; FCVT H -> S
 ;
 
-define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) #0 {
+define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f16_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl2
@@ -96,7 +96,7 @@ define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) #0 {
+define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f16_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl4
@@ -110,7 +110,7 @@ define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) #0 {
+define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v8f16_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #4 // =0x4
@@ -127,7 +127,7 @@ define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) #0 {
+define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v16f16_v16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #8 // =0x8
@@ -157,7 +157,7 @@ define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) #0 {
 ; FCVT H -> D
 ;
 
-define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v1f16_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr h0, [x0]
@@ -170,7 +170,7 @@ define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f16_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -184,7 +184,7 @@ define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f16_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #2 // =0x2
@@ -201,7 +201,7 @@ define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v8f16_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #4 // =0x4
@@ -227,7 +227,7 @@ define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v16f16_v16f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x9, #14 // =0xe
@@ -275,7 +275,7 @@ define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) #0 {
 ; FCVT S -> D
 ;
 
-define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v1f32_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr s0, [x0]
@@ -288,7 +288,7 @@ define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f32_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -302,7 +302,7 @@ define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f32_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #2 // =0x2
@@ -319,7 +319,7 @@ define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) #0 {
+define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v8f32_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #4 // =0x4
@@ -349,7 +349,7 @@ define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) #0 {
 ; FCVT S -> H
 ;
 
-define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) #0 {
+define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f32_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -363,7 +363,7 @@ define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) #0 {
+define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f32_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -377,7 +377,7 @@ define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) #0 {
+define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v8f32_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -398,7 +398,7 @@ define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) #0 {
 ; FCVT D -> H
 ;
 
-define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) #0 {
+define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v1f64_v1f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -412,7 +412,7 @@ define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) #0 {
+define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f64_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -426,7 +426,7 @@ define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) #0 {
+define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f64_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -447,7 +447,7 @@ define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) #0 {
 ; FCVT D -> S
 ;
 
-define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) #0 {
+define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) {
 ; CHECK-LABEL: fcvt_v1f64_v1f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -460,7 +460,7 @@ define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) #0 {
+define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) {
 ; CHECK-LABEL: fcvt_v2f64_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -473,7 +473,7 @@ define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) #0 {
   ret void
 }
 
-define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) #0 {
+define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvt_v4f64_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -489,5 +489,3 @@ define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) #0 {
   store <4 x float> %res, ptr %b
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
index 5c96c56f1d3e6..db8000f9fe6d5 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FMA
 ;
 
-define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) #0 {
+define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) {
 ; CHECK-LABEL: fma_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -22,7 +22,7 @@ define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3)
   ret <4 x half> %res
 }
 
-define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) #0 {
+define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) {
 ; CHECK-LABEL: fma_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -37,7 +37,7 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3)
   ret <8 x half> %res
 }
 
-define void @fma_v16f16(ptr %a, ptr %b, ptr %c) #0 {
+define void @fma_v16f16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fma_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -58,7 +58,7 @@ define void @fma_v16f16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) #0 {
+define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) {
 ; CHECK-LABEL: fma_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -73,7 +73,7 @@ define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %o
   ret <2 x float> %res
 }
 
-define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) #0 {
+define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) {
 ; CHECK-LABEL: fma_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -88,7 +88,7 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o
   ret <4 x float> %res
 }
 
-define void @fma_v8f32(ptr %a, ptr %b, ptr %c) #0 {
+define void @fma_v8f32(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fma_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -109,7 +109,7 @@ define void @fma_v8f32(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double> %op3) #0 {
+define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double> %op3) {
 ; CHECK-LABEL: fma_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -122,7 +122,7 @@ define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double
   ret <1 x double> %res
 }
 
-define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) #0 {
+define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) {
 ; CHECK-LABEL: fma_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -137,7 +137,7 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double
   ret <2 x double> %res
 }
 
-define void @fma_v4f64(ptr %a, ptr %b, ptr %c) #0 {
+define void @fma_v4f64(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: fma_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
@@ -157,5 +157,3 @@ define void @fma_v4f64(ptr %a, ptr %b, ptr %c) #0 {
   store <4 x double> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
index 5516aa94f15ab..47292ee0392d2 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FMAXNM
 ;
 
-define <4 x half> @fmaxnm_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fmaxnm_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fmaxnm_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -20,7 +20,7 @@ define <4 x half> @fmaxnm_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fmaxnm_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -33,7 +33,7 @@ define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fmaxnm_v16f16(ptr %a, ptr %b) #0 {
+define void @fmaxnm_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmaxnm_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -50,7 +50,7 @@ define void @fmaxnm_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fmaxnm_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fmaxnm_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fmaxnm_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -63,7 +63,7 @@ define <2 x float> @fmaxnm_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fmaxnm_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -76,7 +76,7 @@ define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fmaxnm_v8f32(ptr %a, ptr %b) #0 {
+define void @fmaxnm_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmaxnm_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -93,7 +93,7 @@ define void @fmaxnm_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) {
 ; CHECK-LABEL: fmaxnm_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -104,7 +104,7 @@ define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fmaxnm_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -117,7 +117,7 @@ define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fmaxnm_v4f64(ptr %a, ptr %b) #0 {
+define void @fmaxnm_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmaxnm_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -138,7 +138,7 @@ define void @fmaxnm_v4f64(ptr %a, ptr %b) #0 {
 ; FMINNM
 ;
 
-define <4 x half> @fminnm_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fminnm_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fminnm_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -151,7 +151,7 @@ define <4 x half> @fminnm_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fminnm_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -164,7 +164,7 @@ define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fminnm_v16f16(ptr %a, ptr %b) #0 {
+define void @fminnm_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fminnm_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -181,7 +181,7 @@ define void @fminnm_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fminnm_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fminnm_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fminnm_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -194,7 +194,7 @@ define <2 x float> @fminnm_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fminnm_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -207,7 +207,7 @@ define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fminnm_v8f32(ptr %a, ptr %b) #0 {
+define void @fminnm_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fminnm_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -224,7 +224,7 @@ define void @fminnm_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) {
 ; CHECK-LABEL: fminnm_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -235,7 +235,7 @@ define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fminnm_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -248,7 +248,7 @@ define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fminnm_v4f64(ptr %a, ptr %b) #0 {
+define void @fminnm_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fminnm_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -269,7 +269,7 @@ define void @fminnm_v4f64(ptr %a, ptr %b) #0 {
 ; FMAX
 ;
 
-define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fmax_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -282,7 +282,7 @@ define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fmax_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -295,7 +295,7 @@ define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fmax_v16f16(ptr %a, ptr %b) #0 {
+define void @fmax_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmax_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -312,7 +312,7 @@ define void @fmax_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fmax_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -325,7 +325,7 @@ define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fmax_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -338,7 +338,7 @@ define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fmax_v8f32(ptr %a, ptr %b) #0 {
+define void @fmax_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmax_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -355,7 +355,7 @@ define void @fmax_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) {
 ; CHECK-LABEL: fmax_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -366,7 +366,7 @@ define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fmax_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -379,7 +379,7 @@ define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fmax_v4f64(ptr %a, ptr %b) #0 {
+define void @fmax_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmax_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -400,7 +400,7 @@ define void @fmax_v4f64(ptr %a, ptr %b) #0 {
 ; FMIN
 ;
 
-define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: fmin_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -413,7 +413,7 @@ define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: fmin_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -426,7 +426,7 @@ define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
   ret <8 x half> %res
 }
 
-define void @fmin_v16f16(ptr %a, ptr %b) #0 {
+define void @fmin_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmin_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -443,7 +443,7 @@ define void @fmin_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: fmin_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -456,7 +456,7 @@ define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: fmin_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -469,7 +469,7 @@ define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
   ret <4 x float> %res
 }
 
-define void @fmin_v8f32(ptr %a, ptr %b) #0 {
+define void @fmin_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmin_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -486,7 +486,7 @@ define void @fmin_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) {
 ; CHECK-LABEL: fmin_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -497,7 +497,7 @@ define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: fmin_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -510,7 +510,7 @@ define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
   ret <2 x double> %res
 }
 
-define void @fmin_v4f64(ptr %a, ptr %b) #0 {
+define void @fmin_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fmin_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -527,8 +527,6 @@ define void @fmin_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare <4 x half> @llvm.minnum.v4f16(<4 x half>, <4 x half>)
 declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>)
 declare <16 x half> @llvm.minnum.v16f16(<16 x half>, <16 x half>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
index 77a448c934af9..8675477a7d60e 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FADDA
 ;
 
-define half @fadda_v4f16(half %start, <4 x half> %a) #0 {
+define half @fadda_v4f16(half %start, <4 x half> %a) {
 ; CHECK-LABEL: fadda_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -20,7 +20,7 @@ define half @fadda_v4f16(half %start, <4 x half> %a) #0 {
   ret half %res
 }
 
-define half @fadda_v8f16(half %start, <8 x half> %a) #0 {
+define half @fadda_v8f16(half %start, <8 x half> %a) {
 ; CHECK-LABEL: fadda_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -33,7 +33,7 @@ define half @fadda_v8f16(half %start, <8 x half> %a) #0 {
   ret half %res
 }
 
-define half @fadda_v16f16(half %start, ptr %a) #0 {
+define half @fadda_v16f16(half %start, ptr %a) {
 ; CHECK-LABEL: fadda_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x0]
@@ -48,7 +48,7 @@ define half @fadda_v16f16(half %start, ptr %a) #0 {
   ret half %res
 }
 
-define float @fadda_v2f32(float %start, <2 x float> %a) #0 {
+define float @fadda_v2f32(float %start, <2 x float> %a) {
 ; CHECK-LABEL: fadda_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -61,7 +61,7 @@ define float @fadda_v2f32(float %start, <2 x float> %a) #0 {
   ret float %res
 }
 
-define float @fadda_v4f32(float %start, <4 x float> %a) #0 {
+define float @fadda_v4f32(float %start, <4 x float> %a) {
 ; CHECK-LABEL: fadda_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -74,7 +74,7 @@ define float @fadda_v4f32(float %start, <4 x float> %a) #0 {
   ret float %res
 }
 
-define float @fadda_v8f32(float %start, ptr %a) #0 {
+define float @fadda_v8f32(float %start, ptr %a) {
 ; CHECK-LABEL: fadda_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x0]
@@ -89,7 +89,7 @@ define float @fadda_v8f32(float %start, ptr %a) #0 {
   ret float %res
 }
 
-define double @fadda_v1f64(double %start, <1 x double> %a) #0 {
+define double @fadda_v1f64(double %start, <1 x double> %a) {
 ; CHECK-LABEL: fadda_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -99,7 +99,7 @@ define double @fadda_v1f64(double %start, <1 x double> %a) #0 {
   ret double %res
 }
 
-define double @fadda_v2f64(double %start, <2 x double> %a) #0 {
+define double @fadda_v2f64(double %start, <2 x double> %a) {
 ; CHECK-LABEL: fadda_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -112,7 +112,7 @@ define double @fadda_v2f64(double %start, <2 x double> %a) #0 {
   ret double %res
 }
 
-define double @fadda_v4f64(double %start, ptr %a) #0 {
+define double @fadda_v4f64(double %start, ptr %a) {
 ; CHECK-LABEL: fadda_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x0]
@@ -131,7 +131,7 @@ define double @fadda_v4f64(double %start, ptr %a) #0 {
 ; FADDV
 ;
 
-define half @faddv_v4f16(half %start, <4 x half> %a) #0 {
+define half @faddv_v4f16(half %start, <4 x half> %a) {
 ; CHECK-LABEL: faddv_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -143,7 +143,7 @@ define half @faddv_v4f16(half %start, <4 x half> %a) #0 {
   ret half %res
 }
 
-define half @faddv_v8f16(half %start, <8 x half> %a) #0 {
+define half @faddv_v8f16(half %start, <8 x half> %a) {
 ; CHECK-LABEL: faddv_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -155,7 +155,7 @@ define half @faddv_v8f16(half %start, <8 x half> %a) #0 {
   ret half %res
 }
 
-define half @faddv_v16f16(half %start, ptr %a) #0 {
+define half @faddv_v16f16(half %start, ptr %a) {
 ; CHECK-LABEL: faddv_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q1, [x0]
@@ -169,7 +169,7 @@ define half @faddv_v16f16(half %start, ptr %a) #0 {
   ret half %res
 }
 
-define float @faddv_v2f32(float %start, <2 x float> %a) #0 {
+define float @faddv_v2f32(float %start, <2 x float> %a) {
 ; CHECK-LABEL: faddv_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -181,7 +181,7 @@ define float @faddv_v2f32(float %start, <2 x float> %a) #0 {
   ret float %res
 }
 
-define float @faddv_v4f32(float %start, <4 x float> %a) #0 {
+define float @faddv_v4f32(float %start, <4 x float> %a) {
 ; CHECK-LABEL: faddv_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -193,7 +193,7 @@ define float @faddv_v4f32(float %start, <4 x float> %a) #0 {
   ret float %res
 }
 
-define float @faddv_v8f32(float %start, ptr %a) #0 {
+define float @faddv_v8f32(float %start, ptr %a) {
 ; CHECK-LABEL: faddv_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q1, [x0]
@@ -207,7 +207,7 @@ define float @faddv_v8f32(float %start, ptr %a) #0 {
   ret float %res
 }
 
-define double @faddv_v1f64(double %start, <1 x double> %a) #0 {
+define double @faddv_v1f64(double %start, <1 x double> %a) {
 ; CHECK-LABEL: faddv_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -217,7 +217,7 @@ define double @faddv_v1f64(double %start, <1 x double> %a) #0 {
   ret double %res
 }
 
-define double @faddv_v2f64(double %start, <2 x double> %a) #0 {
+define double @faddv_v2f64(double %start, <2 x double> %a) {
 ; CHECK-LABEL: faddv_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -229,7 +229,7 @@ define double @faddv_v2f64(double %start, <2 x double> %a) #0 {
   ret double %res
 }
 
-define double @faddv_v4f64(double %start, ptr %a) #0 {
+define double @faddv_v4f64(double %start, ptr %a) {
 ; CHECK-LABEL: faddv_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q1, [x0]
@@ -247,7 +247,7 @@ define double @faddv_v4f64(double %start, ptr %a) #0 {
 ; FMAXNMV
 ;
 
-define half @fmaxv_v4f16(<4 x half> %a) #0 {
+define half @fmaxv_v4f16(<4 x half> %a) {
 ; CHECK-LABEL: fmaxv_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -259,7 +259,7 @@ define half @fmaxv_v4f16(<4 x half> %a) #0 {
   ret half %res
 }
 
-define half @fmaxv_v8f16(<8 x half> %a) #0 {
+define half @fmaxv_v8f16(<8 x half> %a) {
 ; CHECK-LABEL: fmaxv_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -271,7 +271,7 @@ define half @fmaxv_v8f16(<8 x half> %a) #0 {
   ret half %res
 }
 
-define half @fmaxv_v16f16(ptr %a) #0 {
+define half @fmaxv_v16f16(ptr %a) {
 ; CHECK-LABEL: fmaxv_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -285,7 +285,7 @@ define half @fmaxv_v16f16(ptr %a) #0 {
   ret half %res
 }
 
-define float @fmaxv_v2f32(<2 x float> %a) #0 {
+define float @fmaxv_v2f32(<2 x float> %a) {
 ; CHECK-LABEL: fmaxv_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -297,7 +297,7 @@ define float @fmaxv_v2f32(<2 x float> %a) #0 {
   ret float %res
 }
 
-define float @fmaxv_v4f32(<4 x float> %a) #0 {
+define float @fmaxv_v4f32(<4 x float> %a) {
 ; CHECK-LABEL: fmaxv_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -309,7 +309,7 @@ define float @fmaxv_v4f32(<4 x float> %a) #0 {
   ret float %res
 }
 
-define float @fmaxv_v8f32(ptr %a) #0 {
+define float @fmaxv_v8f32(ptr %a) {
 ; CHECK-LABEL: fmaxv_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -323,7 +323,7 @@ define float @fmaxv_v8f32(ptr %a) #0 {
   ret float %res
 }
 
-define double @fmaxv_v1f64(<1 x double> %a) #0 {
+define double @fmaxv_v1f64(<1 x double> %a) {
 ; CHECK-LABEL: fmaxv_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -333,7 +333,7 @@ define double @fmaxv_v1f64(<1 x double> %a) #0 {
   ret double %res
 }
 
-define double @fmaxv_v2f64(<2 x double> %a) #0 {
+define double @fmaxv_v2f64(<2 x double> %a) {
 ; CHECK-LABEL: fmaxv_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -345,7 +345,7 @@ define double @fmaxv_v2f64(<2 x double> %a) #0 {
   ret double %res
 }
 
-define double @fmaxv_v4f64(ptr %a) #0 {
+define double @fmaxv_v4f64(ptr %a) {
 ; CHECK-LABEL: fmaxv_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -363,7 +363,7 @@ define double @fmaxv_v4f64(ptr %a) #0 {
 ; FMINNMV
 ;
 
-define half @fminv_v4f16(<4 x half> %a) #0 {
+define half @fminv_v4f16(<4 x half> %a) {
 ; CHECK-LABEL: fminv_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -375,7 +375,7 @@ define half @fminv_v4f16(<4 x half> %a) #0 {
   ret half %res
 }
 
-define half @fminv_v8f16(<8 x half> %a) #0 {
+define half @fminv_v8f16(<8 x half> %a) {
 ; CHECK-LABEL: fminv_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -387,7 +387,7 @@ define half @fminv_v8f16(<8 x half> %a) #0 {
   ret half %res
 }
 
-define half @fminv_v16f16(ptr %a) #0 {
+define half @fminv_v16f16(ptr %a) {
 ; CHECK-LABEL: fminv_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -401,7 +401,7 @@ define half @fminv_v16f16(ptr %a) #0 {
   ret half %res
 }
 
-define float @fminv_v2f32(<2 x float> %a) #0 {
+define float @fminv_v2f32(<2 x float> %a) {
 ; CHECK-LABEL: fminv_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -413,7 +413,7 @@ define float @fminv_v2f32(<2 x float> %a) #0 {
   ret float %res
 }
 
-define float @fminv_v4f32(<4 x float> %a) #0 {
+define float @fminv_v4f32(<4 x float> %a) {
 ; CHECK-LABEL: fminv_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -425,7 +425,7 @@ define float @fminv_v4f32(<4 x float> %a) #0 {
   ret float %res
 }
 
-define float @fminv_v8f32(ptr %a) #0 {
+define float @fminv_v8f32(ptr %a) {
 ; CHECK-LABEL: fminv_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -439,7 +439,7 @@ define float @fminv_v8f32(ptr %a) #0 {
   ret float %res
 }
 
-define double @fminv_v1f64(<1 x double> %a) #0 {
+define double @fminv_v1f64(<1 x double> %a) {
 ; CHECK-LABEL: fminv_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -449,7 +449,7 @@ define double @fminv_v1f64(<1 x double> %a) #0 {
   ret double %res
 }
 
-define double @fminv_v2f64(<2 x double> %a) #0 {
+define double @fminv_v2f64(<2 x double> %a) {
 ; CHECK-LABEL: fminv_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -461,7 +461,7 @@ define double @fminv_v2f64(<2 x double> %a) #0 {
   ret double %res
 }
 
-define double @fminv_v4f64(ptr %a) #0 {
+define double @fminv_v4f64(ptr %a) {
 ; CHECK-LABEL: fminv_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -479,7 +479,7 @@ define double @fminv_v4f64(ptr %a) #0 {
 ; FMAXV
 ;
 
-define half @fmaximumv_v4f16(<4 x half> %a) #0 {
+define half @fmaximumv_v4f16(<4 x half> %a) {
 ; CHECK-LABEL: fmaximumv_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -491,7 +491,7 @@ define half @fmaximumv_v4f16(<4 x half> %a) #0 {
   ret half %res
 }
 
-define half @fmaximumv_v8f16(<8 x half> %a) #0 {
+define half @fmaximumv_v8f16(<8 x half> %a) {
 ; CHECK-LABEL: fmaximumv_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -503,7 +503,7 @@ define half @fmaximumv_v8f16(<8 x half> %a) #0 {
   ret half %res
 }
 
-define half @fmaximumv_v16f16(ptr %a) #0 {
+define half @fmaximumv_v16f16(ptr %a) {
 ; CHECK-LABEL: fmaximumv_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -517,7 +517,7 @@ define half @fmaximumv_v16f16(ptr %a) #0 {
   ret half %res
 }
 
-define float @fmaximumv_v2f32(<2 x float> %a) #0 {
+define float @fmaximumv_v2f32(<2 x float> %a) {
 ; CHECK-LABEL: fmaximumv_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -529,7 +529,7 @@ define float @fmaximumv_v2f32(<2 x float> %a) #0 {
   ret float %res
 }
 
-define float @fmaximumv_v4f32(<4 x float> %a) #0 {
+define float @fmaximumv_v4f32(<4 x float> %a) {
 ; CHECK-LABEL: fmaximumv_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -541,7 +541,7 @@ define float @fmaximumv_v4f32(<4 x float> %a) #0 {
   ret float %res
 }
 
-define float @fmaximumv_v8f32(ptr %a) #0 {
+define float @fmaximumv_v8f32(ptr %a) {
 ; CHECK-LABEL: fmaximumv_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -555,7 +555,7 @@ define float @fmaximumv_v8f32(ptr %a) #0 {
   ret float %res
 }
 
-define double @fmaximumv_v1f64(<1 x double> %a) #0 {
+define double @fmaximumv_v1f64(<1 x double> %a) {
 ; CHECK-LABEL: fmaximumv_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -565,7 +565,7 @@ define double @fmaximumv_v1f64(<1 x double> %a) #0 {
   ret double %res
 }
 
-define double @fmaximumv_v2f64(<2 x double> %a) #0 {
+define double @fmaximumv_v2f64(<2 x double> %a) {
 ; CHECK-LABEL: fmaximumv_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -577,7 +577,7 @@ define double @fmaximumv_v2f64(<2 x double> %a) #0 {
   ret double %res
 }
 
-define double @fmaximumv_v4f64(ptr %a) #0 {
+define double @fmaximumv_v4f64(ptr %a) {
 ; CHECK-LABEL: fmaximumv_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -595,7 +595,7 @@ define double @fmaximumv_v4f64(ptr %a) #0 {
 ; FMINV
 ;
 
-define half @fminimumv_v4f16(<4 x half> %a) #0 {
+define half @fminimumv_v4f16(<4 x half> %a) {
 ; CHECK-LABEL: fminimumv_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -607,7 +607,7 @@ define half @fminimumv_v4f16(<4 x half> %a) #0 {
   ret half %res
 }
 
-define half @fminimumv_v8f16(<8 x half> %a) #0 {
+define half @fminimumv_v8f16(<8 x half> %a) {
 ; CHECK-LABEL: fminimumv_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -619,7 +619,7 @@ define half @fminimumv_v8f16(<8 x half> %a) #0 {
   ret half %res
 }
 
-define half @fminimumv_v16f16(ptr %a) #0 {
+define half @fminimumv_v16f16(ptr %a) {
 ; CHECK-LABEL: fminimumv_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -633,7 +633,7 @@ define half @fminimumv_v16f16(ptr %a) #0 {
   ret half %res
 }
 
-define float @fminimumv_v2f32(<2 x float> %a) #0 {
+define float @fminimumv_v2f32(<2 x float> %a) {
 ; CHECK-LABEL: fminimumv_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -645,7 +645,7 @@ define float @fminimumv_v2f32(<2 x float> %a) #0 {
   ret float %res
 }
 
-define float @fminimumv_v4f32(<4 x float> %a) #0 {
+define float @fminimumv_v4f32(<4 x float> %a) {
 ; CHECK-LABEL: fminimumv_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -657,7 +657,7 @@ define float @fminimumv_v4f32(<4 x float> %a) #0 {
   ret float %res
 }
 
-define float @fminimumv_v8f32(ptr %a) #0 {
+define float @fminimumv_v8f32(ptr %a) {
 ; CHECK-LABEL: fminimumv_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -671,7 +671,7 @@ define float @fminimumv_v8f32(ptr %a) #0 {
   ret float %res
 }
 
-define double @fminimumv_v1f64(<1 x double> %a) #0 {
+define double @fminimumv_v1f64(<1 x double> %a) {
 ; CHECK-LABEL: fminimumv_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -681,7 +681,7 @@ define double @fminimumv_v1f64(<1 x double> %a) #0 {
   ret double %res
 }
 
-define double @fminimumv_v2f64(<2 x double> %a) #0 {
+define double @fminimumv_v2f64(<2 x double> %a) {
 ; CHECK-LABEL: fminimumv_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -693,7 +693,7 @@ define double @fminimumv_v2f64(<2 x double> %a) #0 {
   ret double %res
 }
 
-define double @fminimumv_v4f64(ptr %a) #0 {
+define double @fminimumv_v4f64(ptr %a) {
 ; CHECK-LABEL: fminimumv_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -707,8 +707,6 @@ define double @fminimumv_v4f64(ptr %a) #0 {
   ret double %res
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
 declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
index 50d518dc96c17..74d20d188a71d 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; CEIL -> FRINTP
 ;
 
-define <2 x half> @frintp_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frintp_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frintp_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -19,7 +19,7 @@ define <2 x half> @frintp_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frintp_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frintp_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frintp_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -31,7 +31,7 @@ define <4 x half> @frintp_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frintp_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frintp_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frintp_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -43,7 +43,7 @@ define <8 x half> @frintp_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frintp_v16f16(ptr %a) #0 {
+define void @frintp_v16f16(ptr %a) {
 ; CHECK-LABEL: frintp_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -58,7 +58,7 @@ define void @frintp_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frintp_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frintp_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frintp_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -70,7 +70,7 @@ define <2 x float> @frintp_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frintp_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frintp_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frintp_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -82,7 +82,7 @@ define <4 x float> @frintp_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frintp_v8f32(ptr %a) #0 {
+define void @frintp_v8f32(ptr %a) {
 ; CHECK-LABEL: frintp_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -97,7 +97,7 @@ define void @frintp_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frintp_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frintp_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frintp_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -107,7 +107,7 @@ define <1 x double> @frintp_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frintp_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frintp_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frintp_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -119,7 +119,7 @@ define <2 x double> @frintp_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frintp_v4f64(ptr %a) #0 {
+define void @frintp_v4f64(ptr %a) {
 ; CHECK-LABEL: frintp_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -138,7 +138,7 @@ define void @frintp_v4f64(ptr %a) #0 {
 ; FLOOR -> FRINTM
 ;
 
-define <2 x half> @frintm_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frintm_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frintm_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -150,7 +150,7 @@ define <2 x half> @frintm_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frintm_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frintm_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frintm_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -162,7 +162,7 @@ define <4 x half> @frintm_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frintm_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frintm_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frintm_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -174,7 +174,7 @@ define <8 x half> @frintm_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frintm_v16f16(ptr %a) #0 {
+define void @frintm_v16f16(ptr %a) {
 ; CHECK-LABEL: frintm_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -189,7 +189,7 @@ define void @frintm_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frintm_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frintm_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frintm_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -201,7 +201,7 @@ define <2 x float> @frintm_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frintm_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frintm_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frintm_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -213,7 +213,7 @@ define <4 x float> @frintm_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frintm_v8f32(ptr %a) #0 {
+define void @frintm_v8f32(ptr %a) {
 ; CHECK-LABEL: frintm_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -228,7 +228,7 @@ define void @frintm_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frintm_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frintm_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frintm_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -238,7 +238,7 @@ define <1 x double> @frintm_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frintm_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frintm_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frintm_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -250,7 +250,7 @@ define <2 x double> @frintm_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frintm_v4f64(ptr %a) #0 {
+define void @frintm_v4f64(ptr %a) {
 ; CHECK-LABEL: frintm_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -269,7 +269,7 @@ define void @frintm_v4f64(ptr %a) #0 {
 ; FNEARBYINT -> FRINTI
 ;
 
-define <2 x half> @frinti_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frinti_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frinti_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -281,7 +281,7 @@ define <2 x half> @frinti_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frinti_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frinti_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frinti_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -293,7 +293,7 @@ define <4 x half> @frinti_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frinti_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frinti_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frinti_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -305,7 +305,7 @@ define <8 x half> @frinti_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frinti_v16f16(ptr %a) #0 {
+define void @frinti_v16f16(ptr %a) {
 ; CHECK-LABEL: frinti_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -320,7 +320,7 @@ define void @frinti_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frinti_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frinti_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frinti_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -332,7 +332,7 @@ define <2 x float> @frinti_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frinti_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frinti_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frinti_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -344,7 +344,7 @@ define <4 x float> @frinti_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frinti_v8f32(ptr %a) #0 {
+define void @frinti_v8f32(ptr %a) {
 ; CHECK-LABEL: frinti_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -359,7 +359,7 @@ define void @frinti_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frinti_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frinti_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frinti_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -369,7 +369,7 @@ define <1 x double> @frinti_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frinti_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frinti_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frinti_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -381,7 +381,7 @@ define <2 x double> @frinti_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frinti_v4f64(ptr %a) #0 {
+define void @frinti_v4f64(ptr %a) {
 ; CHECK-LABEL: frinti_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -400,7 +400,7 @@ define void @frinti_v4f64(ptr %a) #0 {
 ; RINT -> FRINTX
 ;
 
-define <2 x half> @frintx_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frintx_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frintx_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -412,7 +412,7 @@ define <2 x half> @frintx_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frintx_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frintx_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frintx_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -424,7 +424,7 @@ define <4 x half> @frintx_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frintx_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frintx_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frintx_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -436,7 +436,7 @@ define <8 x half> @frintx_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frintx_v16f16(ptr %a) #0 {
+define void @frintx_v16f16(ptr %a) {
 ; CHECK-LABEL: frintx_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -451,7 +451,7 @@ define void @frintx_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frintx_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frintx_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frintx_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -463,7 +463,7 @@ define <2 x float> @frintx_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frintx_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frintx_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frintx_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -475,7 +475,7 @@ define <4 x float> @frintx_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frintx_v8f32(ptr %a) #0 {
+define void @frintx_v8f32(ptr %a) {
 ; CHECK-LABEL: frintx_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -490,7 +490,7 @@ define void @frintx_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frintx_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frintx_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frintx_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -500,7 +500,7 @@ define <1 x double> @frintx_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frintx_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frintx_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frintx_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -512,7 +512,7 @@ define <2 x double> @frintx_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frintx_v4f64(ptr %a) #0 {
+define void @frintx_v4f64(ptr %a) {
 ; CHECK-LABEL: frintx_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -531,7 +531,7 @@ define void @frintx_v4f64(ptr %a) #0 {
 ; ROUND -> FRINTA
 ;
 
-define <2 x half> @frinta_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frinta_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frinta_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -543,7 +543,7 @@ define <2 x half> @frinta_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frinta_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frinta_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frinta_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -555,7 +555,7 @@ define <4 x half> @frinta_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frinta_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frinta_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frinta_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -567,7 +567,7 @@ define <8 x half> @frinta_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frinta_v16f16(ptr %a) #0 {
+define void @frinta_v16f16(ptr %a) {
 ; CHECK-LABEL: frinta_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -582,7 +582,7 @@ define void @frinta_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frinta_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frinta_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frinta_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -594,7 +594,7 @@ define <2 x float> @frinta_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frinta_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frinta_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frinta_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -606,7 +606,7 @@ define <4 x float> @frinta_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frinta_v8f32(ptr %a) #0 {
+define void @frinta_v8f32(ptr %a) {
 ; CHECK-LABEL: frinta_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -621,7 +621,7 @@ define void @frinta_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frinta_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frinta_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frinta_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -631,7 +631,7 @@ define <1 x double> @frinta_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frinta_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frinta_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frinta_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -643,7 +643,7 @@ define <2 x double> @frinta_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frinta_v4f64(ptr %a) #0 {
+define void @frinta_v4f64(ptr %a) {
 ; CHECK-LABEL: frinta_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -662,7 +662,7 @@ define void @frinta_v4f64(ptr %a) #0 {
 ; ROUNDEVEN -> FRINTN
 ;
 
-define <2 x half> @frintn_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frintn_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frintn_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -674,7 +674,7 @@ define <2 x half> @frintn_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frintn_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frintn_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frintn_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -686,7 +686,7 @@ define <4 x half> @frintn_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frintn_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frintn_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frintn_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -698,7 +698,7 @@ define <8 x half> @frintn_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frintn_v16f16(ptr %a) #0 {
+define void @frintn_v16f16(ptr %a) {
 ; CHECK-LABEL: frintn_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -713,7 +713,7 @@ define void @frintn_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frintn_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frintn_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frintn_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -725,7 +725,7 @@ define <2 x float> @frintn_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frintn_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frintn_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frintn_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -737,7 +737,7 @@ define <4 x float> @frintn_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frintn_v8f32(ptr %a) #0 {
+define void @frintn_v8f32(ptr %a) {
 ; CHECK-LABEL: frintn_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -752,7 +752,7 @@ define void @frintn_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frintn_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frintn_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frintn_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -762,7 +762,7 @@ define <1 x double> @frintn_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frintn_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frintn_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frintn_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -774,7 +774,7 @@ define <2 x double> @frintn_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frintn_v4f64(ptr %a) #0 {
+define void @frintn_v4f64(ptr %a) {
 ; CHECK-LABEL: frintn_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -793,7 +793,7 @@ define void @frintn_v4f64(ptr %a) #0 {
 ; TRUNC -> FRINTZ
 ;
 
-define <2 x half> @frintz_v2f16(<2 x half> %op) #0 {
+define <2 x half> @frintz_v2f16(<2 x half> %op) {
 ; CHECK-LABEL: frintz_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -805,7 +805,7 @@ define <2 x half> @frintz_v2f16(<2 x half> %op) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @frintz_v4f16(<4 x half> %op) #0 {
+define <4 x half> @frintz_v4f16(<4 x half> %op) {
 ; CHECK-LABEL: frintz_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -817,7 +817,7 @@ define <4 x half> @frintz_v4f16(<4 x half> %op) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @frintz_v8f16(<8 x half> %op) #0 {
+define <8 x half> @frintz_v8f16(<8 x half> %op) {
 ; CHECK-LABEL: frintz_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -829,7 +829,7 @@ define <8 x half> @frintz_v8f16(<8 x half> %op) #0 {
   ret <8 x half> %res
 }
 
-define void @frintz_v16f16(ptr %a) #0 {
+define void @frintz_v16f16(ptr %a) {
 ; CHECK-LABEL: frintz_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -844,7 +844,7 @@ define void @frintz_v16f16(ptr %a) #0 {
   ret void
 }
 
-define <2 x float> @frintz_v2f32(<2 x float> %op) #0 {
+define <2 x float> @frintz_v2f32(<2 x float> %op) {
 ; CHECK-LABEL: frintz_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -856,7 +856,7 @@ define <2 x float> @frintz_v2f32(<2 x float> %op) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @frintz_v4f32(<4 x float> %op) #0 {
+define <4 x float> @frintz_v4f32(<4 x float> %op) {
 ; CHECK-LABEL: frintz_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -868,7 +868,7 @@ define <4 x float> @frintz_v4f32(<4 x float> %op) #0 {
   ret <4 x float> %res
 }
 
-define void @frintz_v8f32(ptr %a) #0 {
+define void @frintz_v8f32(ptr %a) {
 ; CHECK-LABEL: frintz_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -883,7 +883,7 @@ define void @frintz_v8f32(ptr %a) #0 {
   ret void
 }
 
-define <1 x double> @frintz_v1f64(<1 x double> %op) #0 {
+define <1 x double> @frintz_v1f64(<1 x double> %op) {
 ; CHECK-LABEL: frintz_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -893,7 +893,7 @@ define <1 x double> @frintz_v1f64(<1 x double> %op) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @frintz_v2f64(<2 x double> %op) #0 {
+define <2 x double> @frintz_v2f64(<2 x double> %op) {
 ; CHECK-LABEL: frintz_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -905,7 +905,7 @@ define <2 x double> @frintz_v2f64(<2 x double> %op) #0 {
   ret <2 x double> %res
 }
 
-define void @frintz_v4f64(ptr %a) #0 {
+define void @frintz_v4f64(ptr %a) {
 ; CHECK-LABEL: frintz_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -920,8 +920,6 @@ define void @frintz_v4f64(ptr %a) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare <2 x half> @llvm.ceil.v2f16(<2 x half>)
 declare <4 x half> @llvm.ceil.v4f16(<4 x half>)
 declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
index 8b7112913d0dc..2344b4741088d 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) #0 {
+define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -19,7 +19,7 @@ define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) #0 {
   ret <2 x half> %sel
 }
 
-define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) #0 {
+define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -35,7 +35,7 @@ define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) #0 {
   ret <4 x half> %sel
 }
 
-define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) #0 {
+define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -51,7 +51,7 @@ define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) #0 {
   ret <8 x half> %sel
 }
 
-define void @select_v16f16(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v16f16(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w2, #0x1
@@ -73,7 +73,7 @@ define void @select_v16f16(ptr %a, ptr %b, i1 %mask) #0 {
   ret void
 }
 
-define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) #0 {
+define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -89,7 +89,7 @@ define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) #
   ret <2 x float> %sel
 }
 
-define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) #0 {
+define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -105,7 +105,7 @@ define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) #
   ret <4 x float> %sel
 }
 
-define void @select_v8f32(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v8f32(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w2, #0x1
@@ -127,7 +127,7 @@ define void @select_v8f32(ptr %a, ptr %b, i1 %mask) #0 {
   ret void
 }
 
-define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) #0 {
+define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
@@ -146,7 +146,7 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask
   ret <1 x double> %sel
 }
 
-define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) #0 {
+define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
@@ -163,7 +163,7 @@ define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask
   ret <2 x double> %sel
 }
 
-define void @select_v4f64(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v4f64(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
@@ -185,5 +185,3 @@ define void @select_v4f64(ptr %a, ptr %b, i1 %mask) #0 {
   store <4 x double> %sel, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
index 10f8c1b655ce5..f2691e0635ac3 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; FCVTZU H -> H
 ;
 
-define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) #0 {
+define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) {
 ; CHECK-LABEL: fcvtzu_v4f16_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -19,7 +19,7 @@ define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) #0 {
   ret <4 x i16> %res
 }
 
-define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v8f16_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -33,7 +33,7 @@ define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v16f16_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -52,7 +52,7 @@ define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) #0 {
 ; FCVTZU H -> S
 ;
 
-define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) #0 {
+define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f16_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -65,7 +65,7 @@ define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) #0 {
+define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) {
 ; CHECK-LABEL: fcvtzu_v4f16_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -78,7 +78,7 @@ define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) #0 {
   ret <4 x i32> %res
 }
 
-define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v8f16_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -96,7 +96,7 @@ define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v16f16_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -125,7 +125,7 @@ define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) #0 {
 ; FCVTZU H -> D
 ;
 
-define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) #0 {
+define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) {
 ; CHECK-LABEL: fcvtzu_v1f16_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x8, h0
@@ -135,7 +135,7 @@ define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) #0 {
+define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f16_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -150,7 +150,7 @@ define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v4f16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -174,7 +174,7 @@ define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v8f16_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #64
@@ -211,7 +211,7 @@ define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v16f16_v16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #128
@@ -275,7 +275,7 @@ define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) #0 {
 ; FCVTZU S -> H
 ;
 
-define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) #0 {
+define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f32_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -287,7 +287,7 @@ define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) #0 {
+define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) {
 ; CHECK-LABEL: fcvtzu_v4f32_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -300,7 +300,7 @@ define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) #0 {
+define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) {
 ; CHECK-LABEL: fcvtzu_v8f32_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -318,7 +318,7 @@ define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) #0 {
   ret <8 x i16> %res
 }
 
-define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v16f32_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -347,7 +347,7 @@ define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) #0 {
 ; FCVTZU S -> S
 ;
 
-define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) #0 {
+define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f32_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -359,7 +359,7 @@ define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) #0 {
+define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) {
 ; CHECK-LABEL: fcvtzu_v4f32_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -371,7 +371,7 @@ define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) #0 {
   ret <4 x i32> %res
 }
 
-define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v8f32_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -390,7 +390,7 @@ define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) #0 {
 ; FCVTZU S -> D
 ;
 
-define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) #0 {
+define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) {
 ; CHECK-LABEL: fcvtzu_v1f32_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -403,7 +403,7 @@ define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) #0 {
+define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f32_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -416,7 +416,7 @@ define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v4f32_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -434,7 +434,7 @@ define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v8f32_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -463,7 +463,7 @@ define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) #0 {
 ; FCVTZU D -> H
 ;
 
-define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) #0 {
+define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) {
 ; CHECK-LABEL: fcvtzu_v1f64_v1i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -475,7 +475,7 @@ define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) #0 {
   ret <1 x i16> %res
 }
 
-define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) #0 {
+define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f64_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -488,7 +488,7 @@ define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) #0 {
+define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) {
 ; CHECK-LABEL: fcvtzu_v4f64_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -517,7 +517,7 @@ define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) #0 {
+define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) {
 ; CHECK-LABEL: fcvtzu_v8f64_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -560,7 +560,7 @@ define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) #0 {
   ret <8 x i16> %res
 }
 
-define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v16f64_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #32
@@ -641,7 +641,7 @@ define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) #0 {
 ; FCVTZU D -> S
 ;
 
-define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) #0 {
+define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) {
 ; CHECK-LABEL: fcvtzu_v1f64_v1i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -654,7 +654,7 @@ define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) #0 {
   ret <1 x i32> %res
 }
 
-define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) #0 {
+define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f64_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -667,7 +667,7 @@ define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) #0 {
+define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) {
 ; CHECK-LABEL: fcvtzu_v4f64_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -685,7 +685,7 @@ define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) #0 {
   ret <4 x i32> %res
 }
 
-define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v8f64_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -714,7 +714,7 @@ define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) #0 {
 ; FCVTZU D -> D
 ;
 
-define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) #0 {
+define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) {
 ; CHECK-LABEL: fcvtzu_v1f64_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -726,7 +726,7 @@ define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) #0 {
+define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) {
 ; CHECK-LABEL: fcvtzu_v2f64_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -738,7 +738,7 @@ define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) #0 {
+define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzu_v4f64_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -757,7 +757,7 @@ define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) #0 {
 ; FCVTZS H -> H
 ;
 
-define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) #0 {
+define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) {
 ; CHECK-LABEL: fcvtzs_v4f16_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -769,7 +769,7 @@ define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) #0 {
   ret <4 x i16> %res
 }
 
-define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v8f16_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -783,7 +783,7 @@ define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v16f16_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -802,7 +802,7 @@ define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) #0 {
 ; FCVTZS H -> S
 ;
 
-define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) #0 {
+define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f16_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -815,7 +815,7 @@ define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) #0 {
+define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) {
 ; CHECK-LABEL: fcvtzs_v4f16_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -828,7 +828,7 @@ define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) #0 {
   ret <4 x i32> %res
 }
 
-define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v8f16_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -846,7 +846,7 @@ define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v16f16_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -875,7 +875,7 @@ define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) #0 {
 ; FCVTZS H -> D
 ;
 
-define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) #0 {
+define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) {
 ; CHECK-LABEL: fcvtzs_v1f16_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x8, h0
@@ -886,7 +886,7 @@ define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) #0 {
 }
 
 ; v2f16 is not legal for NEON, so use SVE
-define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) #0 {
+define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f16_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -901,7 +901,7 @@ define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v4f16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -925,7 +925,7 @@ define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v8f16_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #64
@@ -962,7 +962,7 @@ define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v16f16_v16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #128
@@ -1026,7 +1026,7 @@ define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) #0 {
 ; FCVTZS S -> H
 ;
 
-define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) #0 {
+define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f32_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1038,7 +1038,7 @@ define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) #0 {
+define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) {
 ; CHECK-LABEL: fcvtzs_v4f32_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1051,7 +1051,7 @@ define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) #0 {
+define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) {
 ; CHECK-LABEL: fcvtzs_v8f32_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -1069,7 +1069,7 @@ define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) #0 {
   ret <8 x i16> %res
 }
 
-define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v16f32_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1098,7 +1098,7 @@ define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) #0 {
 ; FCVTZS S -> S
 ;
 
-define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) #0 {
+define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f32_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1110,7 +1110,7 @@ define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) #0 {
+define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) {
 ; CHECK-LABEL: fcvtzs_v4f32_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1122,7 +1122,7 @@ define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) #0 {
   ret <4 x i32> %res
 }
 
-define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v8f32_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1141,7 +1141,7 @@ define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) #0 {
 ; FCVTZS S -> D
 ;
 
-define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) #0 {
+define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) {
 ; CHECK-LABEL: fcvtzs_v1f32_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1154,7 +1154,7 @@ define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) #0 {
+define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f32_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1167,7 +1167,7 @@ define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v4f32_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -1185,7 +1185,7 @@ define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v8f32_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1216,7 +1216,7 @@ define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) #0 {
 ;
 
 ; v1f64 is perfered to be widened to v4f64, so use SVE
-define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) #0 {
+define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) {
 ; CHECK-LABEL: fcvtzs_v1f64_v1i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1228,7 +1228,7 @@ define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) #0 {
   ret <1 x i16> %res
 }
 
-define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) #0 {
+define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f64_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1241,7 +1241,7 @@ define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) #0 {
+define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) {
 ; CHECK-LABEL: fcvtzs_v4f64_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -1270,7 +1270,7 @@ define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) #0 {
+define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) {
 ; CHECK-LABEL: fcvtzs_v8f64_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -1313,7 +1313,7 @@ define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) #0 {
   ret <8 x i16> %res
 }
 
-define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v16f64_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #32
@@ -1394,7 +1394,7 @@ define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) #0 {
 ; FCVTZS D -> S
 ;
 
-define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) #0 {
+define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) {
 ; CHECK-LABEL: fcvtzs_v1f64_v1i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1407,7 +1407,7 @@ define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) #0 {
   ret <1 x i32> %res
 }
 
-define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) #0 {
+define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f64_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1420,7 +1420,7 @@ define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) #0 {
+define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) {
 ; CHECK-LABEL: fcvtzs_v4f64_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -1438,7 +1438,7 @@ define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) #0 {
   ret <4 x i32> %res
 }
 
-define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v8f64_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1467,7 +1467,7 @@ define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) #0 {
 ; FCVTZS D -> D
 ;
 
-define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) #0 {
+define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) {
 ; CHECK-LABEL: fcvtzs_v1f64_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -1479,7 +1479,7 @@ define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) #0 {
+define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) {
 ; CHECK-LABEL: fcvtzs_v2f64_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1491,7 +1491,7 @@ define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) #0 {
+define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fcvtzs_v4f64_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1505,5 +1505,3 @@ define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) #0 {
   store <4 x i64> %res, ptr %b
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
index 008ff7d90b5eb..685efd0574347 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask) #0 {
+define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask) {
 ; CHECK-LABEL: select_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -30,7 +30,7 @@ define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask
   ret <2 x half> %sel
 }
 
-define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask) #0 {
+define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask) {
 ; CHECK-LABEL: select_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -48,7 +48,7 @@ define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask
   ret <4 x half> %sel
 }
 
-define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask) #0 {
+define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask) {
 ; CHECK-LABEL: select_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -67,7 +67,7 @@ define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask
   ret <8 x half> %sel
 }
 
-define void @select_v16f16(ptr %a, ptr %b) #0 {
+define void @select_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -87,7 +87,7 @@ define void @select_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) #0 {
+define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) {
 ; CHECK-LABEL: select_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -105,7 +105,7 @@ define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %m
   ret <2 x float> %sel
 }
 
-define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %mask) #0 {
+define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %mask) {
 ; CHECK-LABEL: select_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -124,7 +124,7 @@ define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %m
   ret <4 x float> %sel
 }
 
-define void @select_v8f32(ptr %a, ptr %b) #0 {
+define void @select_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -144,7 +144,7 @@ define void @select_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) #0 {
+define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) {
 ; CHECK-LABEL: select_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
@@ -163,7 +163,7 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1>
   ret <1 x double> %sel
 }
 
-define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) #0 {
+define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) {
 ; CHECK-LABEL: select_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -182,7 +182,7 @@ define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1>
   ret <2 x double> %sel
 }
 
-define void @select_v4f64(ptr %a, ptr %b) #0 {
+define void @select_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -201,5 +201,3 @@ define void @select_v4f64(ptr %a, ptr %b) #0 {
   store <4 x double> %sel, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
index e10a01c2e3973..8252ca84aa048 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -8,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ;
 
 ; i8
-define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) #0 {
+define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) {
 ; CHECK-LABEL: insertelement_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #3 // =0x3
@@ -25,7 +25,7 @@ define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) #0 {
     ret <4 x i8> %r
 }
 
-define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) #0 {
+define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) {
 ; CHECK-LABEL: insertelement_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #7 // =0x7
@@ -42,7 +42,7 @@ define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) #0 {
     ret <8 x i8> %r
 }
 
-define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) #0 {
+define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) {
 ; CHECK-LABEL: insertelement_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #15 // =0xf
@@ -59,7 +59,7 @@ define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) #0 {
     ret <16 x i8> %r
 }
 
-define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) #0 {
+define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) {
 ; CHECK-LABEL: insertelement_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #15 // =0xf
@@ -77,7 +77,7 @@ define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) #0 {
 }
 
 ; i16
-define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) #0 {
+define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) {
 ; CHECK-LABEL: insertelement_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1 // =0x1
@@ -94,7 +94,7 @@ define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) #0 {
     ret <2 x i16> %r
 }
 
-define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) #0 {
+define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) {
 ; CHECK-LABEL: insertelement_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #3 // =0x3
@@ -111,7 +111,7 @@ define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) #0 {
     ret <4 x i16> %r
 }
 
-define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) #0 {
+define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) {
 ; CHECK-LABEL: insertelement_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #7 // =0x7
@@ -128,7 +128,7 @@ define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) #0 {
     ret <8 x i16> %r
 }
 
-define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) #0 {
+define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) {
 ; CHECK-LABEL: insertelement_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #7 // =0x7
@@ -146,7 +146,7 @@ define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) #0 {
 }
 
 ;i32
-define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) #0 {
+define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) {
 ; CHECK-LABEL: insertelement_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1 // =0x1
@@ -163,7 +163,7 @@ define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) #0 {
     ret <2 x i32> %r
 }
 
-define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) #0 {
+define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) {
 ; CHECK-LABEL: insertelement_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #3 // =0x3
@@ -180,7 +180,7 @@ define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) #0 {
     ret <4 x i32> %r
 }
 
-define <8 x i32> @insertelement_v8i32(ptr %a) #0 {
+define <8 x i32> @insertelement_v8i32(ptr %a) {
 ; CHECK-LABEL: insertelement_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #3 // =0x3
@@ -199,7 +199,7 @@ define <8 x i32> @insertelement_v8i32(ptr %a) #0 {
 }
 
 ;i64
-define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) #0 {
+define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) {
 ; CHECK-LABEL: insertelement_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #5 // =0x5
@@ -209,7 +209,7 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) #0 {
     ret <1 x i64> %r
 }
 
-define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) #0 {
+define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) {
 ; CHECK-LABEL: insertelement_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1 // =0x1
@@ -226,7 +226,7 @@ define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) #0 {
     ret <2 x i64> %r
 }
 
-define <4 x i64> @insertelement_v4i64(ptr %a) #0 {
+define <4 x i64> @insertelement_v4i64(ptr %a) {
 ; CHECK-LABEL: insertelement_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1 // =0x1
@@ -245,7 +245,7 @@ define <4 x i64> @insertelement_v4i64(ptr %a) #0 {
 }
 
 ;f16
-define <2 x half> @insertelement_v2f16(<2 x half> %op1) #0 {
+define <2 x half> @insertelement_v2f16(<2 x half> %op1) {
 ; CHECK-LABEL: insertelement_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -261,7 +261,7 @@ define <2 x half> @insertelement_v2f16(<2 x half> %op1) #0 {
     ret <2 x half> %r
 }
 
-define <4 x half> @insertelement_v4f16(<4 x half> %op1) #0 {
+define <4 x half> @insertelement_v4f16(<4 x half> %op1) {
 ; CHECK-LABEL: insertelement_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #3 // =0x3
@@ -278,7 +278,7 @@ define <4 x half> @insertelement_v4f16(<4 x half> %op1) #0 {
     ret <4 x half> %r
 }
 
-define <8 x half> @insertelement_v8f16(<8 x half> %op1) #0 {
+define <8 x half> @insertelement_v8f16(<8 x half> %op1) {
 ; CHECK-LABEL: insertelement_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #7 // =0x7
@@ -295,7 +295,7 @@ define <8 x half> @insertelement_v8f16(<8 x half> %op1) #0 {
     ret <8 x half> %r
 }
 
-define <16 x half> @insertelement_v16f16(ptr %a) #0 {
+define <16 x half> @insertelement_v16f16(ptr %a) {
 ; CHECK-LABEL: insertelement_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -314,7 +314,7 @@ define <16 x half> @insertelement_v16f16(ptr %a) #0 {
 }
 
 ;f32
-define <2 x float> @insertelement_v2f32(<2 x float> %op1) #0 {
+define <2 x float> @insertelement_v2f32(<2 x float> %op1) {
 ; CHECK-LABEL: insertelement_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1 // =0x1
@@ -331,7 +331,7 @@ define <2 x float> @insertelement_v2f32(<2 x float> %op1) #0 {
     ret <2 x float> %r
 }
 
-define <4 x float> @insertelement_v4f32(<4 x float> %op1) #0 {
+define <4 x float> @insertelement_v4f32(<4 x float> %op1) {
 ; CHECK-LABEL: insertelement_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #3 // =0x3
@@ -348,7 +348,7 @@ define <4 x float> @insertelement_v4f32(<4 x float> %op1) #0 {
     ret <4 x float> %r
 }
 
-define <8 x float> @insertelement_v8f32(ptr %a) #0 {
+define <8 x float> @insertelement_v8f32(ptr %a) {
 ; CHECK-LABEL: insertelement_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -367,7 +367,7 @@ define <8 x float> @insertelement_v8f32(ptr %a) #0 {
 }
 
 ;f64
-define <1 x double> @insertelement_v1f64(<1 x double> %op1) #0 {
+define <1 x double> @insertelement_v1f64(<1 x double> %op1) {
 ; CHECK-LABEL: insertelement_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov d0, #5.00000000
@@ -376,7 +376,7 @@ define <1 x double> @insertelement_v1f64(<1 x double> %op1) #0 {
     ret <1 x double> %r
 }
 
-define <2 x double> @insertelement_v2f64(<2 x double> %op1) #0 {
+define <2 x double> @insertelement_v2f64(<2 x double> %op1) {
 ; CHECK-LABEL: insertelement_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #1 // =0x1
@@ -393,7 +393,7 @@ define <2 x double> @insertelement_v2f64(<2 x double> %op1) #0 {
     ret <2 x double> %r
 }
 
-define <4 x double> @insertelement_v4f64(ptr %a) #0 {
+define <4 x double> @insertelement_v4f64(ptr %a) {
 ; CHECK-LABEL: insertelement_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -410,5 +410,3 @@ define <4 x double> @insertelement_v4f64(ptr %a) #0 {
     %r = insertelement <4 x double> %op1, double 5.0, i64 3
     ret <4 x double> %r
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
index 48c67399963dc..e93c3b4cf685f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
@@ -1,12 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE2
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; ADD
 ;
-define <4 x i8> @add_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @add_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: add_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -18,7 +19,7 @@ define <4 x i8> @add_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: add_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -30,7 +31,7 @@ define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: add_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -42,7 +43,7 @@ define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @add_v32i8(ptr %a, ptr %b) #0 {
+define void @add_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -58,7 +59,7 @@ define void @add_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @add_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @add_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: add_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -70,7 +71,7 @@ define <2 x i16> @add_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: add_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -82,7 +83,7 @@ define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: add_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -94,7 +95,7 @@ define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @add_v16i16(ptr %a, ptr %b) #0 {
+define void @add_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -110,7 +111,7 @@ define void @add_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: add_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -122,7 +123,7 @@ define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: add_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -134,7 +135,7 @@ define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @add_v8i32(ptr %a, ptr %b) #0 {
+define void @add_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -150,7 +151,7 @@ define void @add_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: add_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -162,7 +163,7 @@ define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: add_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -174,7 +175,7 @@ define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @add_v4i64(ptr %a, ptr %b) #0 {
+define void @add_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -194,55 +195,88 @@ define void @add_v4i64(ptr %a, ptr %b) #0 {
 ; MUL
 ;
 
-define <4 x i8> @mul_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
-; CHECK-LABEL: mul_v4i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i8> @mul_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
+; SVE-LABEL: mul_v4i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    mul z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v4i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    mul z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <4 x i8> %op1, %op2
   ret <4 x i8> %res
 }
 
-define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: mul_v8i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.b, vl8
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    mul z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
+; SVE-LABEL: mul_v8i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.b, vl8
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    mul z0.b, p0/m, z0.b, z1.b
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v8i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    mul z0.b, z0.b, z1.b
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <8 x i8> %op1, %op2
   ret <8 x i8> %res
 }
 
-define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: mul_v16i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    mul z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
+; SVE-LABEL: mul_v16i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.b, vl16
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    mul z0.b, p0/m, z0.b, z1.b
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v16i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    mul z0.b, z0.b, z1.b
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <16 x i8> %op1, %op2
   ret <16 x i8> %res
 }
 
-define void @mul_v32i8(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: mul_v32i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    mul z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    mul z1.b, p0/m, z1.b, z3.b
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @mul_v32i8(ptr %a, ptr %b) {
+; SVE-LABEL: mul_v32i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.b, vl16
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    mul z0.b, p0/m, z0.b, z2.b
+; SVE-NEXT:    mul z1.b, p0/m, z1.b, z3.b
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v32i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    mul z0.b, z0.b, z2.b
+; SVE2-NEXT:    mul z1.b, z1.b, z3.b
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %op2 = load <32 x i8>, ptr %b
   %res = mul <32 x i8> %op1, %op2
@@ -250,55 +284,88 @@ define void @mul_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @mul_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
-; CHECK-LABEL: mul_v2i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i16> @mul_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
+; SVE-LABEL: mul_v2i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    mul z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v2i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    mul z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <2 x i16> %op1, %op2
   ret <2 x i16> %res
 }
 
-define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: mul_v4i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
+; SVE-LABEL: mul_v4i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    mul z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v4i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    mul z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <4 x i16> %op1, %op2
   ret <4 x i16> %res
 }
 
-define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: mul_v8i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
+; SVE-LABEL: mul_v8i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl8
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    mul z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v8i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    mul z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <8 x i16> %op1, %op2
   ret <8 x i16> %res
 }
 
-define void @mul_v16i16(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: mul_v16i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z3.h
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @mul_v16i16(ptr %a, ptr %b) {
+; SVE-LABEL: mul_v16i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.h, vl8
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    mul z0.h, p0/m, z0.h, z2.h
+; SVE-NEXT:    mul z1.h, p0/m, z1.h, z3.h
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v16i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    mul z0.h, z0.h, z2.h
+; SVE2-NEXT:    mul z1.h, z1.h, z3.h
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %op2 = load <16 x i16>, ptr %b
   %res = mul <16 x i16> %op1, %op2
@@ -306,42 +373,67 @@ define void @mul_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: mul_v2i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
+; SVE-LABEL: mul_v2i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    mul z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v2i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    mul z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <2 x i32> %op1, %op2
   ret <2 x i32> %res
 }
 
-define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: mul_v4i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
+; SVE-LABEL: mul_v4i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    mul z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v4i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    mul z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <4 x i32> %op1, %op2
   ret <4 x i32> %res
 }
 
-define void @mul_v8i32(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: mul_v8i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    mul z1.s, p0/m, z1.s, z3.s
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @mul_v8i32(ptr %a, ptr %b) {
+; SVE-LABEL: mul_v8i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    mul z0.s, p0/m, z0.s, z2.s
+; SVE-NEXT:    mul z1.s, p0/m, z1.s, z3.s
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v8i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    mul z0.s, z0.s, z2.s
+; SVE2-NEXT:    mul z1.s, z1.s, z3.s
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %op2 = load <8 x i32>, ptr %b
   %res = mul <8 x i32> %op1, %op2
@@ -349,42 +441,67 @@ define void @mul_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: mul_v1i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl1
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
+; SVE-LABEL: mul_v1i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl1
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    mul z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v1i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    mul z0.d, z0.d, z1.d
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <1 x i64> %op1, %op2
   ret <1 x i64> %res
 }
 
-define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: mul_v2i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
+; SVE-LABEL: mul_v2i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    mul z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v2i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    mul z0.d, z0.d, z1.d
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %res = mul <2 x i64> %op1, %op2
   ret <2 x i64> %res
 }
 
-define void @mul_v4i64(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: mul_v4i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    mul z1.d, p0/m, z1.d, z3.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @mul_v4i64(ptr %a, ptr %b) {
+; SVE-LABEL: mul_v4i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    mul z0.d, p0/m, z0.d, z2.d
+; SVE-NEXT:    mul z1.d, p0/m, z1.d, z3.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: mul_v4i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    mul z0.d, z0.d, z2.d
+; SVE2-NEXT:    mul z1.d, z1.d, z3.d
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %op2 = load <4 x i64>, ptr %b
   %res = mul <4 x i64> %op1, %op2
@@ -396,7 +513,7 @@ define void @mul_v4i64(ptr %a, ptr %b) #0 {
 ; SUB
 ;
 
-define <4 x i8> @sub_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @sub_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: sub_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -408,7 +525,7 @@ define <4 x i8> @sub_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @sub_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @sub_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: sub_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -420,7 +537,7 @@ define <8 x i8> @sub_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: sub_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -432,7 +549,7 @@ define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @sub_v32i8(ptr %a, ptr %b) #0 {
+define void @sub_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: sub_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -448,7 +565,7 @@ define void @sub_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @sub_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @sub_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: sub_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -460,7 +577,7 @@ define <2 x i16> @sub_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @sub_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @sub_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: sub_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -472,7 +589,7 @@ define <4 x i16> @sub_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: sub_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -484,7 +601,7 @@ define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @sub_v16i16(ptr %a, ptr %b) #0 {
+define void @sub_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: sub_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -500,7 +617,7 @@ define void @sub_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @sub_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @sub_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: sub_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -512,7 +629,7 @@ define <2 x i32> @sub_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: sub_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -524,7 +641,7 @@ define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @sub_v8i32(ptr %a, ptr %b) #0 {
+define void @sub_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: sub_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -540,7 +657,7 @@ define void @sub_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: sub_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -552,7 +669,7 @@ define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: sub_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -564,7 +681,7 @@ define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @sub_v4i64(ptr %a, ptr %b) #0 {
+define void @sub_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: sub_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -584,7 +701,7 @@ define void @sub_v4i64(ptr %a, ptr %b) #0 {
 ; ABS
 ;
 
-define <4 x i8> @abs_v4i8(<4 x i8> %op1) #0 {
+define <4 x i8> @abs_v4i8(<4 x i8> %op1) {
 ; CHECK-LABEL: abs_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -597,7 +714,7 @@ define <4 x i8> @abs_v4i8(<4 x i8> %op1) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @abs_v8i8(<8 x i8> %op1) #0 {
+define <8 x i8> @abs_v8i8(<8 x i8> %op1) {
 ; CHECK-LABEL: abs_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -609,7 +726,7 @@ define <8 x i8> @abs_v8i8(<8 x i8> %op1) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @abs_v16i8(<16 x i8> %op1) #0 {
+define <16 x i8> @abs_v16i8(<16 x i8> %op1) {
 ; CHECK-LABEL: abs_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -621,7 +738,7 @@ define <16 x i8> @abs_v16i8(<16 x i8> %op1) #0 {
   ret <16 x i8> %res
 }
 
-define void @abs_v32i8(ptr %a) #0 {
+define void @abs_v32i8(ptr %a) {
 ; CHECK-LABEL: abs_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -636,7 +753,7 @@ define void @abs_v32i8(ptr %a) #0 {
   ret void
 }
 
-define <2 x i16> @abs_v2i16(<2 x i16> %op1) #0 {
+define <2 x i16> @abs_v2i16(<2 x i16> %op1) {
 ; CHECK-LABEL: abs_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -649,7 +766,7 @@ define <2 x i16> @abs_v2i16(<2 x i16> %op1) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @abs_v4i16(<4 x i16> %op1) #0 {
+define <4 x i16> @abs_v4i16(<4 x i16> %op1) {
 ; CHECK-LABEL: abs_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -661,7 +778,7 @@ define <4 x i16> @abs_v4i16(<4 x i16> %op1) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @abs_v8i16(<8 x i16> %op1) #0 {
+define <8 x i16> @abs_v8i16(<8 x i16> %op1) {
 ; CHECK-LABEL: abs_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -673,7 +790,7 @@ define <8 x i16> @abs_v8i16(<8 x i16> %op1) #0 {
   ret <8 x i16> %res
 }
 
-define void @abs_v16i16(ptr %a) #0 {
+define void @abs_v16i16(ptr %a) {
 ; CHECK-LABEL: abs_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -688,7 +805,7 @@ define void @abs_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @abs_v2i32(<2 x i32> %op1) #0 {
+define <2 x i32> @abs_v2i32(<2 x i32> %op1) {
 ; CHECK-LABEL: abs_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -700,7 +817,7 @@ define <2 x i32> @abs_v2i32(<2 x i32> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @abs_v4i32(<4 x i32> %op1) #0 {
+define <4 x i32> @abs_v4i32(<4 x i32> %op1) {
 ; CHECK-LABEL: abs_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -712,7 +829,7 @@ define <4 x i32> @abs_v4i32(<4 x i32> %op1) #0 {
   ret <4 x i32> %res
 }
 
-define void @abs_v8i32(ptr %a) #0 {
+define void @abs_v8i32(ptr %a) {
 ; CHECK-LABEL: abs_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -727,7 +844,7 @@ define void @abs_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @abs_v1i64(<1 x i64> %op1) #0 {
+define <1 x i64> @abs_v1i64(<1 x i64> %op1) {
 ; CHECK-LABEL: abs_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -739,7 +856,7 @@ define <1 x i64> @abs_v1i64(<1 x i64> %op1) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @abs_v2i64(<2 x i64> %op1) #0 {
+define <2 x i64> @abs_v2i64(<2 x i64> %op1) {
 ; CHECK-LABEL: abs_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -751,7 +868,7 @@ define <2 x i64> @abs_v2i64(<2 x i64> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @abs_v4i64(ptr %a) #0 {
+define void @abs_v4i64(ptr %a) {
 ; CHECK-LABEL: abs_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -781,5 +898,3 @@ declare <1 x i64> @llvm.abs.v1i64(<1 x i64>, i1)
 declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
 declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
 
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
index 8d2c791660ccc..6d37b119782ba 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; ICMP EQ
 ;
 
-define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: icmp_eq_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.b, vl8
@@ -22,7 +22,7 @@ define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %sext
 }
 
-define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: icmp_eq_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.b, vl16
@@ -37,7 +37,7 @@ define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %sext
 }
 
-define void @icmp_eq_v32i8(ptr %a, ptr %b) #0 {
+define void @icmp_eq_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_eq_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -57,7 +57,7 @@ define void @icmp_eq_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: icmp_eq_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -72,7 +72,7 @@ define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %sext
 }
 
-define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: icmp_eq_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl8
@@ -87,7 +87,7 @@ define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %sext
 }
 
-define void @icmp_eq_v16i16(ptr %a, ptr %b) #0 {
+define void @icmp_eq_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_eq_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -107,7 +107,7 @@ define void @icmp_eq_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: icmp_eq_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl2
@@ -122,7 +122,7 @@ define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %sext
 }
 
-define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: icmp_eq_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl4
@@ -137,7 +137,7 @@ define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %sext
 }
 
-define void @icmp_eq_v8i32(ptr %a, ptr %b) #0 {
+define void @icmp_eq_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_eq_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -157,7 +157,7 @@ define void @icmp_eq_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: icmp_eq_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl1
@@ -172,7 +172,7 @@ define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %sext
 }
 
-define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: icmp_eq_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d, vl2
@@ -187,7 +187,7 @@ define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %sext
 }
 
-define void @icmp_eq_v4i64(ptr %a, ptr %b) #0 {
+define void @icmp_eq_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_eq_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -211,7 +211,7 @@ define void @icmp_eq_v4i64(ptr %a, ptr %b) #0 {
 ; ICMP NE
 ;
 
-define void @icmp_ne_v32i8(ptr %a, ptr %b) #0 {
+define void @icmp_ne_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_ne_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -235,7 +235,7 @@ define void @icmp_ne_v32i8(ptr %a, ptr %b) #0 {
 ; ICMP SGE
 ;
 
-define void @icmp_sge_v8i16(ptr %a, ptr %b) #0 {
+define void @icmp_sge_v8i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_sge_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -257,7 +257,7 @@ define void @icmp_sge_v8i16(ptr %a, ptr %b) #0 {
 ; ICMP SGT
 ;
 
-define void @icmp_sgt_v16i16(ptr %a, ptr %b) #0 {
+define void @icmp_sgt_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_sgt_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -281,7 +281,7 @@ define void @icmp_sgt_v16i16(ptr %a, ptr %b) #0 {
 ; ICMP SLE
 ;
 
-define void @icmp_sle_v4i32(ptr %a, ptr %b) #0 {
+define void @icmp_sle_v4i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_sle_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -303,7 +303,7 @@ define void @icmp_sle_v4i32(ptr %a, ptr %b) #0 {
 ; ICMP SLT
 ;
 
-define void @icmp_slt_v8i32(ptr %a, ptr %b) #0 {
+define void @icmp_slt_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_slt_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -327,7 +327,7 @@ define void @icmp_slt_v8i32(ptr %a, ptr %b) #0 {
 ; ICMP UGE
 ;
 
-define void @icmp_uge_v2i64(ptr %a, ptr %b) #0 {
+define void @icmp_uge_v2i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_uge_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -349,7 +349,7 @@ define void @icmp_uge_v2i64(ptr %a, ptr %b) #0 {
 ; ICMP UGT
 ;
 
-define void @icmp_ugt_v2i64(ptr %a, ptr %b) #0 {
+define void @icmp_ugt_v2i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_ugt_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -371,7 +371,7 @@ define void @icmp_ugt_v2i64(ptr %a, ptr %b) #0 {
 ; ICMP ULE
 ;
 
-define void @icmp_ule_v2i64(ptr %a, ptr %b) #0 {
+define void @icmp_ule_v2i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_ule_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -393,7 +393,7 @@ define void @icmp_ule_v2i64(ptr %a, ptr %b) #0 {
 ; ICMP ULT
 ;
 
-define void @icmp_ult_v2i64(ptr %a, ptr %b) #0 {
+define void @icmp_ult_v2i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: icmp_ult_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -410,5 +410,3 @@ define void @icmp_ult_v2i64(ptr %a, ptr %b) #0 {
   store <2 x i64> %sext, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
index 6a78eaa42c061..9b7ec3e423c2f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE2
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; SDIV
 ;
 
-define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: sdiv_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -26,7 +27,7 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: sdiv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -53,7 +54,7 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: sdiv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -101,7 +102,7 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @sdiv_v32i8(ptr %a, ptr %b) #0 {
+define void @sdiv_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: sdiv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q2, [x0]
@@ -182,7 +183,7 @@ define void @sdiv_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: sdiv_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -197,7 +198,7 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: sdiv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -213,7 +214,7 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: sdiv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -239,7 +240,7 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @sdiv_v16i16(ptr %a, ptr %b) #0 {
+define void @sdiv_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: sdiv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q3, q0, [x1]
@@ -278,7 +279,7 @@ define void @sdiv_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: sdiv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -291,7 +292,7 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: sdiv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -304,7 +305,7 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @sdiv_v8i32(ptr %a, ptr %b)  #0 {
+define void @sdiv_v8i32(ptr %a, ptr %b)  {
 ; CHECK-LABEL: sdiv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -321,7 +322,7 @@ define void @sdiv_v8i32(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: sdiv_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -334,7 +335,7 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: sdiv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -347,7 +348,7 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @sdiv_v4i64(ptr %a, ptr %b)  #0 {
+define void @sdiv_v4i64(ptr %a, ptr %b)  {
 ; CHECK-LABEL: sdiv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -368,7 +369,7 @@ define void @sdiv_v4i64(ptr %a, ptr %b)  #0 {
 ; UDIV
 ;
 
-define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: udiv_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -386,7 +387,7 @@ define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: udiv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -413,7 +414,7 @@ define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: udiv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -461,7 +462,7 @@ define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @udiv_v32i8(ptr %a, ptr %b) #0 {
+define void @udiv_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: udiv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q2, [x0]
@@ -542,7 +543,7 @@ define void @udiv_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: udiv_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -557,7 +558,7 @@ define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: udiv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -573,7 +574,7 @@ define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: udiv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -599,7 +600,7 @@ define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @udiv_v16i16(ptr %a, ptr %b) #0 {
+define void @udiv_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: udiv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q3, q0, [x1]
@@ -638,7 +639,7 @@ define void @udiv_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: udiv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -651,7 +652,7 @@ define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: udiv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -664,7 +665,7 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @udiv_v8i32(ptr %a, ptr %b)  #0 {
+define void @udiv_v8i32(ptr %a, ptr %b)  {
 ; CHECK-LABEL: udiv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -681,7 +682,7 @@ define void @udiv_v8i32(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: udiv_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -694,7 +695,7 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: udiv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -707,7 +708,7 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @udiv_v4i64(ptr %a, ptr %b)  #0 {
+define void @udiv_v4i64(ptr %a, ptr %b)  {
 ; CHECK-LABEL: udiv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -724,31 +725,46 @@ define void @udiv_v4i64(ptr %a, ptr %b)  #0 {
   ret void
 }
 
-define void @udiv_constantsplat_v8i32(ptr %a)  #0 {
-; CHECK-LABEL: udiv_constantsplat_v8i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    mov w8, #8969 // =0x2309
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    movk w8, #22765, lsl #16
-; CHECK-NEXT:    mov z2.s, w8
-; CHECK-NEXT:    movprfx z3, z0
-; CHECK-NEXT:    umulh z3.s, p0/m, z3.s, z2.s
-; CHECK-NEXT:    umulh z2.s, p0/m, z2.s, z1.s
-; CHECK-NEXT:    sub z0.s, z0.s, z3.s
-; CHECK-NEXT:    sub z1.s, z1.s, z2.s
-; CHECK-NEXT:    lsr z0.s, z0.s, #1
-; CHECK-NEXT:    lsr z1.s, z1.s, #1
-; CHECK-NEXT:    add z0.s, z0.s, z3.s
-; CHECK-NEXT:    add z1.s, z1.s, z2.s
-; CHECK-NEXT:    lsr z0.s, z0.s, #6
-; CHECK-NEXT:    lsr z1.s, z1.s, #6
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @udiv_constantsplat_v8i32(ptr %a)  {
+; SVE-LABEL: udiv_constantsplat_v8i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    mov w8, #8969 // =0x2309
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    movk w8, #22765, lsl #16
+; SVE-NEXT:    mov z2.s, w8
+; SVE-NEXT:    movprfx z3, z0
+; SVE-NEXT:    umulh z3.s, p0/m, z3.s, z2.s
+; SVE-NEXT:    umulh z2.s, p0/m, z2.s, z1.s
+; SVE-NEXT:    sub z0.s, z0.s, z3.s
+; SVE-NEXT:    sub z1.s, z1.s, z2.s
+; SVE-NEXT:    lsr z0.s, z0.s, #1
+; SVE-NEXT:    lsr z1.s, z1.s, #1
+; SVE-NEXT:    add z0.s, z0.s, z3.s
+; SVE-NEXT:    add z1.s, z1.s, z2.s
+; SVE-NEXT:    lsr z0.s, z0.s, #6
+; SVE-NEXT:    lsr z1.s, z1.s, #6
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: udiv_constantsplat_v8i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    mov w8, #8969 // =0x2309
+; SVE2-NEXT:    movk w8, #22765, lsl #16
+; SVE2-NEXT:    mov z2.s, w8
+; SVE2-NEXT:    umulh z3.s, z0.s, z2.s
+; SVE2-NEXT:    umulh z2.s, z1.s, z2.s
+; SVE2-NEXT:    sub z0.s, z0.s, z3.s
+; SVE2-NEXT:    sub z1.s, z1.s, z2.s
+; SVE2-NEXT:    usra z3.s, z0.s, #1
+; SVE2-NEXT:    usra z2.s, z1.s, #1
+; SVE2-NEXT:    lsr z0.s, z3.s, #6
+; SVE2-NEXT:    lsr z1.s, z2.s, #6
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %res = udiv <8 x i32> %op1, <i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95>
   store <8 x i32> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
index 95a224ac8ad18..9b79467c6df3c 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE2
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -10,7 +11,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg
 ; type's element type is not byte based and thus cannot be lowered directly to
 ; an SVE instruction.
-define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) #0 {
+define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) {
 ; CHECK-LABEL: sext_v8i1_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -36,7 +37,7 @@ define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) #0 {
 ; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg
 ; type's element type is not power-of-2 based and thus cannot be lowered
 ; directly to an SVE instruction.
-define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) #0 {
+define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) {
 ; CHECK-LABEL: sext_v4i3_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -59,7 +60,7 @@ define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) #0 {
 ; sext i8 -> i16
 ;
 
-define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
+define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) {
 ; CHECK-LABEL: sext_v16i8_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -74,7 +75,7 @@ define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the extend being combined with the load.
-define void @sext_v32i8_v32i16(ptr %in, ptr %out) #0 {
+define void @sext_v32i8_v32i16(ptr %in, ptr %out) {
 ; CHECK-LABEL: sext_v32i8_v32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -100,7 +101,7 @@ define void @sext_v32i8_v32i16(ptr %in, ptr %out) #0 {
 ; sext i8 -> i32
 ;
 
-define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
+define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) {
 ; CHECK-LABEL: sext_v8i8_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -115,7 +116,7 @@ define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
+define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) {
 ; CHECK-LABEL: sext_v16i8_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -136,7 +137,7 @@ define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v32i8_v32i32(ptr %in, ptr %out) #0 {
+define void @sext_v32i8_v32i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: sext_v32i8_v32i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -179,7 +180,7 @@ define void @sext_v32i8_v32i32(ptr %in, ptr %out) #0 {
 ; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The sign
 ; extend is a two step process where the container is any_extend'd with the
 ; result feeding an inreg sign extend.
-define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
+define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) {
 ; CHECK-LABEL: sext_v4i8_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -197,7 +198,7 @@ define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
+define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) {
 ; CHECK-LABEL: sext_v8i8_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -219,7 +220,7 @@ define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
+define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
 ; CHECK-LABEL: sext_v16i8_v16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -254,7 +255,7 @@ define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v32i8_v32i64(ptr %in, ptr %out) #0 {
+define void @sext_v32i8_v32i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: sext_v32i8_v32i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -322,7 +323,7 @@ define void @sext_v32i8_v32i64(ptr %in, ptr %out) #0 {
 ; sext i16 -> i32
 ;
 
-define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
+define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) {
 ; CHECK-LABEL: sext_v8i16_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -336,7 +337,7 @@ define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v16i16_v16i32(ptr %in, ptr %out) #0 {
+define void @sext_v16i16_v16i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: sext_v16i16_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -362,7 +363,7 @@ define void @sext_v16i16_v16i32(ptr %in, ptr %out) #0 {
 ; sext i16 -> i64
 ;
 
-define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
+define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) {
 ; CHECK-LABEL: sext_v4i16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -377,7 +378,7 @@ define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
+define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) {
 ; CHECK-LABEL: sext_v8i16_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -398,7 +399,7 @@ define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v16i16_v16i64(ptr %in, ptr %out) #0 {
+define void @sext_v16i16_v16i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: sext_v16i16_v16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -438,7 +439,7 @@ define void @sext_v16i16_v16i64(ptr %in, ptr %out) #0 {
 ; sext i32 -> i64
 ;
 
-define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
+define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) {
 ; CHECK-LABEL: sext_v4i32_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -452,7 +453,7 @@ define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
   ret void
 }
 
-define void @sext_v8i32_v8i64(ptr %in, ptr %out) #0 {
+define void @sext_v8i32_v8i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: sext_v8i32_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -478,7 +479,7 @@ define void @sext_v8i32_v8i64(ptr %in, ptr %out) #0 {
 ; zext i8 -> i16
 ;
 
-define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
+define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) {
 ; CHECK-LABEL: zext_v16i8_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -493,7 +494,7 @@ define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the extend being combined with the load.
-define void @zext_v32i8_v32i16(ptr %in, ptr %out) #0 {
+define void @zext_v32i8_v32i16(ptr %in, ptr %out) {
 ; CHECK-LABEL: zext_v32i8_v32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -519,7 +520,7 @@ define void @zext_v32i8_v32i16(ptr %in, ptr %out) #0 {
 ; zext i8 -> i32
 ;
 
-define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
+define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) {
 ; CHECK-LABEL: zext_v8i8_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -534,7 +535,7 @@ define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
+define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) {
 ; CHECK-LABEL: zext_v16i8_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -555,7 +556,7 @@ define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v32i8_v32i32(ptr %in, ptr %out) #0 {
+define void @zext_v32i8_v32i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: zext_v32i8_v32i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -598,7 +599,7 @@ define void @zext_v32i8_v32i32(ptr %in, ptr %out) #0 {
 ; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The zero
 ; extend is a two step process where the container is zero_extend_inreg'd with
 ; the result feeding a normal zero extend from halfs to doublewords.
-define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
+define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) {
 ; CHECK-LABEL: zext_v4i8_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -614,7 +615,7 @@ define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
+define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) {
 ; CHECK-LABEL: zext_v8i8_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -636,7 +637,7 @@ define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
+define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
 ; CHECK-LABEL: zext_v16i8_v16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -671,7 +672,7 @@ define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v32i8_v32i64(ptr %in, ptr %out) #0 {
+define void @zext_v32i8_v32i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: zext_v32i8_v32i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -739,7 +740,7 @@ define void @zext_v32i8_v32i64(ptr %in, ptr %out) #0 {
 ; zext i16 -> i32
 ;
 
-define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
+define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) {
 ; CHECK-LABEL: zext_v8i16_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -753,7 +754,7 @@ define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v16i16_v16i32(ptr %in, ptr %out) #0 {
+define void @zext_v16i16_v16i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: zext_v16i16_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -779,7 +780,7 @@ define void @zext_v16i16_v16i32(ptr %in, ptr %out) #0 {
 ; zext i16 -> i64
 ;
 
-define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
+define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) {
 ; CHECK-LABEL: zext_v4i16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -794,7 +795,7 @@ define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
+define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) {
 ; CHECK-LABEL: zext_v8i16_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -815,7 +816,7 @@ define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v16i16_v16i64(ptr %in, ptr %out) #0 {
+define void @zext_v16i16_v16i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: zext_v16i16_v16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -855,7 +856,7 @@ define void @zext_v16i16_v16i64(ptr %in, ptr %out) #0 {
 ; zext i32 -> i64
 ;
 
-define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
+define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) {
 ; CHECK-LABEL: zext_v4i32_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -869,7 +870,7 @@ define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
   ret void
 }
 
-define void @zext_v8i32_v8i64(ptr %in, ptr %out) #0 {
+define void @zext_v8i32_v8i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: zext_v8i32_v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -891,16 +892,25 @@ define void @zext_v8i32_v8i64(ptr %in, ptr %out) #0 {
   ret void
 }
 
-define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) #0 {
-; CHECK-LABEL: extend_and_mul:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z1.s, w0
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    uunpklo z1.d, z1.s
-; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    str q0, [x1]
-; CHECK-NEXT:    ret
+define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) {
+; SVE-LABEL: extend_and_mul:
+; SVE:       // %bb.0:
+; SVE-NEXT:    mov z1.s, w0
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    uunpklo z1.d, z1.s
+; SVE-NEXT:    mul z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    str q0, [x1]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: extend_and_mul:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    mov z1.s, w0
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    uunpklo z1.d, z1.s
+; SVE2-NEXT:    mul z0.d, z1.d, z0.d
+; SVE2-NEXT:    str q0, [x1]
+; SVE2-NEXT:    ret
   %broadcast.splatinsert2 = insertelement <2 x i32> poison, i32 %0, i64 0
   %broadcast.splat3 = shufflevector <2 x i32> %broadcast.splatinsert2, <2 x i32> poison, <2 x i32> zeroinitializer
   %4 = zext <2 x i32> %broadcast.splat3 to <2 x i64>
@@ -909,7 +919,7 @@ define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) #0 {
   ret void
 }
 
-define void @extend_no_mul(i32 %0, <2 x i64> %1, ptr %2) #0 {
+define void @extend_no_mul(i32 %0, <2 x i64> %1, ptr %2) {
 ; CHECK-LABEL: extend_no_mul:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    mov w8, w0
@@ -923,5 +933,3 @@ entry:
   store <2 x i64> %3, ptr %2, align 2
   ret void
 }
-
-attributes #0 = { nounwind "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
index 05c91065cbf60..df3b622c66f0c 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -13,7 +13,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; ADD
 ;
 
-define void @add_v32i8(ptr %a) #0 {
+define void @add_v32i8(ptr %a) {
 ; CHECK-LABEL: add_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -29,7 +29,7 @@ define void @add_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @add_v16i16(ptr %a) #0 {
+define void @add_v16i16(ptr %a) {
 ; CHECK-LABEL: add_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -45,7 +45,7 @@ define void @add_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @add_v8i32(ptr %a) #0 {
+define void @add_v8i32(ptr %a) {
 ; CHECK-LABEL: add_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -61,7 +61,7 @@ define void @add_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @add_v4i64(ptr %a) #0 {
+define void @add_v4i64(ptr %a) {
 ; CHECK-LABEL: add_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -81,7 +81,7 @@ define void @add_v4i64(ptr %a) #0 {
 ; AND
 ;
 
-define void @and_v32i8(ptr %a) #0 {
+define void @and_v32i8(ptr %a) {
 ; CHECK-LABEL: and_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -97,7 +97,7 @@ define void @and_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @and_v16i16(ptr %a) #0 {
+define void @and_v16i16(ptr %a) {
 ; CHECK-LABEL: and_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -113,7 +113,7 @@ define void @and_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @and_v8i32(ptr %a) #0 {
+define void @and_v8i32(ptr %a) {
 ; CHECK-LABEL: and_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -129,7 +129,7 @@ define void @and_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @and_v4i64(ptr %a) #0 {
+define void @and_v4i64(ptr %a) {
 ; CHECK-LABEL: and_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -149,7 +149,7 @@ define void @and_v4i64(ptr %a) #0 {
 ; ASHR
 ;
 
-define void @ashr_v32i8(ptr %a) #0 {
+define void @ashr_v32i8(ptr %a) {
 ; CHECK-LABEL: ashr_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -165,7 +165,7 @@ define void @ashr_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @ashr_v16i16(ptr %a) #0 {
+define void @ashr_v16i16(ptr %a) {
 ; CHECK-LABEL: ashr_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -181,7 +181,7 @@ define void @ashr_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @ashr_v8i32(ptr %a) #0 {
+define void @ashr_v8i32(ptr %a) {
 ; CHECK-LABEL: ashr_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -197,7 +197,7 @@ define void @ashr_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @ashr_v4i64(ptr %a) #0 {
+define void @ashr_v4i64(ptr %a) {
 ; CHECK-LABEL: ashr_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -217,7 +217,7 @@ define void @ashr_v4i64(ptr %a) #0 {
 ; ICMP
 ;
 
-define void @icmp_eq_v32i8(ptr %a) #0 {
+define void @icmp_eq_v32i8(ptr %a) {
 ; CHECK-LABEL: icmp_eq_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -237,7 +237,7 @@ define void @icmp_eq_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @icmp_sge_v16i16(ptr %a) #0 {
+define void @icmp_sge_v16i16(ptr %a) {
 ; CHECK-LABEL: icmp_sge_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -257,7 +257,7 @@ define void @icmp_sge_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @icmp_sgt_v8i32(ptr %a) #0 {
+define void @icmp_sgt_v8i32(ptr %a) {
 ; CHECK-LABEL: icmp_sgt_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -277,7 +277,7 @@ define void @icmp_sgt_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @icmp_ult_v4i64(ptr %a) #0 {
+define void @icmp_ult_v4i64(ptr %a) {
 ; CHECK-LABEL: icmp_ult_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -301,7 +301,7 @@ define void @icmp_ult_v4i64(ptr %a) #0 {
 ; LSHR
 ;
 
-define void @lshr_v32i8(ptr %a) #0 {
+define void @lshr_v32i8(ptr %a) {
 ; CHECK-LABEL: lshr_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -317,7 +317,7 @@ define void @lshr_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @lshr_v16i16(ptr %a) #0 {
+define void @lshr_v16i16(ptr %a) {
 ; CHECK-LABEL: lshr_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -333,7 +333,7 @@ define void @lshr_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @lshr_v8i32(ptr %a) #0 {
+define void @lshr_v8i32(ptr %a) {
 ; CHECK-LABEL: lshr_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -349,7 +349,7 @@ define void @lshr_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @lshr_v4i64(ptr %a) #0 {
+define void @lshr_v4i64(ptr %a) {
 ; CHECK-LABEL: lshr_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -369,7 +369,7 @@ define void @lshr_v4i64(ptr %a) #0 {
 ; MUL
 ;
 
-define void @mul_v32i8(ptr %a) #0 {
+define void @mul_v32i8(ptr %a) {
 ; CHECK-LABEL: mul_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -385,7 +385,7 @@ define void @mul_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @mul_v16i16(ptr %a) #0 {
+define void @mul_v16i16(ptr %a) {
 ; CHECK-LABEL: mul_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -401,7 +401,7 @@ define void @mul_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @mul_v8i32(ptr %a) #0 {
+define void @mul_v8i32(ptr %a) {
 ; CHECK-LABEL: mul_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -417,7 +417,7 @@ define void @mul_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @mul_v4i64(ptr %a) #0 {
+define void @mul_v4i64(ptr %a) {
 ; CHECK-LABEL: mul_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -437,7 +437,7 @@ define void @mul_v4i64(ptr %a) #0 {
 ; OR
 ;
 
-define void @or_v32i8(ptr %a) #0 {
+define void @or_v32i8(ptr %a) {
 ; CHECK-LABEL: or_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -453,7 +453,7 @@ define void @or_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @or_v16i16(ptr %a) #0 {
+define void @or_v16i16(ptr %a) {
 ; CHECK-LABEL: or_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -469,7 +469,7 @@ define void @or_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @or_v8i32(ptr %a) #0 {
+define void @or_v8i32(ptr %a) {
 ; CHECK-LABEL: or_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -485,7 +485,7 @@ define void @or_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @or_v4i64(ptr %a) #0 {
+define void @or_v4i64(ptr %a) {
 ; CHECK-LABEL: or_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -505,7 +505,7 @@ define void @or_v4i64(ptr %a) #0 {
 ; SHL
 ;
 
-define void @shl_v32i8(ptr %a) #0 {
+define void @shl_v32i8(ptr %a) {
 ; CHECK-LABEL: shl_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -521,7 +521,7 @@ define void @shl_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @shl_v16i16(ptr %a) #0 {
+define void @shl_v16i16(ptr %a) {
 ; CHECK-LABEL: shl_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -537,7 +537,7 @@ define void @shl_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @shl_v8i32(ptr %a) #0 {
+define void @shl_v8i32(ptr %a) {
 ; CHECK-LABEL: shl_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -553,7 +553,7 @@ define void @shl_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @shl_v4i64(ptr %a) #0 {
+define void @shl_v4i64(ptr %a) {
 ; CHECK-LABEL: shl_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -573,7 +573,7 @@ define void @shl_v4i64(ptr %a) #0 {
 ; SMAX
 ;
 
-define void @smax_v32i8(ptr %a) #0 {
+define void @smax_v32i8(ptr %a) {
 ; CHECK-LABEL: smax_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -589,7 +589,7 @@ define void @smax_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @smax_v16i16(ptr %a) #0 {
+define void @smax_v16i16(ptr %a) {
 ; CHECK-LABEL: smax_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -605,7 +605,7 @@ define void @smax_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @smax_v8i32(ptr %a) #0 {
+define void @smax_v8i32(ptr %a) {
 ; CHECK-LABEL: smax_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -621,7 +621,7 @@ define void @smax_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @smax_v4i64(ptr %a) #0 {
+define void @smax_v4i64(ptr %a) {
 ; CHECK-LABEL: smax_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -641,7 +641,7 @@ define void @smax_v4i64(ptr %a) #0 {
 ; SMIN
 ;
 
-define void @smin_v32i8(ptr %a) #0 {
+define void @smin_v32i8(ptr %a) {
 ; CHECK-LABEL: smin_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -657,7 +657,7 @@ define void @smin_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @smin_v16i16(ptr %a) #0 {
+define void @smin_v16i16(ptr %a) {
 ; CHECK-LABEL: smin_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -673,7 +673,7 @@ define void @smin_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @smin_v8i32(ptr %a) #0 {
+define void @smin_v8i32(ptr %a) {
 ; CHECK-LABEL: smin_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -689,7 +689,7 @@ define void @smin_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @smin_v4i64(ptr %a) #0 {
+define void @smin_v4i64(ptr %a) {
 ; CHECK-LABEL: smin_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -709,7 +709,7 @@ define void @smin_v4i64(ptr %a) #0 {
 ; SUB
 ;
 
-define void @sub_v32i8(ptr %a) #0 {
+define void @sub_v32i8(ptr %a) {
 ; CHECK-LABEL: sub_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -725,7 +725,7 @@ define void @sub_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @sub_v16i16(ptr %a) #0 {
+define void @sub_v16i16(ptr %a) {
 ; CHECK-LABEL: sub_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -741,7 +741,7 @@ define void @sub_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @sub_v8i32(ptr %a) #0 {
+define void @sub_v8i32(ptr %a) {
 ; CHECK-LABEL: sub_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -757,7 +757,7 @@ define void @sub_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @sub_v4i64(ptr %a) #0 {
+define void @sub_v4i64(ptr %a) {
 ; CHECK-LABEL: sub_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -777,7 +777,7 @@ define void @sub_v4i64(ptr %a) #0 {
 ; UMAX
 ;
 
-define void @umax_v32i8(ptr %a) #0 {
+define void @umax_v32i8(ptr %a) {
 ; CHECK-LABEL: umax_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -793,7 +793,7 @@ define void @umax_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @umax_v16i16(ptr %a) #0 {
+define void @umax_v16i16(ptr %a) {
 ; CHECK-LABEL: umax_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -809,7 +809,7 @@ define void @umax_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @umax_v8i32(ptr %a) #0 {
+define void @umax_v8i32(ptr %a) {
 ; CHECK-LABEL: umax_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -825,7 +825,7 @@ define void @umax_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @umax_v4i64(ptr %a) #0 {
+define void @umax_v4i64(ptr %a) {
 ; CHECK-LABEL: umax_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -845,7 +845,7 @@ define void @umax_v4i64(ptr %a) #0 {
 ; UMIN
 ;
 
-define void @umin_v32i8(ptr %a) #0 {
+define void @umin_v32i8(ptr %a) {
 ; CHECK-LABEL: umin_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -861,7 +861,7 @@ define void @umin_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @umin_v16i16(ptr %a) #0 {
+define void @umin_v16i16(ptr %a) {
 ; CHECK-LABEL: umin_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -877,7 +877,7 @@ define void @umin_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @umin_v8i32(ptr %a) #0 {
+define void @umin_v8i32(ptr %a) {
 ; CHECK-LABEL: umin_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -893,7 +893,7 @@ define void @umin_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @umin_v4i64(ptr %a) #0 {
+define void @umin_v4i64(ptr %a) {
 ; CHECK-LABEL: umin_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -913,7 +913,7 @@ define void @umin_v4i64(ptr %a) #0 {
 ; XOR
 ;
 
-define void @xor_v32i8(ptr %a) #0 {
+define void @xor_v32i8(ptr %a) {
 ; CHECK-LABEL: xor_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -929,7 +929,7 @@ define void @xor_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @xor_v16i16(ptr %a) #0 {
+define void @xor_v16i16(ptr %a) {
 ; CHECK-LABEL: xor_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -945,7 +945,7 @@ define void @xor_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @xor_v8i32(ptr %a) #0 {
+define void @xor_v8i32(ptr %a) {
 ; CHECK-LABEL: xor_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -961,7 +961,7 @@ define void @xor_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @xor_v4i64(ptr %a) #0 {
+define void @xor_v4i64(ptr %a) {
 ; CHECK-LABEL: xor_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -996,5 +996,3 @@ declare <32 x i8> @llvm.umin.v32i8(<32 x i8>, <32 x i8>)
 declare <16 x i16> @llvm.umin.v16i16(<16 x i16>, <16 x i16>)
 declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
 declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
index d2eea846425ef..052d5245b9522 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; AND
 ;
 
-define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: and_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -19,7 +19,7 @@ define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: and_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -31,7 +31,7 @@ define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @and_v32i8(ptr %a, ptr %b) #0 {
+define void @and_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: and_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -47,7 +47,7 @@ define void @and_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: and_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -59,7 +59,7 @@ define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: and_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -71,7 +71,7 @@ define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @and_v16i16(ptr %a, ptr %b) #0 {
+define void @and_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: and_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -87,7 +87,7 @@ define void @and_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: and_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -99,7 +99,7 @@ define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: and_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -111,7 +111,7 @@ define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @and_v8i32(ptr %a, ptr %b) #0 {
+define void @and_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: and_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -127,7 +127,7 @@ define void @and_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: and_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -139,7 +139,7 @@ define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: and_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -151,7 +151,7 @@ define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @and_v4i64(ptr %a, ptr %b) #0 {
+define void @and_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: and_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -171,7 +171,7 @@ define void @and_v4i64(ptr %a, ptr %b) #0 {
 ; OR
 ;
 
-define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: or_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -183,7 +183,7 @@ define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: or_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -195,7 +195,7 @@ define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @or_v32i8(ptr %a, ptr %b) #0 {
+define void @or_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: or_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -211,7 +211,7 @@ define void @or_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: or_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -223,7 +223,7 @@ define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: or_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -235,7 +235,7 @@ define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @or_v16i16(ptr %a, ptr %b) #0 {
+define void @or_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: or_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -251,7 +251,7 @@ define void @or_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: or_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -263,7 +263,7 @@ define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: or_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -275,7 +275,7 @@ define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @or_v8i32(ptr %a, ptr %b) #0 {
+define void @or_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: or_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -291,7 +291,7 @@ define void @or_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: or_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -303,7 +303,7 @@ define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: or_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -315,7 +315,7 @@ define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @or_v4i64(ptr %a, ptr %b) #0 {
+define void @or_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: or_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -335,7 +335,7 @@ define void @or_v4i64(ptr %a, ptr %b) #0 {
 ; XOR
 ;
 
-define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: xor_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -347,7 +347,7 @@ define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: xor_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -359,7 +359,7 @@ define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @xor_v32i8(ptr %a, ptr %b) #0 {
+define void @xor_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: xor_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -375,7 +375,7 @@ define void @xor_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: xor_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -387,7 +387,7 @@ define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: xor_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -399,7 +399,7 @@ define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @xor_v16i16(ptr %a, ptr %b) #0 {
+define void @xor_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: xor_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -415,7 +415,7 @@ define void @xor_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: xor_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -427,7 +427,7 @@ define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: xor_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -439,7 +439,7 @@ define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @xor_v8i32(ptr %a, ptr %b) #0 {
+define void @xor_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: xor_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -455,7 +455,7 @@ define void @xor_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: xor_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -467,7 +467,7 @@ define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: xor_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -479,7 +479,7 @@ define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @xor_v4i64(ptr %a, ptr %b) #0 {
+define void @xor_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: xor_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -494,5 +494,3 @@ define void @xor_v4i64(ptr %a, ptr %b) #0 {
   store <4 x i64> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
index 86ea36ca1fb4d..02c60fbf99bb3 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; SMAX
 ;
 
-define <8 x i8> @smax_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @smax_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: smax_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -20,7 +20,7 @@ define <8 x i8> @smax_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: smax_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -33,7 +33,7 @@ define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @smax_v32i8(ptr %a, ptr %b) #0 {
+define void @smax_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: smax_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -50,7 +50,7 @@ define void @smax_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @smax_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @smax_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: smax_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -63,7 +63,7 @@ define <4 x i16> @smax_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: smax_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -76,7 +76,7 @@ define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @smax_v16i16(ptr %a, ptr %b) #0 {
+define void @smax_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: smax_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -93,7 +93,7 @@ define void @smax_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @smax_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @smax_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: smax_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -106,7 +106,7 @@ define <2 x i32> @smax_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: smax_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -119,7 +119,7 @@ define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @smax_v8i32(ptr %a, ptr %b) #0 {
+define void @smax_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: smax_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -137,7 +137,7 @@ define void @smax_v8i32(ptr %a, ptr %b) #0 {
 }
 
 ; Vector i64 max are not legal for NEON so use SVE when available.
-define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: smax_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -151,7 +151,7 @@ define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
 }
 
 ; Vector i64 max are not legal for NEON so use SVE when available.
-define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: smax_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -164,7 +164,7 @@ define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @smax_v4i64(ptr %a, ptr %b) #0 {
+define void @smax_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: smax_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -185,7 +185,7 @@ define void @smax_v4i64(ptr %a, ptr %b) #0 {
 ; SMIN
 ;
 
-define <8 x i8> @smin_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @smin_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: smin_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -198,7 +198,7 @@ define <8 x i8> @smin_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: smin_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -211,7 +211,7 @@ define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @smin_v32i8(ptr %a, ptr %b) #0 {
+define void @smin_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: smin_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -228,7 +228,7 @@ define void @smin_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @smin_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @smin_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: smin_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -241,7 +241,7 @@ define <4 x i16> @smin_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: smin_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -254,7 +254,7 @@ define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @smin_v16i16(ptr %a, ptr %b) #0 {
+define void @smin_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: smin_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -271,7 +271,7 @@ define void @smin_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @smin_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @smin_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: smin_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -284,7 +284,7 @@ define <2 x i32> @smin_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: smin_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -297,7 +297,7 @@ define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @smin_v8i32(ptr %a, ptr %b) #0 {
+define void @smin_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: smin_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -315,7 +315,7 @@ define void @smin_v8i32(ptr %a, ptr %b) #0 {
 }
 
 ; Vector i64 min are not legal for NEON so use SVE when available.
-define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: smin_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -329,7 +329,7 @@ define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
 }
 
 ; Vector i64 min are not legal for NEON so use SVE when available.
-define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: smin_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -342,7 +342,7 @@ define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @smin_v4i64(ptr %a, ptr %b) #0 {
+define void @smin_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: smin_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -363,7 +363,7 @@ define void @smin_v4i64(ptr %a, ptr %b) #0 {
 ; UMAX
 ;
 
-define <8 x i8> @umax_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @umax_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: umax_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -376,7 +376,7 @@ define <8 x i8> @umax_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: umax_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -389,7 +389,7 @@ define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @umax_v32i8(ptr %a, ptr %b) #0 {
+define void @umax_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: umax_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -406,7 +406,7 @@ define void @umax_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @umax_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @umax_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: umax_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -419,7 +419,7 @@ define <4 x i16> @umax_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: umax_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -432,7 +432,7 @@ define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @umax_v16i16(ptr %a, ptr %b) #0 {
+define void @umax_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: umax_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -449,7 +449,7 @@ define void @umax_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @umax_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @umax_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: umax_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -462,7 +462,7 @@ define <2 x i32> @umax_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: umax_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -475,7 +475,7 @@ define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @umax_v8i32(ptr %a, ptr %b) #0 {
+define void @umax_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: umax_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -493,7 +493,7 @@ define void @umax_v8i32(ptr %a, ptr %b) #0 {
 }
 
 ; Vector i64 max are not legal for NEON so use SVE when available.
-define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: umax_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -507,7 +507,7 @@ define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
 }
 
 ; Vector i64 max are not legal for NEON so use SVE when available.
-define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: umax_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -520,7 +520,7 @@ define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @umax_v4i64(ptr %a, ptr %b) #0 {
+define void @umax_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: umax_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -541,7 +541,7 @@ define void @umax_v4i64(ptr %a, ptr %b) #0 {
 ; UMIN
 ;
 
-define <8 x i8> @umin_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @umin_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: umin_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -554,7 +554,7 @@ define <8 x i8> @umin_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: umin_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -567,7 +567,7 @@ define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @umin_v32i8(ptr %a, ptr %b) #0 {
+define void @umin_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: umin_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -584,7 +584,7 @@ define void @umin_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @umin_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @umin_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: umin_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -597,7 +597,7 @@ define <4 x i16> @umin_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: umin_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -610,7 +610,7 @@ define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @umin_v16i16(ptr %a, ptr %b) #0 {
+define void @umin_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: umin_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -627,7 +627,7 @@ define void @umin_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @umin_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @umin_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: umin_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -640,7 +640,7 @@ define <2 x i32> @umin_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: umin_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -653,7 +653,7 @@ define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @umin_v8i32(ptr %a, ptr %b) #0 {
+define void @umin_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: umin_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -671,7 +671,7 @@ define void @umin_v8i32(ptr %a, ptr %b) #0 {
 }
 
 ; Vector i64 min are not legal for NEON so use SVE when available.
-define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: umin_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -685,7 +685,7 @@ define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
 }
 
 ; Vector i64 min are not legal for NEON so use SVE when available.
-define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: umin_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -698,7 +698,7 @@ define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @umin_v4i64(ptr %a, ptr %b) #0 {
+define void @umin_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: umin_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -715,8 +715,6 @@ define void @umin_v4i64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare <8 x i8> @llvm.smin.v8i8(<8 x i8>, <8 x i8>)
 declare <16 x i8> @llvm.smin.v16i8(<16 x i8>, <16 x i8>)
 declare <32 x i8> @llvm.smin.v32i8(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
index 8e87f8bb0208e..b6a9acb4d550e 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve  < %s | FileCheck %s --check-prefixes=CHECK,SVE2
 
 ; This test only tests the legal types for a given vector width, as mulh nodes
 ; do not get generated for non-legal types.
@@ -10,18 +11,30 @@ target triple = "aarch64-unknown-linux-gnu"
 ; SMULH
 ;
 
-define <4 x i8> @smulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
-; CHECK-LABEL: smulh_v4i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
-; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
-; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    lsr z0.h, z0.h, #4
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i8> @smulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
+; SVE-LABEL: smulh_v4i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    sxtb z0.h, p0/m, z0.h
+; SVE-NEXT:    sxtb z1.h, p0/m, z1.h
+; SVE-NEXT:    mul z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    lsr z0.h, z0.h, #4
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v4i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    ptrue p0.h, vl4
+; SVE2-NEXT:    sxtb z0.h, p0/m, z0.h
+; SVE2-NEXT:    sxtb z1.h, p0/m, z1.h
+; SVE2-NEXT:    mul z0.h, z0.h, z1.h
+; SVE2-NEXT:    lsr z0.h, z0.h, #4
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %insert = insertelement <4 x i16> undef, i16 4, i64 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> undef, <4 x i32> zeroinitializer
   %1 = sext <4 x i8> %op1 to <4 x i16>
@@ -32,15 +45,23 @@ define <4 x i8> @smulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: smulh_v8i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.b, vl8
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
+; SVE-LABEL: smulh_v8i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.b, vl8
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    smulh z0.b, p0/m, z0.b, z1.b
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v8i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    smulh z0.b, z0.b, z1.b
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %insert = insertelement <8 x i16> undef, i16 8, i64 0
   %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
   %1 = sext <8 x i8> %op1 to <8 x i16>
@@ -51,15 +72,23 @@ define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: smulh_v16i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
+; SVE-LABEL: smulh_v16i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.b, vl16
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    smulh z0.b, p0/m, z0.b, z1.b
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v16i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    smulh z0.b, z0.b, z1.b
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <16 x i8> %op1 to <16 x i16>
   %2 = sext <16 x i8> %op2 to <16 x i16>
   %mul = mul <16 x i16> %1, %2
@@ -68,16 +97,25 @@ define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @smulh_v32i8(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: smulh_v32i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    smulh z1.b, p0/m, z1.b, z3.b
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @smulh_v32i8(ptr %a, ptr %b) {
+; SVE-LABEL: smulh_v32i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.b, vl16
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    smulh z0.b, p0/m, z0.b, z2.b
+; SVE-NEXT:    smulh z1.b, p0/m, z1.b, z3.b
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v32i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    smulh z0.b, z0.b, z2.b
+; SVE2-NEXT:    smulh z1.b, z1.b, z3.b
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %op2 = load <32 x i8>, ptr %b
   %1 = sext <32 x i8> %op1 to <32 x i16>
@@ -89,18 +127,30 @@ define void @smulh_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @smulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
-; CHECK-LABEL: smulh_v2i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    sxth z0.s, p0/m, z0.s
-; CHECK-NEXT:    sxth z1.s, p0/m, z1.s
-; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    lsr z0.s, z0.s, #16
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i16> @smulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
+; SVE-LABEL: smulh_v2i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    sxth z0.s, p0/m, z0.s
+; SVE-NEXT:    sxth z1.s, p0/m, z1.s
+; SVE-NEXT:    mul z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    lsr z0.s, z0.s, #16
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v2i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    ptrue p0.s, vl2
+; SVE2-NEXT:    sxth z0.s, p0/m, z0.s
+; SVE2-NEXT:    sxth z1.s, p0/m, z1.s
+; SVE2-NEXT:    mul z0.s, z0.s, z1.s
+; SVE2-NEXT:    lsr z0.s, z0.s, #16
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <2 x i16> %op1 to <2 x i32>
   %2 = sext <2 x i16> %op2 to <2 x i32>
   %mul = mul <2 x i32> %1, %2
@@ -109,15 +159,23 @@ define <2 x i16> @smulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: smulh_v4i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
+; SVE-LABEL: smulh_v4i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    smulh z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v4i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    smulh z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <4 x i16> %op1 to <4 x i32>
   %2 = sext <4 x i16> %op2 to <4 x i32>
   %mul = mul <4 x i32> %1, %2
@@ -126,15 +184,23 @@ define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: smulh_v8i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
+; SVE-LABEL: smulh_v8i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl8
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    smulh z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v8i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    smulh z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <8 x i16> %op1 to <8 x i32>
   %2 = sext <8 x i16> %op2 to <8 x i32>
   %mul = mul <8 x i32> %1, %2
@@ -143,16 +209,25 @@ define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @smulh_v16i16(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: smulh_v16i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    smulh z1.h, p0/m, z1.h, z3.h
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @smulh_v16i16(ptr %a, ptr %b) {
+; SVE-LABEL: smulh_v16i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.h, vl8
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    smulh z0.h, p0/m, z0.h, z2.h
+; SVE-NEXT:    smulh z1.h, p0/m, z1.h, z3.h
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v16i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    smulh z0.h, z0.h, z2.h
+; SVE2-NEXT:    smulh z1.h, z1.h, z3.h
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %op2 = load <16 x i16>, ptr %b
   %1 = sext <16 x i16> %op1 to <16 x i32>
@@ -164,15 +239,23 @@ define void @smulh_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @smulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: smulh_v2i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i32> @smulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
+; SVE-LABEL: smulh_v2i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v2i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    smulh z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <2 x i32> %op1 to <2 x i64>
   %2 = sext <2 x i32> %op2 to <2 x i64>
   %mul = mul <2 x i64> %1, %2
@@ -181,15 +264,23 @@ define <2 x i32> @smulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: smulh_v4i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
+; SVE-LABEL: smulh_v4i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v4i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    smulh z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <4 x i32> %op1 to <4 x i64>
   %2 = sext <4 x i32> %op2 to <4 x i64>
   %mul = mul <4 x i64> %1, %2
@@ -198,16 +289,25 @@ define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @smulh_v8i32(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: smulh_v8i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    smulh z1.s, p0/m, z1.s, z3.s
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @smulh_v8i32(ptr %a, ptr %b) {
+; SVE-LABEL: smulh_v8i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    smulh z0.s, p0/m, z0.s, z2.s
+; SVE-NEXT:    smulh z1.s, p0/m, z1.s, z3.s
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v8i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    smulh z0.s, z0.s, z2.s
+; SVE2-NEXT:    smulh z1.s, z1.s, z3.s
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %op2 = load <8 x i32>, ptr %b
   %1 = sext <8 x i32> %op1 to <8 x i64>
@@ -219,15 +319,23 @@ define void @smulh_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: smulh_v1i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl1
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
+; SVE-LABEL: smulh_v1i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl1
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    smulh z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v1i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    smulh z0.d, z0.d, z1.d
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %insert = insertelement <1 x i128> undef, i128 64, i128 0
   %splat = shufflevector <1 x i128> %insert, <1 x i128> undef, <1 x i32> zeroinitializer
   %1 = sext <1 x i64> %op1 to <1 x i128>
@@ -238,15 +346,23 @@ define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: smulh_v2i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
+; SVE-LABEL: smulh_v2i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    smulh z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v2i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    smulh z0.d, z0.d, z1.d
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = sext <2 x i64> %op1 to <2 x i128>
   %2 = sext <2 x i64> %op2 to <2 x i128>
   %mul = mul <2 x i128> %1, %2
@@ -255,16 +371,25 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @smulh_v4i64(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: smulh_v4i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    smulh z1.d, p0/m, z1.d, z3.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @smulh_v4i64(ptr %a, ptr %b) {
+; SVE-LABEL: smulh_v4i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    smulh z0.d, p0/m, z0.d, z2.d
+; SVE-NEXT:    smulh z1.d, p0/m, z1.d, z3.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: smulh_v4i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    smulh z0.d, z0.d, z2.d
+; SVE2-NEXT:    smulh z1.d, z1.d, z3.d
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %op2 = load <4 x i64>, ptr %b
   %1 = sext <4 x i64> %op1 to <4 x i128>
@@ -280,18 +405,29 @@ define void @smulh_v4i64(ptr %a, ptr %b) #0 {
 ; UMULH
 ;
 
-define <4 x i8> @umulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
-; CHECK-LABEL: umulh_v4i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    and z0.h, z0.h, #0xff
-; CHECK-NEXT:    and z1.h, z1.h, #0xff
-; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    lsr z0.h, z0.h, #4
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i8> @umulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
+; SVE-LABEL: umulh_v4i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    and z0.h, z0.h, #0xff
+; SVE-NEXT:    and z1.h, z1.h, #0xff
+; SVE-NEXT:    mul z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    lsr z0.h, z0.h, #4
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v4i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    and z0.h, z0.h, #0xff
+; SVE2-NEXT:    and z1.h, z1.h, #0xff
+; SVE2-NEXT:    mul z0.h, z0.h, z1.h
+; SVE2-NEXT:    lsr z0.h, z0.h, #4
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <4 x i8> %op1 to <4 x i16>
   %2 = zext <4 x i8> %op2 to <4 x i16>
   %mul = mul <4 x i16> %1, %2
@@ -300,15 +436,23 @@ define <4 x i8> @umulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: umulh_v8i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.b, vl8
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    umulh z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
+; SVE-LABEL: umulh_v8i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.b, vl8
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    umulh z0.b, p0/m, z0.b, z1.b
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v8i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    umulh z0.b, z0.b, z1.b
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <8 x i8> %op1 to <8 x i16>
   %2 = zext <8 x i8> %op2 to <8 x i16>
   %mul = mul <8 x i16> %1, %2
@@ -317,15 +461,23 @@ define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: umulh_v16i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    umulh z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
+; SVE-LABEL: umulh_v16i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.b, vl16
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    umulh z0.b, p0/m, z0.b, z1.b
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v16i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    umulh z0.b, z0.b, z1.b
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <16 x i8> %op1 to <16 x i16>
   %2 = zext <16 x i8> %op2 to <16 x i16>
   %mul = mul <16 x i16> %1, %2
@@ -334,16 +486,25 @@ define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @umulh_v32i8(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: umulh_v32i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    umulh z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    umulh z1.b, p0/m, z1.b, z3.b
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @umulh_v32i8(ptr %a, ptr %b) {
+; SVE-LABEL: umulh_v32i8:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.b, vl16
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    umulh z0.b, p0/m, z0.b, z2.b
+; SVE-NEXT:    umulh z1.b, p0/m, z1.b, z3.b
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v32i8:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    umulh z0.b, z0.b, z2.b
+; SVE2-NEXT:    umulh z1.b, z1.b, z3.b
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %op2 = load <32 x i8>, ptr %b
   %1 = zext <32 x i8> %op1 to <32 x i16>
@@ -355,18 +516,29 @@ define void @umulh_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @umulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
-; CHECK-LABEL: umulh_v2i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    and z0.s, z0.s, #0xffff
-; CHECK-NEXT:    and z1.s, z1.s, #0xffff
-; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    lsr z0.s, z0.s, #16
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i16> @umulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
+; SVE-LABEL: umulh_v2i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    and z0.s, z0.s, #0xffff
+; SVE-NEXT:    and z1.s, z1.s, #0xffff
+; SVE-NEXT:    mul z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    lsr z0.s, z0.s, #16
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v2i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    and z0.s, z0.s, #0xffff
+; SVE2-NEXT:    and z1.s, z1.s, #0xffff
+; SVE2-NEXT:    mul z0.s, z0.s, z1.s
+; SVE2-NEXT:    lsr z0.s, z0.s, #16
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <2 x i16> %op1 to <2 x i32>
   %2 = zext <2 x i16> %op2 to <2 x i32>
   %mul = mul <2 x i32> %1, %2
@@ -375,15 +547,23 @@ define <2 x i16> @umulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @umulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: umulh_v4i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    umulh z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i16> @umulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
+; SVE-LABEL: umulh_v4i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl4
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    umulh z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v4i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    umulh z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <4 x i16> %op1 to <4 x i32>
   %2 = zext <4 x i16> %op2 to <4 x i32>
   %mul = mul <4 x i32> %1, %2
@@ -392,15 +572,23 @@ define <4 x i16> @umulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: umulh_v8i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    umulh z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
+; SVE-LABEL: umulh_v8i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.h, vl8
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    umulh z0.h, p0/m, z0.h, z1.h
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v8i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    umulh z0.h, z0.h, z1.h
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <8 x i16> %op1 to <8 x i32>
   %2 = zext <8 x i16> %op2 to <8 x i32>
   %mul = mul <8 x i32> %1, %2
@@ -409,16 +597,25 @@ define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @umulh_v16i16(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: umulh_v16i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    umulh z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    umulh z1.h, p0/m, z1.h, z3.h
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @umulh_v16i16(ptr %a, ptr %b) {
+; SVE-LABEL: umulh_v16i16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.h, vl8
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    umulh z0.h, p0/m, z0.h, z2.h
+; SVE-NEXT:    umulh z1.h, p0/m, z1.h, z3.h
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v16i16:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    umulh z0.h, z0.h, z2.h
+; SVE2-NEXT:    umulh z1.h, z1.h, z3.h
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %op2 = load <16 x i16>, ptr %b
   %1 = zext <16 x i16> %op1 to <16 x i32>
@@ -430,15 +627,23 @@ define void @umulh_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @umulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: umulh_v2i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    umulh z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i32> @umulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
+; SVE-LABEL: umulh_v2i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl2
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    umulh z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v2i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    umulh z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <2 x i32> %op1 to <2 x i64>
   %2 = zext <2 x i32> %op2 to <2 x i64>
   %mul = mul <2 x i64> %1, %2
@@ -447,15 +652,23 @@ define <2 x i32> @umulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: umulh_v4i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    umulh z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
+; SVE-LABEL: umulh_v4i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    umulh z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v4i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    umulh z0.s, z0.s, z1.s
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <4 x i32> %op1 to <4 x i64>
   %2 = zext <4 x i32> %op2 to <4 x i64>
   %mul = mul <4 x i64> %1, %2
@@ -464,16 +677,25 @@ define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @umulh_v8i32(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: umulh_v8i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    umulh z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    umulh z1.s, p0/m, z1.s, z3.s
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @umulh_v8i32(ptr %a, ptr %b) {
+; SVE-LABEL: umulh_v8i32:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.s, vl4
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    umulh z0.s, p0/m, z0.s, z2.s
+; SVE-NEXT:    umulh z1.s, p0/m, z1.s, z3.s
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v8i32:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    umulh z0.s, z0.s, z2.s
+; SVE2-NEXT:    umulh z1.s, z1.s, z3.s
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %op2 = load <8 x i32>, ptr %b
   %insert = insertelement <8 x i64> undef, i64 32, i64 0
@@ -487,15 +709,23 @@ define void @umulh_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: umulh_v1i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl1
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    umulh z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    ret
+define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
+; SVE-LABEL: umulh_v1i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl1
+; SVE-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE-NEXT:    umulh z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v1i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $d0 killed $d0 def $z0
+; SVE2-NEXT:    // kill: def $d1 killed $d1 def $z1
+; SVE2-NEXT:    umulh z0.d, z0.d, z1.d
+; SVE2-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <1 x i64> %op1 to <1 x i128>
   %2 = zext <1 x i64> %op2 to <1 x i128>
   %mul = mul <1 x i128> %1, %2
@@ -504,15 +734,23 @@ define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: umulh_v2i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT:    umulh z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    ret
+define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
+; SVE-LABEL: umulh_v2i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE-NEXT:    umulh z0.d, p0/m, z0.d, z1.d
+; SVE-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v2i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    // kill: def $q0 killed $q0 def $z0
+; SVE2-NEXT:    // kill: def $q1 killed $q1 def $z1
+; SVE2-NEXT:    umulh z0.d, z0.d, z1.d
+; SVE2-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; SVE2-NEXT:    ret
   %1 = zext <2 x i64> %op1 to <2 x i128>
   %2 = zext <2 x i64> %op2 to <2 x i128>
   %mul = mul <2 x i128> %1, %2
@@ -521,16 +759,25 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @umulh_v4i64(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: umulh_v4i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q2, q3, [x1]
-; CHECK-NEXT:    umulh z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    umulh z1.d, p0/m, z1.d, z3.d
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+define void @umulh_v4i64(ptr %a, ptr %b) {
+; SVE-LABEL: umulh_v4i64:
+; SVE:       // %bb.0:
+; SVE-NEXT:    ldp q0, q1, [x0]
+; SVE-NEXT:    ptrue p0.d, vl2
+; SVE-NEXT:    ldp q2, q3, [x1]
+; SVE-NEXT:    umulh z0.d, p0/m, z0.d, z2.d
+; SVE-NEXT:    umulh z1.d, p0/m, z1.d, z3.d
+; SVE-NEXT:    stp q0, q1, [x0]
+; SVE-NEXT:    ret
+;
+; SVE2-LABEL: umulh_v4i64:
+; SVE2:       // %bb.0:
+; SVE2-NEXT:    ldp q0, q1, [x0]
+; SVE2-NEXT:    ldp q2, q3, [x1]
+; SVE2-NEXT:    umulh z0.d, z0.d, z2.d
+; SVE2-NEXT:    umulh z1.d, z1.d, z3.d
+; SVE2-NEXT:    stp q0, q1, [x0]
+; SVE2-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %op2 = load <4 x i64>, ptr %b
   %1 = zext <4 x i64> %op1 to <4 x i128>
@@ -541,5 +788,5 @@ define void @umulh_v4i64(ptr %a, ptr %b) #0 {
   store <4 x i64> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
index 3980db7b5305b..b8570865846ad 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; UADDV
 ;
 
-define i8 @uaddv_v8i8(<8 x i8> %a) #0 {
+define i8 @uaddv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: uaddv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -20,7 +20,7 @@ define i8 @uaddv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @uaddv_v16i8(<16 x i8> %a) #0 {
+define i8 @uaddv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: uaddv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -33,7 +33,7 @@ define i8 @uaddv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @uaddv_v32i8(ptr %a) #0 {
+define i8 @uaddv_v32i8(ptr %a) {
 ; CHECK-LABEL: uaddv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -48,7 +48,7 @@ define i8 @uaddv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @uaddv_v4i16(<4 x i16> %a) #0 {
+define i16 @uaddv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: uaddv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -61,7 +61,7 @@ define i16 @uaddv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @uaddv_v8i16(<8 x i16> %a) #0 {
+define i16 @uaddv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: uaddv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -74,7 +74,7 @@ define i16 @uaddv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @uaddv_v16i16(ptr %a) #0 {
+define i16 @uaddv_v16i16(ptr %a) {
 ; CHECK-LABEL: uaddv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -89,7 +89,7 @@ define i16 @uaddv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @uaddv_v2i32(<2 x i32> %a) #0 {
+define i32 @uaddv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: uaddv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -102,7 +102,7 @@ define i32 @uaddv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @uaddv_v4i32(<4 x i32> %a) #0 {
+define i32 @uaddv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: uaddv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -115,7 +115,7 @@ define i32 @uaddv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @uaddv_v8i32(ptr %a) #0 {
+define i32 @uaddv_v8i32(ptr %a) {
 ; CHECK-LABEL: uaddv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -130,7 +130,7 @@ define i32 @uaddv_v8i32(ptr %a) #0 {
   ret i32 %res
 }
 
-define i64 @uaddv_v2i64(<2 x i64> %a) #0 {
+define i64 @uaddv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: uaddv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -142,7 +142,7 @@ define i64 @uaddv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @uaddv_v4i64(ptr %a) #0 {
+define i64 @uaddv_v4i64(ptr %a) {
 ; CHECK-LABEL: uaddv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -160,7 +160,7 @@ define i64 @uaddv_v4i64(ptr %a) #0 {
 ; SMAXV
 ;
 
-define i8 @smaxv_v8i8(<8 x i8> %a) #0 {
+define i8 @smaxv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: smaxv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -172,7 +172,7 @@ define i8 @smaxv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @smaxv_v16i8(<16 x i8> %a) #0 {
+define i8 @smaxv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: smaxv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -184,7 +184,7 @@ define i8 @smaxv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @smaxv_v32i8(ptr %a) #0 {
+define i8 @smaxv_v32i8(ptr %a) {
 ; CHECK-LABEL: smaxv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -198,7 +198,7 @@ define i8 @smaxv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @smaxv_v4i16(<4 x i16> %a) #0 {
+define i16 @smaxv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: smaxv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -210,7 +210,7 @@ define i16 @smaxv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @smaxv_v8i16(<8 x i16> %a) #0 {
+define i16 @smaxv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: smaxv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -222,7 +222,7 @@ define i16 @smaxv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @smaxv_v16i16(ptr %a) #0 {
+define i16 @smaxv_v16i16(ptr %a) {
 ; CHECK-LABEL: smaxv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -236,7 +236,7 @@ define i16 @smaxv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @smaxv_v2i32(<2 x i32> %a) #0 {
+define i32 @smaxv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: smaxv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -248,7 +248,7 @@ define i32 @smaxv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @smaxv_v4i32(<4 x i32> %a) #0 {
+define i32 @smaxv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: smaxv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -260,7 +260,7 @@ define i32 @smaxv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @smaxv_v8i32(ptr %a) #0 {
+define i32 @smaxv_v8i32(ptr %a) {
 ; CHECK-LABEL: smaxv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -275,7 +275,7 @@ define i32 @smaxv_v8i32(ptr %a) #0 {
 }
 
 ; No NEON 64-bit vector SMAXV support. Use SVE.
-define i64 @smaxv_v2i64(<2 x i64> %a) #0 {
+define i64 @smaxv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: smaxv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -287,7 +287,7 @@ define i64 @smaxv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @smaxv_v4i64(ptr %a) #0 {
+define i64 @smaxv_v4i64(ptr %a) {
 ; CHECK-LABEL: smaxv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -305,7 +305,7 @@ define i64 @smaxv_v4i64(ptr %a) #0 {
 ; SMINV
 ;
 
-define i8 @sminv_v8i8(<8 x i8> %a) #0 {
+define i8 @sminv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: sminv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -317,7 +317,7 @@ define i8 @sminv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @sminv_v16i8(<16 x i8> %a) #0 {
+define i8 @sminv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: sminv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -329,7 +329,7 @@ define i8 @sminv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @sminv_v32i8(ptr %a) #0 {
+define i8 @sminv_v32i8(ptr %a) {
 ; CHECK-LABEL: sminv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -343,7 +343,7 @@ define i8 @sminv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @sminv_v4i16(<4 x i16> %a) #0 {
+define i16 @sminv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: sminv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -355,7 +355,7 @@ define i16 @sminv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @sminv_v8i16(<8 x i16> %a) #0 {
+define i16 @sminv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: sminv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -367,7 +367,7 @@ define i16 @sminv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @sminv_v16i16(ptr %a) #0 {
+define i16 @sminv_v16i16(ptr %a) {
 ; CHECK-LABEL: sminv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -381,7 +381,7 @@ define i16 @sminv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @sminv_v2i32(<2 x i32> %a) #0 {
+define i32 @sminv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: sminv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -393,7 +393,7 @@ define i32 @sminv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @sminv_v4i32(<4 x i32> %a) #0 {
+define i32 @sminv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: sminv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -405,7 +405,7 @@ define i32 @sminv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @sminv_v8i32(ptr %a) #0 {
+define i32 @sminv_v8i32(ptr %a) {
 ; CHECK-LABEL: sminv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -420,7 +420,7 @@ define i32 @sminv_v8i32(ptr %a) #0 {
 }
 
 ; No NEON 64-bit vector SMINV support. Use SVE.
-define i64 @sminv_v2i64(<2 x i64> %a) #0 {
+define i64 @sminv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: sminv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -432,7 +432,7 @@ define i64 @sminv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @sminv_v4i64(ptr %a) #0 {
+define i64 @sminv_v4i64(ptr %a) {
 ; CHECK-LABEL: sminv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -450,7 +450,7 @@ define i64 @sminv_v4i64(ptr %a) #0 {
 ; UMAXV
 ;
 
-define i8 @umaxv_v8i8(<8 x i8> %a) #0 {
+define i8 @umaxv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: umaxv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -462,7 +462,7 @@ define i8 @umaxv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @umaxv_v16i8(<16 x i8> %a) #0 {
+define i8 @umaxv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: umaxv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -474,7 +474,7 @@ define i8 @umaxv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @umaxv_v32i8(ptr %a) #0 {
+define i8 @umaxv_v32i8(ptr %a) {
 ; CHECK-LABEL: umaxv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -488,7 +488,7 @@ define i8 @umaxv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @umaxv_v4i16(<4 x i16> %a) #0 {
+define i16 @umaxv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: umaxv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -500,7 +500,7 @@ define i16 @umaxv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @umaxv_v8i16(<8 x i16> %a) #0 {
+define i16 @umaxv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: umaxv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -512,7 +512,7 @@ define i16 @umaxv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @umaxv_v16i16(ptr %a) #0 {
+define i16 @umaxv_v16i16(ptr %a) {
 ; CHECK-LABEL: umaxv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -526,7 +526,7 @@ define i16 @umaxv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @umaxv_v2i32(<2 x i32> %a) #0 {
+define i32 @umaxv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: umaxv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -538,7 +538,7 @@ define i32 @umaxv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @umaxv_v4i32(<4 x i32> %a) #0 {
+define i32 @umaxv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: umaxv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -550,7 +550,7 @@ define i32 @umaxv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @umaxv_v8i32(ptr %a) #0 {
+define i32 @umaxv_v8i32(ptr %a) {
 ; CHECK-LABEL: umaxv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -565,7 +565,7 @@ define i32 @umaxv_v8i32(ptr %a) #0 {
 }
 
 ; No NEON 64-bit vector UMAXV support. Use SVE.
-define i64 @umaxv_v2i64(<2 x i64> %a) #0 {
+define i64 @umaxv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: umaxv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -577,7 +577,7 @@ define i64 @umaxv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @umaxv_v4i64(ptr %a) #0 {
+define i64 @umaxv_v4i64(ptr %a) {
 ; CHECK-LABEL: umaxv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -595,7 +595,7 @@ define i64 @umaxv_v4i64(ptr %a) #0 {
 ; UMINV
 ;
 
-define i8 @uminv_v8i8(<8 x i8> %a) #0 {
+define i8 @uminv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: uminv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -607,7 +607,7 @@ define i8 @uminv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @uminv_v16i8(<16 x i8> %a) #0 {
+define i8 @uminv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: uminv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -619,7 +619,7 @@ define i8 @uminv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @uminv_v32i8(ptr %a) #0 {
+define i8 @uminv_v32i8(ptr %a) {
 ; CHECK-LABEL: uminv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -633,7 +633,7 @@ define i8 @uminv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @uminv_v4i16(<4 x i16> %a) #0 {
+define i16 @uminv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: uminv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -645,7 +645,7 @@ define i16 @uminv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @uminv_v8i16(<8 x i16> %a) #0 {
+define i16 @uminv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: uminv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -657,7 +657,7 @@ define i16 @uminv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @uminv_v16i16(ptr %a) #0 {
+define i16 @uminv_v16i16(ptr %a) {
 ; CHECK-LABEL: uminv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -671,7 +671,7 @@ define i16 @uminv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @uminv_v2i32(<2 x i32> %a) #0 {
+define i32 @uminv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: uminv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -683,7 +683,7 @@ define i32 @uminv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @uminv_v4i32(<4 x i32> %a) #0 {
+define i32 @uminv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: uminv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -695,7 +695,7 @@ define i32 @uminv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @uminv_v8i32(ptr %a) #0 {
+define i32 @uminv_v8i32(ptr %a) {
 ; CHECK-LABEL: uminv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -710,7 +710,7 @@ define i32 @uminv_v8i32(ptr %a) #0 {
 }
 
 ; No NEON 64-bit vector UMINV support. Use SVE.
-define i64 @uminv_v2i64(<2 x i64> %a) #0 {
+define i64 @uminv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: uminv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -722,7 +722,7 @@ define i64 @uminv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @uminv_v4i64(ptr %a) #0 {
+define i64 @uminv_v4i64(ptr %a) {
 ; CHECK-LABEL: uminv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -736,8 +736,6 @@ define i64 @uminv_v4i64(ptr %a) #0 {
   ret i64 %res
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
 declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
index 31c0a24c166d3..436e360d3cf73 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; SREM
 ;
 
-define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: srem_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -27,7 +27,7 @@ define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: srem_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -56,7 +56,7 @@ define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: srem_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -106,7 +106,7 @@ define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @srem_v32i8(ptr %a, ptr %b) #0 {
+define void @srem_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: srem_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q0, [x0]
@@ -192,7 +192,7 @@ define void @srem_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: srem_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -210,7 +210,7 @@ define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: srem_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -238,7 +238,7 @@ define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @srem_v16i16(ptr %a, ptr %b) #0 {
+define void @srem_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: srem_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q0, [x0]
@@ -284,7 +284,7 @@ define void @srem_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: srem_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -299,7 +299,7 @@ define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: srem_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -314,7 +314,7 @@ define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @srem_v8i32(ptr %a, ptr %b) #0 {
+define void @srem_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: srem_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -335,7 +335,7 @@ define void @srem_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: srem_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -350,7 +350,7 @@ define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: srem_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -365,7 +365,7 @@ define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @srem_v4i64(ptr %a, ptr %b) #0 {
+define void @srem_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: srem_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -390,7 +390,7 @@ define void @srem_v4i64(ptr %a, ptr %b) #0 {
 ; UREM
 ;
 
-define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: urem_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -410,7 +410,7 @@ define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: urem_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -439,7 +439,7 @@ define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: urem_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -489,7 +489,7 @@ define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @urem_v32i8(ptr %a, ptr %b) #0 {
+define void @urem_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: urem_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q0, [x0]
@@ -575,7 +575,7 @@ define void @urem_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: urem_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -593,7 +593,7 @@ define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: urem_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
@@ -621,7 +621,7 @@ define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @urem_v16i16(ptr %a, ptr %b) #0 {
+define void @urem_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: urem_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q0, [x0]
@@ -667,7 +667,7 @@ define void @urem_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: urem_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -682,7 +682,7 @@ define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: urem_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -697,7 +697,7 @@ define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @urem_v8i32(ptr %a, ptr %b) #0 {
+define void @urem_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: urem_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -718,7 +718,7 @@ define void @urem_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: urem_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -733,7 +733,7 @@ define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: urem_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -748,7 +748,7 @@ define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @urem_v4i64(ptr %a, ptr %b) #0 {
+define void @urem_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: urem_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -768,5 +768,3 @@ define void @urem_v4i64(ptr %a, ptr %b) #0 {
   store <4 x i64> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
index b0f9a7c1f4763..5654fe938ddb6 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 {
+define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -19,7 +19,7 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 {
   ret <4 x i8> %sel
 }
 
-define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 {
+define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -35,7 +35,7 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 {
   ret <8 x i8> %sel
 }
 
-define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 {
+define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -51,7 +51,7 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 {
   ret <16 x i8> %sel
 }
 
-define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v32i8(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w2, #0x1
@@ -73,7 +73,7 @@ define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 {
   ret void
 }
 
-define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 {
+define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -89,7 +89,7 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 {
   ret <2 x i16> %sel
 }
 
-define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 {
+define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -105,7 +105,7 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 {
   ret <4 x i16> %sel
 }
 
-define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 {
+define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -121,7 +121,7 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 {
   ret <8 x i16> %sel
 }
 
-define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v16i16(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w2, #0x1
@@ -143,7 +143,7 @@ define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 {
   ret void
 }
 
-define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 {
+define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -159,7 +159,7 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 {
   ret <2 x i32> %sel
 }
 
-define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 {
+define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0x1
@@ -175,7 +175,7 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 {
   ret <4 x i32> %sel
 }
 
-define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v8i32(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w2, #0x1
@@ -197,7 +197,7 @@ define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 {
   ret void
 }
 
-define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 {
+define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
@@ -214,7 +214,7 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 {
   ret <1 x i64> %sel
 }
 
-define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 {
+define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) {
 ; CHECK-LABEL: select_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
@@ -231,7 +231,7 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 {
   ret <2 x i64> %sel
 }
 
-define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 {
+define void @select_v4i64(ptr %a, ptr %b, i1 %mask) {
 ; CHECK-LABEL: select_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
@@ -253,5 +253,3 @@ define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 {
   store <4 x i64> %sel, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
index 2f9e395209488..e6e0a07cbf33b 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; ASHR
 ;
 
-define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: ashr_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -22,7 +22,7 @@ define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: ashr_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -35,7 +35,7 @@ define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: ashr_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -48,7 +48,7 @@ define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @ashr_v32i8(ptr %a, ptr %b) #0 {
+define void @ashr_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: ashr_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -65,7 +65,7 @@ define void @ashr_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: ashr_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -80,7 +80,7 @@ define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: ashr_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -93,7 +93,7 @@ define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: ashr_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -106,7 +106,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @ashr_v16i16(ptr %a, ptr %b) #0 {
+define void @ashr_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: ashr_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -123,7 +123,7 @@ define void @ashr_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: ashr_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -136,7 +136,7 @@ define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: ashr_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -149,7 +149,7 @@ define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @ashr_v8i32(ptr %a, ptr %b) #0 {
+define void @ashr_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: ashr_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -166,7 +166,7 @@ define void @ashr_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: ashr_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -179,7 +179,7 @@ define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: ashr_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -192,7 +192,7 @@ define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @ashr_v4i64(ptr %a, ptr %b) #0 {
+define void @ashr_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ashr_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -213,7 +213,7 @@ define void @ashr_v4i64(ptr %a, ptr %b) #0 {
 ; LSHR
 ;
 
-define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: lshr_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -228,7 +228,7 @@ define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: lshr_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -241,7 +241,7 @@ define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: lshr_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -254,7 +254,7 @@ define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @lshr_v32i8(ptr %a, ptr %b) #0 {
+define void @lshr_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: lshr_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -271,7 +271,7 @@ define void @lshr_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: lshr_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -286,7 +286,7 @@ define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: lshr_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -299,7 +299,7 @@ define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: lshr_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -312,7 +312,7 @@ define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @lshr_v16i16(ptr %a, ptr %b) #0 {
+define void @lshr_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: lshr_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -329,7 +329,7 @@ define void @lshr_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: lshr_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -342,7 +342,7 @@ define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: lshr_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -355,7 +355,7 @@ define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @lshr_v8i32(ptr %a, ptr %b) #0 {
+define void @lshr_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: lshr_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -372,7 +372,7 @@ define void @lshr_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: lshr_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -385,7 +385,7 @@ define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: lshr_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -398,7 +398,7 @@ define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @lshr_v4i64(ptr %a, ptr %b) #0 {
+define void @lshr_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: lshr_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -419,7 +419,7 @@ define void @lshr_v4i64(ptr %a, ptr %b) #0 {
 ; SHL
 ;
 
-define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) #0 {
+define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) {
 ; CHECK-LABEL: shl_v2i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -433,7 +433,7 @@ define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) #0 {
   ret <2 x i8> %res
 }
 
-define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: shl_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
@@ -447,7 +447,7 @@ define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: shl_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -460,7 +460,7 @@ define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: shl_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -473,7 +473,7 @@ define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %res
 }
 
-define void @shl_v32i8(ptr %a, ptr %b) #0 {
+define void @shl_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: shl_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -490,7 +490,7 @@ define void @shl_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: shl_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -503,7 +503,7 @@ define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: shl_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -516,7 +516,7 @@ define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %res
 }
 
-define void @shl_v16i16(ptr %a, ptr %b) #0 {
+define void @shl_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: shl_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -533,7 +533,7 @@ define void @shl_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: shl_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -546,7 +546,7 @@ define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: shl_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -559,7 +559,7 @@ define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %res
 }
 
-define void @shl_v8i32(ptr %a, ptr %b) #0 {
+define void @shl_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: shl_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -576,7 +576,7 @@ define void @shl_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
 ; CHECK-LABEL: shl_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -589,7 +589,7 @@ define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: shl_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -602,7 +602,7 @@ define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %res
 }
 
-define void @shl_v4i64(ptr %a, ptr %b) #0 {
+define void @shl_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: shl_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -618,5 +618,3 @@ define void @shl_v4i64(ptr %a, ptr %b) #0 {
   store <4 x i64> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
index b60150a707f22..0bd767cd43655 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; UCVTF H -> H
 ;
 
-define <4 x half> @ucvtf_v4i16_v4f16(<4 x i16> %op1) #0 {
+define <4 x half> @ucvtf_v4i16_v4f16(<4 x i16> %op1) {
 ; CHECK-LABEL: ucvtf_v4i16_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -19,7 +19,7 @@ define <4 x half> @ucvtf_v4i16_v4f16(<4 x i16> %op1) #0 {
   ret <4 x half> %res
 }
 
-define void @ucvtf_v8i16_v8f16(ptr %a, ptr %b) #0 {
+define void @ucvtf_v8i16_v8f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v8i16_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -33,7 +33,7 @@ define void @ucvtf_v8i16_v8f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @ucvtf_v16i16_v16f16(ptr %a, ptr %b) #0 {
+define void @ucvtf_v16i16_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v16i16_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -52,7 +52,7 @@ define void @ucvtf_v16i16_v16f16(ptr %a, ptr %b) #0 {
 ; UCVTF H -> S
 ;
 
-define <2 x float> @ucvtf_v2i16_v2f32(<2 x i16> %op1) #0 {
+define <2 x float> @ucvtf_v2i16_v2f32(<2 x i16> %op1) {
 ; CHECK-LABEL: ucvtf_v2i16_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -65,7 +65,7 @@ define <2 x float> @ucvtf_v2i16_v2f32(<2 x i16> %op1) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) #0 {
+define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) {
 ; CHECK-LABEL: ucvtf_v4i16_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -78,7 +78,7 @@ define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) #0 {
   ret <4 x float> %res
 }
 
-define void @ucvtf_v8i16_v8f32(ptr %a, ptr %b) #0 {
+define void @ucvtf_v8i16_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v8i16_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -96,7 +96,7 @@ define void @ucvtf_v8i16_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @ucvtf_v16i16_v16f32(ptr %a, ptr %b) #0 {
+define void @ucvtf_v16i16_v16f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v16i16_v16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -125,7 +125,7 @@ define void @ucvtf_v16i16_v16f32(ptr %a, ptr %b) #0 {
 ; UCVTF H -> D
 ;
 
-define <1 x double> @ucvtf_v1i16_v1f64(<1 x i16> %op1) #0 {
+define <1 x double> @ucvtf_v1i16_v1f64(<1 x i16> %op1) {
 ; CHECK-LABEL: ucvtf_v1i16_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -137,7 +137,7 @@ define <1 x double> @ucvtf_v1i16_v1f64(<1 x i16> %op1) #0 {
   ret <1 x double> %res
 }
 
-define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) #0 {
+define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) {
 ; CHECK-LABEL: ucvtf_v2i16_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -151,7 +151,7 @@ define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) #0 {
   ret <2 x double> %res
 }
 
-define void @ucvtf_v4i16_v4f64(ptr %a, ptr %b) #0 {
+define void @ucvtf_v4i16_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v4i16_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -170,7 +170,7 @@ define void @ucvtf_v4i16_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {
+define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v8i16_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -198,7 +198,7 @@ define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) #0 {
+define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v16i16_v16f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -248,7 +248,7 @@ define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) #0 {
 ; UCVTF S -> H
 ;
 
-define <2 x half> @ucvtf_v2i32_v2f16(<2 x i32> %op1) #0 {
+define <2 x half> @ucvtf_v2i32_v2f16(<2 x i32> %op1) {
 ; CHECK-LABEL: ucvtf_v2i32_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -261,7 +261,7 @@ define <2 x half> @ucvtf_v2i32_v2f16(<2 x i32> %op1) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @ucvtf_v4i32_v4f16(<4 x i32> %op1) #0 {
+define <4 x half> @ucvtf_v4i32_v4f16(<4 x i32> %op1) {
 ; CHECK-LABEL: ucvtf_v4i32_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -274,7 +274,7 @@ define <4 x half> @ucvtf_v4i32_v4f16(<4 x i32> %op1) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @ucvtf_v8i32_v8f16(ptr %a) #0 {
+define <8 x half> @ucvtf_v8i32_v8f16(ptr %a) {
 ; CHECK-LABEL: ucvtf_v8i32_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -292,7 +292,7 @@ define <8 x half> @ucvtf_v8i32_v8f16(ptr %a) #0 {
   ret <8 x half> %res
 }
 
-define void @ucvtf_v16i32_v16f16(ptr %a, ptr %b) #0 {
+define void @ucvtf_v16i32_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v16i32_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -321,7 +321,7 @@ define void @ucvtf_v16i32_v16f16(ptr %a, ptr %b) #0 {
 ; UCVTF S -> S
 ;
 
-define <2 x float> @ucvtf_v2i32_v2f32(<2 x i32> %op1) #0 {
+define <2 x float> @ucvtf_v2i32_v2f32(<2 x i32> %op1) {
 ; CHECK-LABEL: ucvtf_v2i32_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -333,7 +333,7 @@ define <2 x float> @ucvtf_v2i32_v2f32(<2 x i32> %op1) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @ucvtf_v4i32_v4f32(<4 x i32> %op1) #0 {
+define <4 x float> @ucvtf_v4i32_v4f32(<4 x i32> %op1) {
 ; CHECK-LABEL: ucvtf_v4i32_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -345,7 +345,7 @@ define <4 x float> @ucvtf_v4i32_v4f32(<4 x i32> %op1) #0 {
   ret <4 x float> %res
 }
 
-define void @ucvtf_v8i32_v8f32(ptr %a, ptr %b) #0 {
+define void @ucvtf_v8i32_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v8i32_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -364,7 +364,7 @@ define void @ucvtf_v8i32_v8f32(ptr %a, ptr %b) #0 {
 ; UCVTF S -> D
 ;
 
-define <2 x double> @ucvtf_v2i32_v2f64(<2 x i32> %op1) #0 {
+define <2 x double> @ucvtf_v2i32_v2f64(<2 x i32> %op1) {
 ; CHECK-LABEL: ucvtf_v2i32_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -377,7 +377,7 @@ define <2 x double> @ucvtf_v2i32_v2f64(<2 x i32> %op1) #0 {
   ret <2 x double> %res
 }
 
-define void @ucvtf_v4i32_v4f64(ptr %a, ptr %b) #0 {
+define void @ucvtf_v4i32_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v4i32_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -395,7 +395,7 @@ define void @ucvtf_v4i32_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @ucvtf_v8i32_v8f64(ptr %a, ptr %b) #0 {
+define void @ucvtf_v8i32_v8f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v8i32_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -424,7 +424,7 @@ define void @ucvtf_v8i32_v8f64(ptr %a, ptr %b) #0 {
 ; UCVTF D -> H
 ;
 
-define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) #0 {
+define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) {
 ; CHECK-LABEL: ucvtf_v2i64_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -444,7 +444,7 @@ define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @ucvtf_v4i64_v4f16(ptr %a) #0 {
+define <4 x half> @ucvtf_v4i64_v4f16(ptr %a) {
 ; CHECK-LABEL: ucvtf_v4i64_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -466,7 +466,7 @@ define <4 x half> @ucvtf_v4i64_v4f16(ptr %a) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @ucvtf_v8i64_v8f16(ptr %a) #0 {
+define <8 x half> @ucvtf_v8i64_v8f16(ptr %a) {
 ; CHECK-LABEL: ucvtf_v8i64_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -502,7 +502,7 @@ define <8 x half> @ucvtf_v8i64_v8f16(ptr %a) #0 {
 ; UCVTF D -> S
 ;
 
-define <2 x float> @ucvtf_v2i64_v2f32(<2 x i64> %op1) #0 {
+define <2 x float> @ucvtf_v2i64_v2f32(<2 x i64> %op1) {
 ; CHECK-LABEL: ucvtf_v2i64_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -515,7 +515,7 @@ define <2 x float> @ucvtf_v2i64_v2f32(<2 x i64> %op1) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @ucvtf_v4i64_v4f32(ptr %a) #0 {
+define <4 x float> @ucvtf_v4i64_v4f32(ptr %a) {
 ; CHECK-LABEL: ucvtf_v4i64_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -533,7 +533,7 @@ define <4 x float> @ucvtf_v4i64_v4f32(ptr %a) #0 {
   ret <4 x float> %res
 }
 
-define void @ucvtf_v8i64_v8f32(ptr %a, ptr %b) #0 {
+define void @ucvtf_v8i64_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v8i64_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -562,7 +562,7 @@ define void @ucvtf_v8i64_v8f32(ptr %a, ptr %b) #0 {
 ; UCVTF D -> D
 ;
 
-define <2 x double> @ucvtf_v2i64_v2f64(<2 x i64> %op1) #0 {
+define <2 x double> @ucvtf_v2i64_v2f64(<2 x i64> %op1) {
 ; CHECK-LABEL: ucvtf_v2i64_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -574,7 +574,7 @@ define <2 x double> @ucvtf_v2i64_v2f64(<2 x i64> %op1) #0 {
   ret <2 x double> %res
 }
 
-define void @ucvtf_v4i64_v4f64(ptr %a, ptr %b) #0 {
+define void @ucvtf_v4i64_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: ucvtf_v4i64_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -593,7 +593,7 @@ define void @ucvtf_v4i64_v4f64(ptr %a, ptr %b) #0 {
 ; SCVTF H -> H
 ;
 
-define <4 x half> @scvtf_v4i16_v4f16(<4 x i16> %op1) #0 {
+define <4 x half> @scvtf_v4i16_v4f16(<4 x i16> %op1) {
 ; CHECK-LABEL: scvtf_v4i16_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -605,7 +605,7 @@ define <4 x half> @scvtf_v4i16_v4f16(<4 x i16> %op1) #0 {
   ret <4 x half> %res
 }
 
-define void @scvtf_v8i16_v8f16(ptr %a, ptr %b) #0 {
+define void @scvtf_v8i16_v8f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v8i16_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -619,7 +619,7 @@ define void @scvtf_v8i16_v8f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @scvtf_v16i16_v16f16(ptr %a, ptr %b) #0 {
+define void @scvtf_v16i16_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v16i16_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -637,7 +637,7 @@ define void @scvtf_v16i16_v16f16(ptr %a, ptr %b) #0 {
 ; SCVTF H -> S
 ;
 
-define <2 x float> @scvtf_v2i16_v2f32(<2 x i16> %op1) #0 {
+define <2 x float> @scvtf_v2i16_v2f32(<2 x i16> %op1) {
 ; CHECK-LABEL: scvtf_v2i16_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -650,7 +650,7 @@ define <2 x float> @scvtf_v2i16_v2f32(<2 x i16> %op1) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) #0 {
+define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) {
 ; CHECK-LABEL: scvtf_v4i16_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -663,7 +663,7 @@ define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) #0 {
   ret <4 x float> %res
 }
 
-define void @scvtf_v8i16_v8f32(ptr %a, ptr %b) #0 {
+define void @scvtf_v8i16_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v8i16_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -681,7 +681,7 @@ define void @scvtf_v8i16_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @scvtf_v16i16_v16f32(ptr %a, ptr %b) #0 {
+define void @scvtf_v16i16_v16f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v16i16_v16f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -710,7 +710,7 @@ define void @scvtf_v16i16_v16f32(ptr %a, ptr %b) #0 {
 ; SCVTF H -> D
 ;
 
-define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) #0 {
+define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) {
 ; CHECK-LABEL: scvtf_v2i16_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -725,7 +725,7 @@ define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) #0 {
   ret <2 x double> %res
 }
 
-define void @scvtf_v4i16_v4f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v4i16_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v4i16_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -744,7 +744,7 @@ define void @scvtf_v4i16_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v8i16_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -772,7 +772,7 @@ define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v16i16_v16f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -822,7 +822,7 @@ define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) #0 {
 ; SCVTF S -> H
 ;
 
-define <2 x half> @scvtf_v2i32_v2f16(<2 x i32> %op1) #0 {
+define <2 x half> @scvtf_v2i32_v2f16(<2 x i32> %op1) {
 ; CHECK-LABEL: scvtf_v2i32_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -835,7 +835,7 @@ define <2 x half> @scvtf_v2i32_v2f16(<2 x i32> %op1) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @scvtf_v4i32_v4f16(<4 x i32> %op1) #0 {
+define <4 x half> @scvtf_v4i32_v4f16(<4 x i32> %op1) {
 ; CHECK-LABEL: scvtf_v4i32_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -848,7 +848,7 @@ define <4 x half> @scvtf_v4i32_v4f16(<4 x i32> %op1) #0 {
   ret <4 x half> %res
 }
 
-define <8 x half> @scvtf_v8i32_v8f16(ptr %a) #0 {
+define <8 x half> @scvtf_v8i32_v8f16(ptr %a) {
 ; CHECK-LABEL: scvtf_v8i32_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -870,7 +870,7 @@ define <8 x half> @scvtf_v8i32_v8f16(ptr %a) #0 {
 ; SCVTF S -> S
 ;
 
-define <2 x float> @scvtf_v2i32_v2f32(<2 x i32> %op1) #0 {
+define <2 x float> @scvtf_v2i32_v2f32(<2 x i32> %op1) {
 ; CHECK-LABEL: scvtf_v2i32_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -882,7 +882,7 @@ define <2 x float> @scvtf_v2i32_v2f32(<2 x i32> %op1) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @scvtf_v4i32_v4f32(<4 x i32> %op1) #0 {
+define <4 x float> @scvtf_v4i32_v4f32(<4 x i32> %op1) {
 ; CHECK-LABEL: scvtf_v4i32_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -894,7 +894,7 @@ define <4 x float> @scvtf_v4i32_v4f32(<4 x i32> %op1) #0 {
   ret <4 x float> %res
 }
 
-define void @scvtf_v8i32_v8f32(ptr %a, ptr %b) #0 {
+define void @scvtf_v8i32_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v8i32_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -913,7 +913,7 @@ define void @scvtf_v8i32_v8f32(ptr %a, ptr %b) #0 {
 ; SCVTF S -> D
 ;
 
-define <2 x double> @scvtf_v2i32_v2f64(<2 x i32> %op1) #0 {
+define <2 x double> @scvtf_v2i32_v2f64(<2 x i32> %op1) {
 ; CHECK-LABEL: scvtf_v2i32_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -926,7 +926,7 @@ define <2 x double> @scvtf_v2i32_v2f64(<2 x i32> %op1) #0 {
   ret <2 x double> %res
 }
 
-define void @scvtf_v4i32_v4f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v4i32_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v4i32_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -944,7 +944,7 @@ define void @scvtf_v4i32_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @scvtf_v8i32_v8f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v8i32_v8f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v8i32_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -969,7 +969,7 @@ define void @scvtf_v8i32_v8f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @scvtf_v16i32_v16f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v16i32_v16f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v16i32_v16f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q2, q3, [x0, #32]
@@ -1015,7 +1015,7 @@ define void @scvtf_v16i32_v16f64(ptr %a, ptr %b) #0 {
 ; SCVTF D -> H
 ;
 
-define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) #0 {
+define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) {
 ; CHECK-LABEL: scvtf_v2i64_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -1035,7 +1035,7 @@ define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) #0 {
   ret <2 x half> %res
 }
 
-define <4 x half> @scvtf_v4i64_v4f16(ptr %a) #0 {
+define <4 x half> @scvtf_v4i64_v4f16(ptr %a) {
 ; CHECK-LABEL: scvtf_v4i64_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -1061,7 +1061,7 @@ define <4 x half> @scvtf_v4i64_v4f16(ptr %a) #0 {
 ; SCVTF D -> S
 ;
 
-define <2 x float> @scvtf_v2i64_v2f32(<2 x i64> %op1) #0 {
+define <2 x float> @scvtf_v2i64_v2f32(<2 x i64> %op1) {
 ; CHECK-LABEL: scvtf_v2i64_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1074,7 +1074,7 @@ define <2 x float> @scvtf_v2i64_v2f32(<2 x i64> %op1) #0 {
   ret <2 x float> %res
 }
 
-define <4 x float> @scvtf_v4i64_v4f32(ptr %a) #0 {
+define <4 x float> @scvtf_v4i64_v4f32(ptr %a) {
 ; CHECK-LABEL: scvtf_v4i64_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -1096,7 +1096,7 @@ define <4 x float> @scvtf_v4i64_v4f32(ptr %a) #0 {
 ; SCVTF D -> D
 ;
 
-define <2 x double> @scvtf_v2i64_v2f64(<2 x i64> %op1) #0 {
+define <2 x double> @scvtf_v2i64_v2f64(<2 x i64> %op1) {
 ; CHECK-LABEL: scvtf_v2i64_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -1108,7 +1108,7 @@ define <2 x double> @scvtf_v2i64_v2f64(<2 x i64> %op1) #0 {
   ret <2 x double> %res
 }
 
-define void @scvtf_v4i64_v4f64(ptr %a, ptr %b) #0 {
+define void @scvtf_v4i64_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: scvtf_v4i64_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1122,5 +1122,3 @@ define void @scvtf_v4i64_v4f64(ptr %a, ptr %b) #0 {
   store <4 x double> %res, ptr %b
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
index 3f6a9b9d8785b..01618021c9391 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 {
+define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) {
 ; CHECK-LABEL: select_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -21,7 +21,7 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 {
   ret <4 x i8> %sel
 }
 
-define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
+define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) {
 ; CHECK-LABEL: select_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -39,7 +39,7 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
   ret <8 x i8> %sel
 }
 
-define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {
+define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) {
 ; CHECK-LABEL: select_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
@@ -57,7 +57,7 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask)
   ret <16 x i8> %sel
 }
 
-define void @select_v32i8(ptr %a, ptr %b) #0 {
+define void @select_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -77,7 +77,7 @@ define void @select_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #0 {
+define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) {
 ; CHECK-LABEL: select_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -95,7 +95,7 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #
   ret <2 x i16> %sel
 }
 
-define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #0 {
+define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) {
 ; CHECK-LABEL: select_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -113,7 +113,7 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #
   ret <4 x i16> %sel
 }
 
-define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {
+define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) {
 ; CHECK-LABEL: select_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -132,7 +132,7 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #
   ret <8 x i16> %sel
 }
 
-define void @select_v16i16(ptr %a, ptr %b) #0 {
+define void @select_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -152,7 +152,7 @@ define void @select_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 {
+define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) {
 ; CHECK-LABEL: select_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -170,7 +170,7 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #
   ret <2 x i32> %sel
 }
 
-define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {
+define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) {
 ; CHECK-LABEL: select_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -189,7 +189,7 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #
   ret <4 x i32> %sel
 }
 
-define void @select_v8i32(ptr %a, ptr %b) #0 {
+define void @select_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -209,7 +209,7 @@ define void @select_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 {
+define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) {
 ; CHECK-LABEL: select_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
@@ -226,7 +226,7 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #
   ret <1 x i64> %sel
 }
 
-define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {
+define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) {
 ; CHECK-LABEL: select_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
@@ -245,7 +245,7 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #
   ret <2 x i64> %sel
 }
 
-define void @select_v4i64(ptr %a, ptr %b) #0 {
+define void @select_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: select_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -264,5 +264,3 @@ define void @select_v4i64(ptr %a, ptr %b) #0 {
   store <4 x i64> %sel, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" uwtable }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
index 60637882f6e68..91b2b59534bb8 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 declare void @def(ptr)
 
-define void @alloc_v4i8(ptr %st_ptr) #0 {
+define void @alloc_v4i8(ptr %st_ptr) nounwind {
 ; CHECK-LABEL: alloc_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #48
@@ -36,7 +36,7 @@ define void @alloc_v4i8(ptr %st_ptr) #0 {
   ret void
 }
 
-define void @alloc_v6i8(ptr %st_ptr) #0 {
+define void @alloc_v6i8(ptr %st_ptr) nounwind {
 ; CHECK-LABEL: alloc_v6i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #48
@@ -78,7 +78,7 @@ define void @alloc_v6i8(ptr %st_ptr) #0 {
   ret void
 }
 
-define void @alloc_v32i8(ptr %st_ptr) #0 {
+define void @alloc_v32i8(ptr %st_ptr) nounwind {
 ; CHECK-LABEL: alloc_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #64
@@ -127,7 +127,7 @@ define void @alloc_v32i8(ptr %st_ptr) #0 {
 }
 
 
-define void @alloc_v8f64(ptr %st_ptr) #0 {
+define void @alloc_v8f64(ptr %st_ptr) nounwind {
 ; CHECK-LABEL: alloc_v8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #96
@@ -153,5 +153,3 @@ define void @alloc_v8f64(ptr %st_ptr) #0 {
   store <4 x double> %strided.vec, ptr %st_ptr
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" nounwind}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
index 943098d817404..a3591dfe527ee 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
index 251f6ea48920c..bd954df190477 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <4 x i8> @load_v4i8(ptr %a) #0 {
+define <4 x i8> @load_v4i8(ptr %a) {
 ; CHECK-LABEL: load_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -14,7 +14,7 @@ define <4 x i8> @load_v4i8(ptr %a) #0 {
   ret <4 x i8> %load
 }
 
-define <8 x i8> @load_v8i8(ptr %a) #0 {
+define <8 x i8> @load_v8i8(ptr %a) {
 ; CHECK-LABEL: load_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -23,7 +23,7 @@ define <8 x i8> @load_v8i8(ptr %a) #0 {
   ret <8 x i8> %load
 }
 
-define <16 x i8> @load_v16i8(ptr %a) #0 {
+define <16 x i8> @load_v16i8(ptr %a) {
 ; CHECK-LABEL: load_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -32,7 +32,7 @@ define <16 x i8> @load_v16i8(ptr %a) #0 {
   ret <16 x i8> %load
 }
 
-define <32 x i8> @load_v32i8(ptr %a) #0 {
+define <32 x i8> @load_v32i8(ptr %a) {
 ; CHECK-LABEL: load_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -41,7 +41,7 @@ define <32 x i8> @load_v32i8(ptr %a) #0 {
   ret <32 x i8> %load
 }
 
-define <2 x i16> @load_v2i16(ptr %a) #0 {
+define <2 x i16> @load_v2i16(ptr %a) {
 ; CHECK-LABEL: load_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -57,7 +57,7 @@ define <2 x i16> @load_v2i16(ptr %a) #0 {
   ret <2 x i16> %load
 }
 
-define <2 x half> @load_v2f16(ptr %a) #0 {
+define <2 x half> @load_v2f16(ptr %a) {
 ; CHECK-LABEL: load_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr s0, [x0]
@@ -66,7 +66,7 @@ define <2 x half> @load_v2f16(ptr %a) #0 {
   ret <2 x half> %load
 }
 
-define <4 x i16> @load_v4i16(ptr %a) #0 {
+define <4 x i16> @load_v4i16(ptr %a) {
 ; CHECK-LABEL: load_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -75,7 +75,7 @@ define <4 x i16> @load_v4i16(ptr %a) #0 {
   ret <4 x i16> %load
 }
 
-define <4 x half> @load_v4f16(ptr %a) #0 {
+define <4 x half> @load_v4f16(ptr %a) {
 ; CHECK-LABEL: load_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -84,7 +84,7 @@ define <4 x half> @load_v4f16(ptr %a) #0 {
   ret <4 x half> %load
 }
 
-define <8 x i16> @load_v8i16(ptr %a) #0 {
+define <8 x i16> @load_v8i16(ptr %a) {
 ; CHECK-LABEL: load_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -93,7 +93,7 @@ define <8 x i16> @load_v8i16(ptr %a) #0 {
   ret <8 x i16> %load
 }
 
-define <8 x half> @load_v8f16(ptr %a) #0 {
+define <8 x half> @load_v8f16(ptr %a) {
 ; CHECK-LABEL: load_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -102,7 +102,7 @@ define <8 x half> @load_v8f16(ptr %a) #0 {
   ret <8 x half> %load
 }
 
-define <16 x i16> @load_v16i16(ptr %a) #0 {
+define <16 x i16> @load_v16i16(ptr %a) {
 ; CHECK-LABEL: load_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -111,7 +111,7 @@ define <16 x i16> @load_v16i16(ptr %a) #0 {
   ret <16 x i16> %load
 }
 
-define <16 x half> @load_v16f16(ptr %a) #0 {
+define <16 x half> @load_v16f16(ptr %a) {
 ; CHECK-LABEL: load_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -120,7 +120,7 @@ define <16 x half> @load_v16f16(ptr %a) #0 {
   ret <16 x half> %load
 }
 
-define <2 x i32> @load_v2i32(ptr %a) #0 {
+define <2 x i32> @load_v2i32(ptr %a) {
 ; CHECK-LABEL: load_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -129,7 +129,7 @@ define <2 x i32> @load_v2i32(ptr %a) #0 {
   ret <2 x i32> %load
 }
 
-define <2 x float> @load_v2f32(ptr %a) #0 {
+define <2 x float> @load_v2f32(ptr %a) {
 ; CHECK-LABEL: load_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -138,7 +138,7 @@ define <2 x float> @load_v2f32(ptr %a) #0 {
   ret <2 x float> %load
 }
 
-define <4 x i32> @load_v4i32(ptr %a) #0 {
+define <4 x i32> @load_v4i32(ptr %a) {
 ; CHECK-LABEL: load_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -147,7 +147,7 @@ define <4 x i32> @load_v4i32(ptr %a) #0 {
   ret <4 x i32> %load
 }
 
-define <4 x float> @load_v4f32(ptr %a) #0 {
+define <4 x float> @load_v4f32(ptr %a) {
 ; CHECK-LABEL: load_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -156,7 +156,7 @@ define <4 x float> @load_v4f32(ptr %a) #0 {
   ret <4 x float> %load
 }
 
-define <8 x i32> @load_v8i32(ptr %a) #0 {
+define <8 x i32> @load_v8i32(ptr %a) {
 ; CHECK-LABEL: load_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -165,7 +165,7 @@ define <8 x i32> @load_v8i32(ptr %a) #0 {
   ret <8 x i32> %load
 }
 
-define <8 x float> @load_v8f32(ptr %a) #0 {
+define <8 x float> @load_v8f32(ptr %a) {
 ; CHECK-LABEL: load_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -174,7 +174,7 @@ define <8 x float> @load_v8f32(ptr %a) #0 {
   ret <8 x float> %load
 }
 
-define <1 x i64> @load_v1i64(ptr %a) #0 {
+define <1 x i64> @load_v1i64(ptr %a) {
 ; CHECK-LABEL: load_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -183,7 +183,7 @@ define <1 x i64> @load_v1i64(ptr %a) #0 {
   ret <1 x i64> %load
 }
 
-define <1 x double> @load_v1f64(ptr %a) #0 {
+define <1 x double> @load_v1f64(ptr %a) {
 ; CHECK-LABEL: load_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -192,7 +192,7 @@ define <1 x double> @load_v1f64(ptr %a) #0 {
   ret <1 x double> %load
 }
 
-define <2 x i64> @load_v2i64(ptr %a) #0 {
+define <2 x i64> @load_v2i64(ptr %a) {
 ; CHECK-LABEL: load_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -201,7 +201,7 @@ define <2 x i64> @load_v2i64(ptr %a) #0 {
   ret <2 x i64> %load
 }
 
-define <2 x double> @load_v2f64(ptr %a) #0 {
+define <2 x double> @load_v2f64(ptr %a) {
 ; CHECK-LABEL: load_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -210,7 +210,7 @@ define <2 x double> @load_v2f64(ptr %a) #0 {
   ret <2 x double> %load
 }
 
-define <4 x i64> @load_v4i64(ptr %a) #0 {
+define <4 x i64> @load_v4i64(ptr %a) {
 ; CHECK-LABEL: load_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -219,7 +219,7 @@ define <4 x i64> @load_v4i64(ptr %a) #0 {
   ret <4 x i64> %load
 }
 
-define <4 x double> @load_v4f64(ptr %a) #0 {
+define <4 x double> @load_v4f64(ptr %a) {
 ; CHECK-LABEL: load_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -228,5 +228,3 @@ define <4 x double> @load_v4f64(ptr %a) #0 {
   ret <4 x double> %load
 }
 
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
index cf2c826db54e0..c42be3a535489 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; ANDV
 ;
 
-define i8 @andv_v4i8(<4 x i8> %a) #0 {
+define i8 @andv_v4i8(<4 x i8> %a) {
 ; CHECK-LABEL: andv_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -19,7 +20,7 @@ define i8 @andv_v4i8(<4 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @andv_v8i8(<8 x i8> %a) #0 {
+define i8 @andv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: andv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -31,7 +32,7 @@ define i8 @andv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @andv_v16i8(<16 x i8> %a) #0 {
+define i8 @andv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: andv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -43,7 +44,7 @@ define i8 @andv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @andv_v32i8(ptr %a) #0 {
+define i8 @andv_v32i8(ptr %a) {
 ; CHECK-LABEL: andv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -57,7 +58,7 @@ define i8 @andv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @andv_v2i16(<2 x i16> %a) #0 {
+define i16 @andv_v2i16(<2 x i16> %a) {
 ; CHECK-LABEL: andv_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -69,7 +70,7 @@ define i16 @andv_v2i16(<2 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @andv_v4i16(<4 x i16> %a) #0 {
+define i16 @andv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: andv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -81,7 +82,7 @@ define i16 @andv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @andv_v8i16(<8 x i16> %a) #0 {
+define i16 @andv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: andv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -93,7 +94,7 @@ define i16 @andv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @andv_v16i16(ptr %a) #0 {
+define i16 @andv_v16i16(ptr %a) {
 ; CHECK-LABEL: andv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -107,7 +108,7 @@ define i16 @andv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @andv_v2i32(<2 x i32> %a) #0 {
+define i32 @andv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: andv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -119,7 +120,7 @@ define i32 @andv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @andv_v4i32(<4 x i32> %a) #0 {
+define i32 @andv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: andv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -131,7 +132,7 @@ define i32 @andv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @andv_v8i32(ptr %a) #0 {
+define i32 @andv_v8i32(ptr %a) {
 ; CHECK-LABEL: andv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -145,7 +146,7 @@ define i32 @andv_v8i32(ptr %a) #0 {
   ret i32 %res
 }
 
-define i64 @andv_v2i64(<2 x i64> %a) #0 {
+define i64 @andv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: andv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -157,7 +158,7 @@ define i64 @andv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @andv_v4i64(ptr %a) #0 {
+define i64 @andv_v4i64(ptr %a) {
 ; CHECK-LABEL: andv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -175,7 +176,7 @@ define i64 @andv_v4i64(ptr %a) #0 {
 ; EORV
 ;
 
-define i8 @eorv_v4i8(<4 x i8> %a) #0 {
+define i8 @eorv_v4i8(<4 x i8> %a) {
 ; CHECK-LABEL: eorv_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -187,7 +188,7 @@ define i8 @eorv_v4i8(<4 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @eorv_v8i8(<8 x i8> %a) #0 {
+define i8 @eorv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: eorv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -199,7 +200,7 @@ define i8 @eorv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @eorv_v16i8(<16 x i8> %a) #0 {
+define i8 @eorv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: eorv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -211,7 +212,7 @@ define i8 @eorv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @eorv_v32i8(ptr %a) #0 {
+define i8 @eorv_v32i8(ptr %a) {
 ; CHECK-LABEL: eorv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -225,7 +226,7 @@ define i8 @eorv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @eorv_v2i16(<2 x i16> %a) #0 {
+define i16 @eorv_v2i16(<2 x i16> %a) {
 ; CHECK-LABEL: eorv_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -237,7 +238,7 @@ define i16 @eorv_v2i16(<2 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @eorv_v4i16(<4 x i16> %a) #0 {
+define i16 @eorv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: eorv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -249,7 +250,7 @@ define i16 @eorv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @eorv_v8i16(<8 x i16> %a) #0 {
+define i16 @eorv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: eorv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -261,7 +262,7 @@ define i16 @eorv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @eorv_v16i16(ptr %a) #0 {
+define i16 @eorv_v16i16(ptr %a) {
 ; CHECK-LABEL: eorv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -275,7 +276,7 @@ define i16 @eorv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @eorv_v2i32(<2 x i32> %a) #0 {
+define i32 @eorv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: eorv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -287,7 +288,7 @@ define i32 @eorv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @eorv_v4i32(<4 x i32> %a) #0 {
+define i32 @eorv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: eorv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -299,7 +300,7 @@ define i32 @eorv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @eorv_v8i32(ptr %a) #0 {
+define i32 @eorv_v8i32(ptr %a) {
 ; CHECK-LABEL: eorv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -313,7 +314,7 @@ define i32 @eorv_v8i32(ptr %a) #0 {
   ret i32 %res
 }
 
-define i64 @eorv_v2i64(<2 x i64> %a) #0 {
+define i64 @eorv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: eorv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -325,7 +326,7 @@ define i64 @eorv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @eorv_v4i64(ptr %a) #0 {
+define i64 @eorv_v4i64(ptr %a) {
 ; CHECK-LABEL: eorv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -343,7 +344,7 @@ define i64 @eorv_v4i64(ptr %a) #0 {
 ; ORV
 ;
 
-define i8 @orv_v4i8(<4 x i8> %a) #0 {
+define i8 @orv_v4i8(<4 x i8> %a) {
 ; CHECK-LABEL: orv_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -355,7 +356,7 @@ define i8 @orv_v4i8(<4 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @orv_v8i8(<8 x i8> %a) #0 {
+define i8 @orv_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: orv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -367,7 +368,7 @@ define i8 @orv_v8i8(<8 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @orv_v16i8(<16 x i8> %a) #0 {
+define i8 @orv_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: orv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -379,7 +380,7 @@ define i8 @orv_v16i8(<16 x i8> %a) #0 {
   ret i8 %res
 }
 
-define i8 @orv_v32i8(ptr %a) #0 {
+define i8 @orv_v32i8(ptr %a) {
 ; CHECK-LABEL: orv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -393,7 +394,7 @@ define i8 @orv_v32i8(ptr %a) #0 {
   ret i8 %res
 }
 
-define i16 @orv_v2i16(<2 x i16> %a) #0 {
+define i16 @orv_v2i16(<2 x i16> %a) {
 ; CHECK-LABEL: orv_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -405,7 +406,7 @@ define i16 @orv_v2i16(<2 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @orv_v4i16(<4 x i16> %a) #0 {
+define i16 @orv_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: orv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -417,7 +418,7 @@ define i16 @orv_v4i16(<4 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @orv_v8i16(<8 x i16> %a) #0 {
+define i16 @orv_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: orv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -429,7 +430,7 @@ define i16 @orv_v8i16(<8 x i16> %a) #0 {
   ret i16 %res
 }
 
-define i16 @orv_v16i16(ptr %a) #0 {
+define i16 @orv_v16i16(ptr %a) {
 ; CHECK-LABEL: orv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -443,7 +444,7 @@ define i16 @orv_v16i16(ptr %a) #0 {
   ret i16 %res
 }
 
-define i32 @orv_v2i32(<2 x i32> %a) #0 {
+define i32 @orv_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: orv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -455,7 +456,7 @@ define i32 @orv_v2i32(<2 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @orv_v4i32(<4 x i32> %a) #0 {
+define i32 @orv_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: orv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -467,7 +468,7 @@ define i32 @orv_v4i32(<4 x i32> %a) #0 {
   ret i32 %res
 }
 
-define i32 @orv_v8i32(ptr %a) #0 {
+define i32 @orv_v8i32(ptr %a) {
 ; CHECK-LABEL: orv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -481,7 +482,7 @@ define i32 @orv_v8i32(ptr %a) #0 {
   ret i32 %res
 }
 
-define i64 @orv_v2i64(<2 x i64> %a) #0 {
+define i64 @orv_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: orv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -493,7 +494,7 @@ define i64 @orv_v2i64(<2 x i64> %a) #0 {
   ret i64 %res
 }
 
-define i64 @orv_v4i64(ptr %a) #0 {
+define i64 @orv_v4i64(ptr %a) {
 ; CHECK-LABEL: orv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -507,8 +508,6 @@ define i64 @orv_v4i64(ptr %a) #0 {
   ret i64 %res
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
 declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
 declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
index 13d84d31bce91..e746770e29a2f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; Masked Load
 ;
 
-define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) #0 {
+define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -22,7 +23,7 @@ define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) #0 {
   ret <4 x i8> %load
 }
 
-define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) #0 {
+define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -37,7 +38,7 @@ define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) #0 {
   ret <8 x i8> %load
 }
 
-define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) #0 {
+define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -52,7 +53,7 @@ define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) #0 {
   ret <16 x i8> %load
 }
 
-define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) #0 {
+define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #32
@@ -133,7 +134,7 @@ define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) #0 {
   ret <32 x i8> %load
 }
 
-define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) #0 {
+define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -158,7 +159,7 @@ define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) #0 {
   ret <2 x half> %load
 }
 
-define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) #0 {
+define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -173,7 +174,7 @@ define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) #0 {
   ret <4 x half> %load
 }
 
-define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) #0 {
+define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -189,7 +190,7 @@ define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) #0 {
   ret <8 x half> %load
 }
 
-define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) #0 {
+define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -213,7 +214,7 @@ define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) #0 {
   ret <16 x half> %load
 }
 
-define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) #0 {
+define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -228,7 +229,7 @@ define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) #0 {
   ret <2 x float> %load
 }
 
-define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) #0 {
+define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -244,7 +245,7 @@ define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) #0 {
   ret <4 x float> %load
 }
 
-define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) #0 {
+define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -293,7 +294,7 @@ define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) #0 {
   ret <8 x float> %load
 }
 
-define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) #0 {
+define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -309,7 +310,7 @@ define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) #0 {
   ret <2 x double> %load
 }
 
-define <4 x double> @masked_load_v4f64(ptr %src, <4 x i1> %mask) #0 {
+define <4 x double> @masked_load_v4f64(ptr %src, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_load_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -350,5 +351,3 @@ declare <8 x float> @llvm.masked.load.v8f32(ptr, i32, <8 x i1>, <8 x float>)
 
 declare <2 x double> @llvm.masked.load.v2f64(ptr, i32, <2 x i1>, <2 x double>)
 declare <4 x double> @llvm.masked.load.v4f64(ptr, i32, <4 x i1>, <4 x double>)
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
index acdbcd6ed9671..f6aa59fd7c804 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; Masked Store
 ;
 
-define void @masked_store_v4i8(ptr %dst, <4 x i1> %mask) #0 {
+define void @masked_store_v4i8(ptr %dst, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -22,7 +23,7 @@ define void @masked_store_v4i8(ptr %dst, <4 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v8i8(ptr %dst, <8 x i1> %mask) #0 {
+define void @masked_store_v8i8(ptr %dst, <8 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -37,7 +38,7 @@ define void @masked_store_v8i8(ptr %dst, <8 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v16i8(ptr %dst, <16 x i1> %mask) #0 {
+define void @masked_store_v16i8(ptr %dst, <16 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -52,7 +53,7 @@ define void @masked_store_v16i8(ptr %dst, <16 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v32i8(ptr %dst, <32 x i1> %mask) #0 {
+define void @masked_store_v32i8(ptr %dst, <32 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #32
@@ -132,7 +133,7 @@ define void @masked_store_v32i8(ptr %dst, <32 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v2f16(ptr %dst, <2 x i1> %mask) #0 {
+define void @masked_store_v2f16(ptr %dst, <2 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -157,7 +158,7 @@ define void @masked_store_v2f16(ptr %dst, <2 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v4f16(ptr %dst, <4 x i1> %mask) #0 {
+define void @masked_store_v4f16(ptr %dst, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -172,7 +173,7 @@ define void @masked_store_v4f16(ptr %dst, <4 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v8f16(ptr %dst, <8 x i1> %mask) #0 {
+define void @masked_store_v8f16(ptr %dst, <8 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -188,7 +189,7 @@ define void @masked_store_v8f16(ptr %dst, <8 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v16f16(ptr %dst, <16 x i1> %mask) #0 {
+define void @masked_store_v16f16(ptr %dst, <16 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -212,7 +213,7 @@ define void @masked_store_v16f16(ptr %dst, <16 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v4f32(ptr %dst, <4 x i1> %mask) #0 {
+define void @masked_store_v4f32(ptr %dst, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -228,7 +229,7 @@ define void @masked_store_v4f32(ptr %dst, <4 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) #0 {
+define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -278,7 +279,7 @@ define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v2f64(ptr %dst, <2 x i1> %mask) #0 {
+define void @masked_store_v2f64(ptr %dst, <2 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -294,7 +295,7 @@ define void @masked_store_v2f64(ptr %dst, <2 x i1> %mask) #0 {
   ret void
 }
 
-define void @masked_store_v4f64(ptr %dst, <4 x i1> %mask) #0 {
+define void @masked_store_v4f64(ptr %dst, <4 x i1> %mask) {
 ; CHECK-LABEL: masked_store_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -330,5 +331,3 @@ declare void @llvm.masked.store.v4f32(<4 x float>, ptr, i32, <4 x i1>)
 declare void @llvm.masked.store.v8f32(<8 x float>, ptr, i32, <8 x i1>)
 declare void @llvm.masked.store.v2f64(<2 x double>, ptr, i32, <2 x i1>)
 declare void @llvm.masked.store.v4f64(<4 x double>, ptr, i32, <4 x i1>)
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
index 904fac734ca1a..c8cbc6b14d631 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @add_v4i8(ptr %a, ptr %b) #0 {
+define void @add_v4i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -19,7 +20,7 @@ define void @add_v4i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @add_v8i8(ptr %a, ptr %b) #0 {
+define void @add_v8i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -34,7 +35,7 @@ define void @add_v8i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @add_v16i8(ptr %a, ptr %b) #0 {
+define void @add_v16i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -49,7 +50,7 @@ define void @add_v16i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @add_v32i8(ptr %a, ptr %b) #0 {
+define void @add_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: add_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -65,7 +66,7 @@ define void @add_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @add_v2i16(ptr %a, ptr %b, ptr %c) #0 {
+define void @add_v2i16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: add_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -91,7 +92,7 @@ define void @add_v2i16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define void @add_v4i16(ptr %a, ptr %b, ptr %c) #0 {
+define void @add_v4i16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: add_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -106,7 +107,7 @@ define void @add_v4i16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define void @add_v8i16(ptr %a, ptr %b, ptr %c) #0 {
+define void @add_v8i16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: add_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -121,7 +122,7 @@ define void @add_v8i16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define void @add_v16i16(ptr %a, ptr %b, ptr %c) #0 {
+define void @add_v16i16(ptr %a, ptr %b, ptr %c) {
 ; CHECK-LABEL: add_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -137,7 +138,7 @@ define void @add_v16i16(ptr %a, ptr %b, ptr %c) #0 {
   ret void
 }
 
-define void @abs_v2i32(ptr %a) #0 {
+define void @abs_v2i32(ptr %a) {
 ; CHECK-LABEL: abs_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -151,7 +152,7 @@ define void @abs_v2i32(ptr %a) #0 {
   ret void
 }
 
-define void @abs_v4i32(ptr %a) #0 {
+define void @abs_v4i32(ptr %a) {
 ; CHECK-LABEL: abs_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -165,7 +166,7 @@ define void @abs_v4i32(ptr %a) #0 {
   ret void
 }
 
-define void @abs_v8i32(ptr %a) #0 {
+define void @abs_v8i32(ptr %a) {
 ; CHECK-LABEL: abs_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -180,7 +181,7 @@ define void @abs_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @abs_v2i64(ptr %a) #0 {
+define void @abs_v2i64(ptr %a) {
 ; CHECK-LABEL: abs_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -194,7 +195,7 @@ define void @abs_v2i64(ptr %a) #0 {
   ret void
 }
 
-define void @abs_v4i64(ptr %a) #0 {
+define void @abs_v4i64(ptr %a) {
 ; CHECK-LABEL: abs_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -209,7 +210,7 @@ define void @abs_v4i64(ptr %a) #0 {
   ret void
 }
 
-define void @fadd_v2f16(ptr %a, ptr %b) #0 {
+define void @fadd_v2f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr s0, [x0]
@@ -226,7 +227,7 @@ define void @fadd_v2f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v4f16(ptr %a, ptr %b) #0 {
+define void @fadd_v4f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -242,7 +243,7 @@ define void @fadd_v4f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v8f16(ptr %a, ptr %b) #0 {
+define void @fadd_v8f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -258,7 +259,7 @@ define void @fadd_v8f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v16f16(ptr %a, ptr %b) #0 {
+define void @fadd_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -275,7 +276,7 @@ define void @fadd_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v2f32(ptr %a, ptr %b) #0 {
+define void @fadd_v2f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -291,7 +292,7 @@ define void @fadd_v2f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v4f32(ptr %a, ptr %b) #0 {
+define void @fadd_v4f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -307,7 +308,7 @@ define void @fadd_v4f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v8f32(ptr %a, ptr %b) #0 {
+define void @fadd_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -324,7 +325,7 @@ define void @fadd_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v2f64(ptr %a, ptr %b) #0 {
+define void @fadd_v2f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -340,7 +341,7 @@ define void @fadd_v2f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @fadd_v4f64(ptr %a, ptr %b) #0 {
+define void @fadd_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: fadd_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -362,5 +363,3 @@ declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
 declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
 declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
 declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
index 961c17f5a24e2..c4c87debac087 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
@@ -1,10 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; REVB pattern for shuffle v32i8 -> v16i16
-define void @test_revbv16i16(ptr %a) #0 {
+define void @test_revbv16i16(ptr %a) {
 ; CHECK-LABEL: test_revbv16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -20,7 +21,7 @@ define void @test_revbv16i16(ptr %a) #0 {
 }
 
 ; REVB pattern for shuffle v32i8 -> v8i32
-define void @test_revbv8i32(ptr %a) #0 {
+define void @test_revbv8i32(ptr %a) {
 ; CHECK-LABEL: test_revbv8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -36,7 +37,7 @@ define void @test_revbv8i32(ptr %a) #0 {
 }
 
 ; REVB pattern for shuffle v32i8 -> v4i64
-define void @test_revbv4i64(ptr %a) #0 {
+define void @test_revbv4i64(ptr %a) {
 ; CHECK-LABEL: test_revbv4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -52,7 +53,7 @@ define void @test_revbv4i64(ptr %a) #0 {
 }
 
 ; REVH pattern for shuffle v16i16 -> v8i32
-define void @test_revhv8i32(ptr %a) #0 {
+define void @test_revhv8i32(ptr %a) {
 ; CHECK-LABEL: test_revhv8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -68,7 +69,7 @@ define void @test_revhv8i32(ptr %a) #0 {
 }
 
 ; REVH pattern for shuffle v16f16 -> v8f32
-define void @test_revhv8f32(ptr %a) #0 {
+define void @test_revhv8f32(ptr %a) {
 ; CHECK-LABEL: test_revhv8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -84,7 +85,7 @@ define void @test_revhv8f32(ptr %a) #0 {
 }
 
 ; REVH pattern for shuffle v16i16 -> v4i64
-define void @test_revhv4i64(ptr %a) #0 {
+define void @test_revhv4i64(ptr %a) {
 ; CHECK-LABEL: test_revhv4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -100,7 +101,7 @@ define void @test_revhv4i64(ptr %a) #0 {
 }
 
 ; REVW pattern for shuffle v8i32 -> v4i64
-define void @test_revwv4i64(ptr %a) #0 {
+define void @test_revwv4i64(ptr %a) {
 ; CHECK-LABEL: test_revwv4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -116,7 +117,7 @@ define void @test_revwv4i64(ptr %a) #0 {
 }
 
 ; REVW pattern for shuffle v8f32 -> v4f64
-define void @test_revwv4f64(ptr %a) #0 {
+define void @test_revwv4f64(ptr %a) {
 ; CHECK-LABEL: test_revwv4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -131,7 +132,7 @@ define void @test_revwv4f64(ptr %a) #0 {
   ret void
 }
 
-define <16 x i8> @test_revv16i8(ptr %a) #0 {
+define <16 x i8> @test_revv16i8(ptr %a) {
 ; CHECK-LABEL: test_revv16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -145,7 +146,7 @@ define <16 x i8> @test_revv16i8(ptr %a) #0 {
 }
 
 ; REVW pattern for shuffle two v8i32 inputs with the second input available.
-define void @test_revwv8i32v8i32(ptr %a, ptr %b) #0 {
+define void @test_revwv8i32v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: test_revwv8i32v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
@@ -161,7 +162,7 @@ define void @test_revwv8i32v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @test_revhv32i16(ptr %a) #0 {
+define void @test_revhv32i16(ptr %a) {
 ; CHECK-LABEL: test_revhv32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -180,7 +181,7 @@ define void @test_revhv32i16(ptr %a) #0 {
   ret void
 }
 
-define void @test_rev_elts_fail(ptr %a) #0 {
+define void @test_rev_elts_fail(ptr %a) {
 ; CHECK-LABEL: test_rev_elts_fail:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -235,7 +236,7 @@ define void @test_revdv4f64_sve2p1(ptr %a) #1 {
   ret void
 }
 
-define void @test_revv8i32(ptr %a) #0 {
+define void @test_revv8i32(ptr %a) {
 ; CHECK-LABEL: test_revv8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #32
@@ -268,6 +269,4 @@ define void @test_revv8i32(ptr %a) #0 {
   store <8 x i32> %tmp2, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
 attributes #1 = { "target-features"="+sve2p1" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
index 8712985b41588..80edfc5ada010 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @zip1_v32i8(ptr %a, ptr %b) #0 {
+define void @zip1_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip1_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -73,7 +74,7 @@ define void @zip1_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @zip_v32i16(ptr %a, ptr %b) #0 {
+define void @zip_v32i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip_v32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #64
@@ -203,7 +204,7 @@ define void @zip_v32i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @zip1_v16i16(ptr %a, ptr %b) #0 {
+define void @zip1_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip1_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -249,7 +250,7 @@ define void @zip1_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @zip1_v8i32(ptr %a, ptr %b) #0 {
+define void @zip1_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip1_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -281,7 +282,7 @@ define void @zip1_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @zip_v4f64(ptr %a, ptr %b) #0 {
+define void @zip_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -304,7 +305,7 @@ define void @zip_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @zip_v4i32(ptr %a, ptr %b) #0 {
+define void @zip_v4i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -336,7 +337,7 @@ define void @zip_v4i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @zip1_v8i32_undef(ptr %a) #0 {
+define void @zip1_v8i32_undef(ptr %a) {
 ; CHECK-LABEL: zip1_v8i32_undef:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -361,7 +362,7 @@ define void @zip1_v8i32_undef(ptr %a) #0 {
   ret void
 }
 
-define void @trn_v32i8(ptr %a, ptr %b) #0 {
+define void @trn_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: trn_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -383,7 +384,7 @@ define void @trn_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @trn_v8i16(ptr %a, ptr %b) #0 {
+define void @trn_v8i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: trn_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -431,7 +432,7 @@ define void @trn_v8i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @trn_v16i16(ptr %a, ptr %b) #0 {
+define void @trn_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: trn_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -453,7 +454,7 @@ define void @trn_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @trn_v8i32(ptr %a, ptr %b) #0 {
+define void @trn_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: trn_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -475,7 +476,7 @@ define void @trn_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @trn_v4f64(ptr %a, ptr %b) #0 {
+define void @trn_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: trn_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -498,7 +499,7 @@ define void @trn_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @trn_v4f32(ptr %a, ptr %b) #0 {
+define void @trn_v4f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: trn_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -518,7 +519,7 @@ define void @trn_v4f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @trn_v8i32_undef(ptr %a) #0 {
+define void @trn_v8i32_undef(ptr %a) {
 ; CHECK-LABEL: trn_v8i32_undef:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -1245,7 +1246,7 @@ define void @uzp_v8i32_undef(ptr %a) #0{
   ret void
 }
 
-define void @zip_vscale2_4(ptr %a, ptr %b) #0 {
+define void @zip_vscale2_4(ptr %a, ptr %b) {
 ; CHECK-LABEL: zip_vscale2_4:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
@@ -1267,5 +1268,3 @@ define void @zip_vscale2_4(ptr %a, ptr %b) #0 {
   store <4 x double> %tmp5, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
index 0841fbe1763c6..93146398a653c 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define i1 @ptest_v16i1(ptr %a, ptr %b) #0 {
+define i1 @ptest_v16i1(ptr %a, ptr %b) {
 ; CHECK-LABEL: ptest_v16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -40,7 +41,7 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) #0 {
   ret i1 %v3
 }
 
-define i1 @ptest_or_v16i1(ptr %a, ptr %b) #0 {
+define i1 @ptest_or_v16i1(ptr %a, ptr %b) {
 ; CHECK-LABEL: ptest_or_v16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -107,7 +108,7 @@ declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>)
 ; AND reduction.
 ;
 
-define i1 @ptest_and_v16i1(ptr %a, ptr %b) #0 {
+define i1 @ptest_and_v16i1(ptr %a, ptr %b) {
 ; CHECK-LABEL: ptest_and_v16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -168,6 +169,4 @@ define i1 @ptest_and_v16i1(ptr %a, ptr %b) #0 {
   ret i1 %v7
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare i1 @llvm.vector.reduce.and.i1.v16i1(<16 x i1>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
index 546d08e6bad35..3dd08f04f2619 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
@@ -1,11 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; == Matching first N elements ==
 
-define <4 x i1> @reshuffle_v4i1_nxv4i1(<vscale x 4 x i1> %a) #0 {
+define <4 x i1> @reshuffle_v4i1_nxv4i1(<vscale x 4 x i1> %a) {
 ; CHECK-LABEL: reshuffle_v4i1_nxv4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -35,5 +36,3 @@ define <4 x i1> @reshuffle_v4i1_nxv4i1(<vscale x 4 x i1> %a) #0 {
   %v3 = insertelement <4 x i1> %v2, i1 %el3, i32 3
   ret <4 x i1> %v3
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
index 1d034e4475c91..c4cc4d9d408de 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; RBIT
 ;
 
-define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) #0 {
+define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) {
 ; CHECK-LABEL: bitreverse_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -20,7 +21,7 @@ define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) #0 {
+define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) {
 ; CHECK-LABEL: bitreverse_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -32,7 +33,7 @@ define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) #0 {
+define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) {
 ; CHECK-LABEL: bitreverse_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -44,7 +45,7 @@ define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) #0 {
   ret <16 x i8> %res
 }
 
-define void @bitreverse_v32i8(ptr %a) #0 {
+define void @bitreverse_v32i8(ptr %a) {
 ; CHECK-LABEL: bitreverse_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -59,7 +60,7 @@ define void @bitreverse_v32i8(ptr %a) #0 {
   ret void
 }
 
-define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) #0 {
+define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) {
 ; CHECK-LABEL: bitreverse_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -72,7 +73,7 @@ define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) #0 {
+define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) {
 ; CHECK-LABEL: bitreverse_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -84,7 +85,7 @@ define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) #0 {
+define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) {
 ; CHECK-LABEL: bitreverse_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -96,7 +97,7 @@ define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) #0 {
   ret <8 x i16> %res
 }
 
-define void @bitreverse_v16i16(ptr %a) #0 {
+define void @bitreverse_v16i16(ptr %a) {
 ; CHECK-LABEL: bitreverse_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -111,7 +112,7 @@ define void @bitreverse_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) #0 {
+define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) {
 ; CHECK-LABEL: bitreverse_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -123,7 +124,7 @@ define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) #0 {
+define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) {
 ; CHECK-LABEL: bitreverse_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -135,7 +136,7 @@ define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) #0 {
   ret <4 x i32> %res
 }
 
-define void @bitreverse_v8i32(ptr %a) #0 {
+define void @bitreverse_v8i32(ptr %a) {
 ; CHECK-LABEL: bitreverse_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -150,7 +151,7 @@ define void @bitreverse_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) #0 {
+define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) {
 ; CHECK-LABEL: bitreverse_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -162,7 +163,7 @@ define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) #0 {
+define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) {
 ; CHECK-LABEL: bitreverse_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -174,7 +175,7 @@ define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) #0 {
   ret <2 x i64> %res
 }
 
-define void @bitreverse_v4i64(ptr %a) #0 {
+define void @bitreverse_v4i64(ptr %a) {
 ; CHECK-LABEL: bitreverse_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -193,7 +194,7 @@ define void @bitreverse_v4i64(ptr %a) #0 {
 ; REVB
 ;
 
-define <2 x i16> @bswap_v2i16(<2 x i16> %op) #0 {
+define <2 x i16> @bswap_v2i16(<2 x i16> %op) {
 ; CHECK-LABEL: bswap_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -206,7 +207,7 @@ define <2 x i16> @bswap_v2i16(<2 x i16> %op) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 {
+define <4 x i16> @bswap_v4i16(<4 x i16> %op) {
 ; CHECK-LABEL: bswap_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -218,7 +219,7 @@ define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @bswap_v8i16(<8 x i16> %op) #0 {
+define <8 x i16> @bswap_v8i16(<8 x i16> %op) {
 ; CHECK-LABEL: bswap_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -230,7 +231,7 @@ define <8 x i16> @bswap_v8i16(<8 x i16> %op) #0 {
   ret <8 x i16> %res
 }
 
-define void @bswap_v16i16(ptr %a) #0 {
+define void @bswap_v16i16(ptr %a) {
 ; CHECK-LABEL: bswap_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -245,7 +246,7 @@ define void @bswap_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 {
+define <2 x i32> @bswap_v2i32(<2 x i32> %op) {
 ; CHECK-LABEL: bswap_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -257,7 +258,7 @@ define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 {
+define <4 x i32> @bswap_v4i32(<4 x i32> %op) {
 ; CHECK-LABEL: bswap_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -269,7 +270,7 @@ define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 {
   ret <4 x i32> %res
 }
 
-define void @bswap_v8i32(ptr %a) #0 {
+define void @bswap_v8i32(ptr %a) {
 ; CHECK-LABEL: bswap_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -284,7 +285,7 @@ define void @bswap_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
+define <1 x i64> @bswap_v1i64(<1 x i64> %op) {
 ; CHECK-LABEL: bswap_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -296,7 +297,7 @@ define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
   ret <1 x i64> %res
 }
 
-define <2 x i64> @bswap_v2i64(<2 x i64> %op) #0 {
+define <2 x i64> @bswap_v2i64(<2 x i64> %op) {
 ; CHECK-LABEL: bswap_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -308,7 +309,7 @@ define <2 x i64> @bswap_v2i64(<2 x i64> %op) #0 {
   ret <2 x i64> %res
 }
 
-define void @bswap_v4i64(ptr %a) #0 {
+define void @bswap_v4i64(ptr %a) {
 ; CHECK-LABEL: bswap_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -323,8 +324,6 @@ define void @bswap_v4i64(ptr %a) #0 {
   ret void
 }
 
-attributes #0 = { "target-features"="+sve" }
-
 declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>)
 declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>)
 declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
index 9f0102075b5c6..355dcc6b3faee 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) #0 {
+define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) {
 ; CHECK-LABEL: sdiv_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -16,7 +17,7 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) #0 {
   ret <4 x i8> %res
 }
 
-define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) #0 {
+define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) {
 ; CHECK-LABEL: sdiv_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -28,7 +29,7 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) #0 {
   ret <8 x i8> %res
 }
 
-define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) #0 {
+define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) {
 ; CHECK-LABEL: sdiv_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -40,7 +41,7 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) #0 {
   ret <16 x i8> %res
 }
 
-define void @sdiv_v32i8(ptr %a) #0 {
+define void @sdiv_v32i8(ptr %a) {
 ; CHECK-LABEL: sdiv_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -55,7 +56,7 @@ define void @sdiv_v32i8(ptr %a) #0 {
   ret void
 }
 
-define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) #0 {
+define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) {
 ; CHECK-LABEL: sdiv_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -68,7 +69,7 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) #0 {
   ret <2 x i16> %res
 }
 
-define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) #0 {
+define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) {
 ; CHECK-LABEL: sdiv_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -80,7 +81,7 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) #0 {
   ret <4 x i16> %res
 }
 
-define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) #0 {
+define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) {
 ; CHECK-LABEL: sdiv_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -92,7 +93,7 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) #0 {
   ret <8 x i16> %res
 }
 
-define void @sdiv_v16i16(ptr %a) #0 {
+define void @sdiv_v16i16(ptr %a) {
 ; CHECK-LABEL: sdiv_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -107,7 +108,7 @@ define void @sdiv_v16i16(ptr %a) #0 {
   ret void
 }
 
-define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) #0 {
+define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) {
 ; CHECK-LABEL: sdiv_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -119,7 +120,7 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) #0 {
   ret <2 x i32> %res
 }
 
-define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) #0 {
+define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) {
 ; CHECK-LABEL: sdiv_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -131,7 +132,7 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) #0 {
   ret <4 x i32> %res
 }
 
-define void @sdiv_v8i32(ptr %a) #0 {
+define void @sdiv_v8i32(ptr %a) {
 ; CHECK-LABEL: sdiv_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -146,7 +147,7 @@ define void @sdiv_v8i32(ptr %a) #0 {
   ret void
 }
 
-define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) #0 {
+define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) {
 ; CHECK-LABEL: sdiv_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -159,7 +160,7 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) #0 {
 }
 
 ; Vector i64 sdiv are not legal for NEON so use SVE when available.
-define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) #0 {
+define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) {
 ; CHECK-LABEL: sdiv_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -171,7 +172,7 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) #0 {
   ret <2 x i64> %res
 }
 
-define void @sdiv_v4i64(ptr %a) #0 {
+define void @sdiv_v4i64(ptr %a) {
 ; CHECK-LABEL: sdiv_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -185,5 +186,3 @@ define void @sdiv_v4i64(ptr %a) #0 {
   store <4 x i64> %res, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
index ae8f53f0be990..6260295000804 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) #0 {
+define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) {
 ; CHECK-LABEL: hang_when_merging_stores_after_legalisation:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -18,7 +19,7 @@ define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) #
   ret void
 }
 
-define void @interleave_store_without_splat(ptr %a, <4 x i32> %v1, <4 x i32> %v2) #0 {
+define void @interleave_store_without_splat(ptr %a, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: interleave_store_without_splat:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
@@ -32,7 +33,7 @@ define void @interleave_store_without_splat(ptr %a, <4 x i32> %v1, <4 x i32> %v2
   ret void
 }
 
-define void @interleave_store_legalization(ptr %a, <8 x i32> %v1, <8 x i32> %v2) #0 {
+define void @interleave_store_legalization(ptr %a, <8 x i32> %v1, <8 x i32> %v2) {
 ; CHECK-LABEL: interleave_store_legalization:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #8 // =0x8
@@ -51,7 +52,7 @@ define void @interleave_store_legalization(ptr %a, <8 x i32> %v1, <8 x i32> %v2)
 }
 
 ; Ensure we don't crash when trying to lower a shuffle via an extract
-define void @crash_when_lowering_extract_shuffle(ptr %dst, i1 %cond) #0 {
+define void @crash_when_lowering_extract_shuffle(ptr %dst, i1 %cond) {
 ; CHECK-LABEL: crash_when_lowering_extract_shuffle:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
@@ -67,5 +68,3 @@ vector.body:
 exit:
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
index a8203cd639af1..323d5278592f3 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 
 target triple = "aarch64-unknown-linux-gnu"
@@ -8,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; DUP (integer)
 ;
 
-define <4 x i8> @splat_v4i8(i8 %a) #0 {
+define <4 x i8> @splat_v4i8(i8 %a) {
 ; CHECK-LABEL: splat_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, w0
@@ -19,7 +20,7 @@ define <4 x i8> @splat_v4i8(i8 %a) #0 {
   ret <4 x i8> %splat
 }
 
-define <8 x i8> @splat_v8i8(i8 %a) #0 {
+define <8 x i8> @splat_v8i8(i8 %a) {
 ; CHECK-LABEL: splat_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, w0
@@ -30,7 +31,7 @@ define <8 x i8> @splat_v8i8(i8 %a) #0 {
   ret <8 x i8> %splat
 }
 
-define <16 x i8> @splat_v16i8(i8 %a) #0 {
+define <16 x i8> @splat_v16i8(i8 %a) {
 ; CHECK-LABEL: splat_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, w0
@@ -41,7 +42,7 @@ define <16 x i8> @splat_v16i8(i8 %a) #0 {
   ret <16 x i8> %splat
 }
 
-define void @splat_v32i8(i8 %a, ptr %b) #0 {
+define void @splat_v32i8(i8 %a, ptr %b) {
 ; CHECK-LABEL: splat_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, w0
@@ -53,7 +54,7 @@ define void @splat_v32i8(i8 %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @splat_v2i16(i16 %a) #0 {
+define <2 x i16> @splat_v2i16(i16 %a) {
 ; CHECK-LABEL: splat_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, w0
@@ -64,7 +65,7 @@ define <2 x i16> @splat_v2i16(i16 %a) #0 {
   ret <2 x i16> %splat
 }
 
-define <4 x i16> @splat_v4i16(i16 %a) #0 {
+define <4 x i16> @splat_v4i16(i16 %a) {
 ; CHECK-LABEL: splat_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, w0
@@ -75,7 +76,7 @@ define <4 x i16> @splat_v4i16(i16 %a) #0 {
   ret <4 x i16> %splat
 }
 
-define <8 x i16> @splat_v8i16(i16 %a) #0 {
+define <8 x i16> @splat_v8i16(i16 %a) {
 ; CHECK-LABEL: splat_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, w0
@@ -86,7 +87,7 @@ define <8 x i16> @splat_v8i16(i16 %a) #0 {
   ret <8 x i16> %splat
 }
 
-define void @splat_v16i16(i16 %a, ptr %b) #0 {
+define void @splat_v16i16(i16 %a, ptr %b) {
 ; CHECK-LABEL: splat_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, w0
@@ -98,7 +99,7 @@ define void @splat_v16i16(i16 %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @splat_v2i32(i32 %a) #0 {
+define <2 x i32> @splat_v2i32(i32 %a) {
 ; CHECK-LABEL: splat_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, w0
@@ -109,7 +110,7 @@ define <2 x i32> @splat_v2i32(i32 %a) #0 {
   ret <2 x i32> %splat
 }
 
-define <4 x i32> @splat_v4i32(i32 %a) #0 {
+define <4 x i32> @splat_v4i32(i32 %a) {
 ; CHECK-LABEL: splat_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, w0
@@ -120,7 +121,7 @@ define <4 x i32> @splat_v4i32(i32 %a) #0 {
   ret <4 x i32> %splat
 }
 
-define void @splat_v8i32(i32 %a, ptr %b) #0 {
+define void @splat_v8i32(i32 %a, ptr %b) {
 ; CHECK-LABEL: splat_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, w0
@@ -132,7 +133,7 @@ define void @splat_v8i32(i32 %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x i64> @splat_v1i64(i64 %a) #0 {
+define <1 x i64> @splat_v1i64(i64 %a) {
 ; CHECK-LABEL: splat_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, x0
@@ -143,7 +144,7 @@ define <1 x i64> @splat_v1i64(i64 %a) #0 {
   ret <1 x i64> %splat
 }
 
-define <2 x i64> @splat_v2i64(i64 %a) #0 {
+define <2 x i64> @splat_v2i64(i64 %a) {
 ; CHECK-LABEL: splat_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, x0
@@ -154,7 +155,7 @@ define <2 x i64> @splat_v2i64(i64 %a) #0 {
   ret <2 x i64> %splat
 }
 
-define void @splat_v4i64(i64 %a, ptr %b) #0 {
+define void @splat_v4i64(i64 %a, ptr %b) {
 ; CHECK-LABEL: splat_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, x0
@@ -170,7 +171,7 @@ define void @splat_v4i64(i64 %a, ptr %b) #0 {
 ; DUP (floating-point)
 ;
 
-define <2 x half> @splat_v2f16(half %a) #0 {
+define <2 x half> @splat_v2f16(half %a) {
 ; CHECK-LABEL: splat_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -182,7 +183,7 @@ define <2 x half> @splat_v2f16(half %a) #0 {
   ret <2 x half> %splat
 }
 
-define <4 x half> @splat_v4f16(half %a) #0 {
+define <4 x half> @splat_v4f16(half %a) {
 ; CHECK-LABEL: splat_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -194,7 +195,7 @@ define <4 x half> @splat_v4f16(half %a) #0 {
   ret <4 x half> %splat
 }
 
-define <8 x half> @splat_v8f16(half %a) #0 {
+define <8 x half> @splat_v8f16(half %a) {
 ; CHECK-LABEL: splat_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -206,7 +207,7 @@ define <8 x half> @splat_v8f16(half %a) #0 {
   ret <8 x half> %splat
 }
 
-define void @splat_v16f16(half %a, ptr %b) #0 {
+define void @splat_v16f16(half %a, ptr %b) {
 ; CHECK-LABEL: splat_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -219,7 +220,7 @@ define void @splat_v16f16(half %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @splat_v2f32(float %a, <2 x float> %op2) #0 {
+define <2 x float> @splat_v2f32(float %a, <2 x float> %op2) {
 ; CHECK-LABEL: splat_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -231,7 +232,7 @@ define <2 x float> @splat_v2f32(float %a, <2 x float> %op2) #0 {
   ret <2 x float> %splat
 }
 
-define <4 x float> @splat_v4f32(float %a, <4 x float> %op2) #0 {
+define <4 x float> @splat_v4f32(float %a, <4 x float> %op2) {
 ; CHECK-LABEL: splat_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -243,7 +244,7 @@ define <4 x float> @splat_v4f32(float %a, <4 x float> %op2) #0 {
   ret <4 x float> %splat
 }
 
-define void @splat_v8f32(float %a, ptr %b) #0 {
+define void @splat_v8f32(float %a, ptr %b) {
 ; CHECK-LABEL: splat_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -256,7 +257,7 @@ define void @splat_v8f32(float %a, ptr %b) #0 {
   ret void
 }
 
-define <1 x double> @splat_v1f64(double %a, <1 x double> %op2) #0 {
+define <1 x double> @splat_v1f64(double %a, <1 x double> %op2) {
 ; CHECK-LABEL: splat_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
@@ -265,7 +266,7 @@ define <1 x double> @splat_v1f64(double %a, <1 x double> %op2) #0 {
   ret <1 x double> %splat
 }
 
-define <2 x double> @splat_v2f64(double %a, <2 x double> %op2) #0 {
+define <2 x double> @splat_v2f64(double %a, <2 x double> %op2) {
 ; CHECK-LABEL: splat_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -277,7 +278,7 @@ define <2 x double> @splat_v2f64(double %a, <2 x double> %op2) #0 {
   ret <2 x double> %splat
 }
 
-define void @splat_v4f64(double %a, ptr %b) #0 {
+define void @splat_v4f64(double %a, ptr %b) {
 ; CHECK-LABEL: splat_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -294,7 +295,7 @@ define void @splat_v4f64(double %a, ptr %b) #0 {
 ; DUP (integer immediate)
 ;
 
-define void @splat_imm_v32i8(ptr %a) #0 {
+define void @splat_imm_v32i8(ptr %a) {
 ; CHECK-LABEL: splat_imm_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, #1 // =0x1
@@ -306,7 +307,7 @@ define void @splat_imm_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @splat_imm_v16i16(ptr %a) #0 {
+define void @splat_imm_v16i16(ptr %a) {
 ; CHECK-LABEL: splat_imm_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #2 // =0x2
@@ -318,7 +319,7 @@ define void @splat_imm_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @splat_imm_v8i32(ptr %a) #0 {
+define void @splat_imm_v8i32(ptr %a) {
 ; CHECK-LABEL: splat_imm_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, #3 // =0x3
@@ -330,7 +331,7 @@ define void @splat_imm_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @splat_imm_v4i64(ptr %a) #0 {
+define void @splat_imm_v4i64(ptr %a) {
 ; CHECK-LABEL: splat_imm_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #4 // =0x4
@@ -346,7 +347,7 @@ define void @splat_imm_v4i64(ptr %a) #0 {
 ; DUP (floating-point immediate)
 ;
 
-define void @splat_imm_v16f16(ptr %a) #0 {
+define void @splat_imm_v16f16(ptr %a) {
 ; CHECK-LABEL: splat_imm_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov z0.h, #5.00000000
@@ -358,7 +359,7 @@ define void @splat_imm_v16f16(ptr %a) #0 {
   ret void
 }
 
-define void @splat_imm_v8f32(ptr %a) #0 {
+define void @splat_imm_v8f32(ptr %a) {
 ; CHECK-LABEL: splat_imm_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov z0.s, #6.00000000
@@ -370,7 +371,7 @@ define void @splat_imm_v8f32(ptr %a) #0 {
   ret void
 }
 
-define void @splat_imm_v4f64(ptr %a) #0 {
+define void @splat_imm_v4f64(ptr %a) {
 ; CHECK-LABEL: splat_imm_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov z0.d, #7.00000000
@@ -381,5 +382,3 @@ define void @splat_imm_v4f64(ptr %a) #0 {
   store <4 x double> %splat, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
index 55ecec520f38f..3ba311693479f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @store_v4i8(ptr %a) #0 {
+define void @store_v4i8(ptr %a) {
 ; CHECK-LABEL: store_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -14,7 +15,7 @@ define void @store_v4i8(ptr %a) #0 {
   ret void
 }
 
-define void @store_v8i8(ptr %a) #0 {
+define void @store_v8i8(ptr %a) {
 ; CHECK-LABEL: store_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, #0 // =0x0
@@ -24,7 +25,7 @@ define void @store_v8i8(ptr %a) #0 {
   ret void
 }
 
-define void @store_v16i8(ptr %a) #0 {
+define void @store_v16i8(ptr %a) {
 ; CHECK-LABEL: store_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, #0 // =0x0
@@ -34,7 +35,7 @@ define void @store_v16i8(ptr %a) #0 {
   ret void
 }
 
-define void @store_v32i8(ptr %a) #0 {
+define void @store_v32i8(ptr %a) {
 ; CHECK-LABEL: store_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.b, #0 // =0x0
@@ -44,7 +45,7 @@ define void @store_v32i8(ptr %a) #0 {
   ret void
 }
 
-define void @store_v2i16(ptr %a) #0 {
+define void @store_v2i16(ptr %a) {
 ; CHECK-LABEL: store_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl2
@@ -55,7 +56,7 @@ define void @store_v2i16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v2f16(ptr %a) #0 {
+define void @store_v2f16(ptr %a) {
 ; CHECK-LABEL: store_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -66,7 +67,7 @@ define void @store_v2f16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v4i16(ptr %a) #0 {
+define void @store_v4i16(ptr %a) {
 ; CHECK-LABEL: store_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -76,7 +77,7 @@ define void @store_v4i16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v4f16(ptr %a) #0 {
+define void @store_v4f16(ptr %a) {
 ; CHECK-LABEL: store_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -86,7 +87,7 @@ define void @store_v4f16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v8i16(ptr %a) #0 {
+define void @store_v8i16(ptr %a) {
 ; CHECK-LABEL: store_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -96,7 +97,7 @@ define void @store_v8i16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v8f16(ptr %a) #0 {
+define void @store_v8f16(ptr %a) {
 ; CHECK-LABEL: store_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -106,7 +107,7 @@ define void @store_v8f16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v16i16(ptr %a) #0 {
+define void @store_v16i16(ptr %a) {
 ; CHECK-LABEL: store_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -116,7 +117,7 @@ define void @store_v16i16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v16f16(ptr %a) #0 {
+define void @store_v16f16(ptr %a) {
 ; CHECK-LABEL: store_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.h, #0 // =0x0
@@ -126,7 +127,7 @@ define void @store_v16f16(ptr %a) #0 {
   ret void
 }
 
-define void @store_v2i32(ptr %a) #0 {
+define void @store_v2i32(ptr %a) {
 ; CHECK-LABEL: store_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str xzr, [x0]
@@ -135,7 +136,7 @@ define void @store_v2i32(ptr %a) #0 {
   ret void
 }
 
-define void @store_v2f32(ptr %a) #0 {
+define void @store_v2f32(ptr %a) {
 ; CHECK-LABEL: store_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str xzr, [x0]
@@ -144,7 +145,7 @@ define void @store_v2f32(ptr %a) #0 {
   ret void
 }
 
-define void @store_v4i32(ptr %a) #0 {
+define void @store_v4i32(ptr %a) {
 ; CHECK-LABEL: store_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp xzr, xzr, [x0]
@@ -153,7 +154,7 @@ define void @store_v4i32(ptr %a) #0 {
   ret void
 }
 
-define void @store_v4f32(ptr %a) #0 {
+define void @store_v4f32(ptr %a) {
 ; CHECK-LABEL: store_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp xzr, xzr, [x0]
@@ -162,7 +163,7 @@ define void @store_v4f32(ptr %a) #0 {
   ret void
 }
 
-define void @store_v8i32(ptr %a) #0 {
+define void @store_v8i32(ptr %a) {
 ; CHECK-LABEL: store_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, #0 // =0x0
@@ -172,7 +173,7 @@ define void @store_v8i32(ptr %a) #0 {
   ret void
 }
 
-define void @store_v8f32(ptr %a) #0 {
+define void @store_v8f32(ptr %a) {
 ; CHECK-LABEL: store_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.s, #0 // =0x0
@@ -182,7 +183,7 @@ define void @store_v8f32(ptr %a) #0 {
   ret void
 }
 
-define void @store_v1i64(ptr %a) #0 {
+define void @store_v1i64(ptr %a) {
 ; CHECK-LABEL: store_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #0 // =0x0
@@ -192,7 +193,7 @@ define void @store_v1i64(ptr %a) #0 {
   ret void
 }
 
-define void @store_v1f64(ptr %a) #0 {
+define void @store_v1f64(ptr %a) {
 ; CHECK-LABEL: store_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov d0, xzr
@@ -202,7 +203,7 @@ define void @store_v1f64(ptr %a) #0 {
   ret void
 }
 
-define void @store_v2i64(ptr %a) #0 {
+define void @store_v2i64(ptr %a) {
 ; CHECK-LABEL: store_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp xzr, xzr, [x0]
@@ -211,7 +212,7 @@ define void @store_v2i64(ptr %a) #0 {
   ret void
 }
 
-define void @store_v2f64(ptr %a) #0 {
+define void @store_v2f64(ptr %a) {
 ; CHECK-LABEL: store_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp xzr, xzr, [x0]
@@ -220,7 +221,7 @@ define void @store_v2f64(ptr %a) #0 {
   ret void
 }
 
-define void @store_v4i64(ptr %a) #0 {
+define void @store_v4i64(ptr %a) {
 ; CHECK-LABEL: store_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #0 // =0x0
@@ -230,7 +231,7 @@ define void @store_v4i64(ptr %a) #0 {
   ret void
 }
 
-define void @store_v4f64(ptr %a) #0 {
+define void @store_v4f64(ptr %a) {
 ; CHECK-LABEL: store_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #0 // =0x0
@@ -239,5 +240,3 @@ define void @store_v4f64(ptr %a) #0 {
   store <4 x double> zeroinitializer, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll
index 6a283a62792f3..b8a7031c546d5 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 ; Test we can code generater patterns of the form:
 ;   fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
@@ -14,7 +15,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux-gnu"
 
 ; i8
-define void @subvector_v4i8(ptr %in, ptr %out) #0 {
+define void @subvector_v4i8(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4i8:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ptrue p0.h, vl4
@@ -29,7 +30,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v8i8(ptr %in, ptr %out) #0 {
+define void @subvector_v8i8(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v8i8:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -43,7 +44,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v16i8(ptr %in, ptr %out) #0 {
+define void @subvector_v16i8(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v16i8:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -57,7 +58,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v32i8(ptr %in, ptr %out) #0 {
+define void @subvector_v32i8(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v32i8:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -72,7 +73,7 @@ bb1:
 }
 
 ; i16
-define void @subvector_v2i16(ptr %in, ptr %out) #0 {
+define void @subvector_v2i16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v2i16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -94,7 +95,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v4i16(ptr %in, ptr %out) #0 {
+define void @subvector_v4i16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4i16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -108,7 +109,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v8i16(ptr %in, ptr %out) #0 {
+define void @subvector_v8i16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v8i16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -122,7 +123,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v16i16(ptr %in, ptr %out) #0 {
+define void @subvector_v16i16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v16i16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -137,7 +138,7 @@ bb1:
 }
 
 ; i32
-define void @subvector_v2i32(ptr %in, ptr %out) #0 {
+define void @subvector_v2i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v2i32:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -151,7 +152,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v4i32(ptr %in, ptr %out) #0 {
+define void @subvector_v4i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4i32:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -165,7 +166,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v8i32(ptr %in, ptr %out) #0 {
+define void @subvector_v8i32(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v8i32:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -180,7 +181,7 @@ bb1:
 }
 
 ; i64
-define void @subvector_v2i64(ptr %in, ptr %out) #0 {
+define void @subvector_v2i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v2i64:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -194,7 +195,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v4i64(ptr %in, ptr %out) #0 {
+define void @subvector_v4i64(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4i64:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -209,7 +210,7 @@ bb1:
 }
 
 ; f16
-define void @subvector_v2f16(ptr %in, ptr %out) #0 {
+define void @subvector_v2f16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v2f16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr w8, [x0]
@@ -223,7 +224,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v4f16(ptr %in, ptr %out) #0 {
+define void @subvector_v4f16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4f16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -237,7 +238,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v8f16(ptr %in, ptr %out) #0 {
+define void @subvector_v8f16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v8f16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -251,7 +252,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v16f16(ptr %in, ptr %out) #0 {
+define void @subvector_v16f16(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v16f16:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -266,7 +267,7 @@ bb1:
 }
 
 ; f32
-define void @subvector_v2f32(ptr %in, ptr %out) #0 {
+define void @subvector_v2f32(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v2f32:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr d0, [x0]
@@ -280,7 +281,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v4f32(ptr %in, ptr %out) #0 {
+define void @subvector_v4f32(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4f32:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -294,7 +295,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v8f32(ptr %in, ptr %out) #0 {
+define void @subvector_v8f32(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v8f32:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -309,7 +310,7 @@ bb1:
 }
 
 ; f64
-define void @subvector_v2f64(ptr %in, ptr %out) #0 {
+define void @subvector_v2f64(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v2f64:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -323,7 +324,7 @@ bb1:
   ret void
 }
 
-define void @subvector_v4f64(ptr %in, ptr %out) #0 {
+define void @subvector_v4f64(ptr %in, ptr %out) {
 ; CHECK-LABEL: subvector_v4f64:
 ; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -336,5 +337,3 @@ bb1:
   store <4 x double> %a, ptr %out
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
index f084d01f99d71..49492b428ddef 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define void @store_trunc_v8i16i8(ptr %ap, ptr %dest) #0 {
+define void @store_trunc_v8i16i8(ptr %ap, ptr %dest) {
 ; CHECK-LABEL: store_trunc_v8i16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -16,7 +17,7 @@ define void @store_trunc_v8i16i8(ptr %ap, ptr %dest) #0 {
   ret void
 }
 
-define void @store_trunc_v4i32i8(ptr %ap, ptr %dest) #0 {
+define void @store_trunc_v4i32i8(ptr %ap, ptr %dest) {
 ; CHECK-LABEL: store_trunc_v4i32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -29,7 +30,7 @@ define void @store_trunc_v4i32i8(ptr %ap, ptr %dest) #0 {
   ret void
 }
 
-define void @store_trunc_v4i32i16(ptr %ap, ptr %dest) #0 {
+define void @store_trunc_v4i32i16(ptr %ap, ptr %dest) {
 ; CHECK-LABEL: store_trunc_v4i32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -42,7 +43,7 @@ define void @store_trunc_v4i32i16(ptr %ap, ptr %dest) #0 {
   ret void
 }
 
-define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) #0 {
+define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) {
 ; CHECK-LABEL: store_trunc_v2i64i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
@@ -55,7 +56,7 @@ define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) #0 {
   ret void
 }
 
-define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) #0 {
+define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) {
 ; CHECK-LABEL: store_trunc_v2i256i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0, #32]
@@ -69,5 +70,3 @@ define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) #0 {
   store <2 x i64> %val, ptr %dest
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
index 4200605c66350..ef992f0736fee 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -7,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu"
 ; truncate i16 -> i8
 ;
 
-define <16 x i8> @trunc_v16i16_v16i8(ptr %in) #0 {
+define <16 x i8> @trunc_v16i16_v16i8(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v16i16_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -23,7 +24,7 @@ define <16 x i8> @trunc_v16i16_v16i8(ptr %in) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v32i16_v32i8(ptr %in, ptr %out) #0 {
+define void @trunc_v32i16_v32i8(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v32i16_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -47,7 +48,7 @@ define void @trunc_v32i16_v32i8(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v64i16_v64i8(ptr %in, ptr %out) #0 {
+define void @trunc_v64i16_v64i8(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v64i16_v64i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #64]
@@ -82,7 +83,7 @@ define void @trunc_v64i16_v64i8(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v128i16_v128i8(ptr %in, ptr %out) #0 {
+define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v128i16_v128i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #192]
@@ -142,7 +143,7 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) #0 {
 ; truncate i32 -> i8
 ;
 
-define <8 x i8> @trunc_v8i32_v8i8(ptr %in) #0 {
+define <8 x i8> @trunc_v8i32_v8i8(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v8i32_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -158,7 +159,7 @@ define <8 x i8> @trunc_v8i32_v8i8(ptr %in) #0 {
   ret <8 x i8> %b
 }
 
-define <16 x i8> @trunc_v16i32_v16i8(ptr %in) #0 {
+define <16 x i8> @trunc_v16i32_v16i8(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v16i32_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -182,7 +183,7 @@ define <16 x i8> @trunc_v16i32_v16i8(ptr %in) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v32i32_v32i8(ptr %in, ptr %out) #0 {
+define void @trunc_v32i32_v32i8(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v32i32_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #96]
@@ -221,7 +222,7 @@ define void @trunc_v32i32_v32i8(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v64i32_v64i8(ptr %in, ptr %out) #0 {
+define void @trunc_v64i32_v64i8(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v64i32_v64i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #128]
@@ -288,7 +289,7 @@ define void @trunc_v64i32_v64i8(ptr %in, ptr %out) #0 {
 ; truncate i32 -> i16
 ;
 
-define <8 x i16> @trunc_v8i32_v8i16(ptr %in) #0 {
+define <8 x i16> @trunc_v8i32_v8i16(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v8i32_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -304,7 +305,7 @@ define <8 x i16> @trunc_v8i32_v8i16(ptr %in) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v16i32_v16i16(ptr %in, ptr %out) #0 {
+define void @trunc_v16i32_v16i16(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v16i32_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -328,7 +329,7 @@ define void @trunc_v16i32_v16i16(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v32i32_v32i16(ptr %in, ptr %out) #0 {
+define void @trunc_v32i32_v32i16(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v32i32_v32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #64]
@@ -363,7 +364,7 @@ define void @trunc_v32i32_v32i16(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v64i32_v64i16(ptr %in, ptr %out) #0 {
+define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v64i32_v64i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #192]
@@ -424,7 +425,7 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) #0 {
 ;
 
 ; NOTE: v4i8 is not legal so result i8 elements are held within i16 containers.
-define <4 x i8> @trunc_v4i64_v4i8(ptr %in) #0 {
+define <4 x i8> @trunc_v4i64_v4i8(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v4i64_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -440,7 +441,7 @@ define <4 x i8> @trunc_v4i64_v4i8(ptr %in) #0 {
   ret <4 x i8> %b
 }
 
-define <8 x i8> @trunc_v8i64_v8i8(ptr %in) #0 {
+define <8 x i8> @trunc_v8i64_v8i8(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v8i64_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -464,7 +465,7 @@ define <8 x i8> @trunc_v8i64_v8i8(ptr %in) #0 {
   ret <8 x i8> %b
 }
 
-define <16 x i8> @trunc_v16i64_v16i8(ptr %in) #0 {
+define <16 x i8> @trunc_v16i64_v16i8(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v16i64_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #96]
@@ -503,7 +504,7 @@ define <16 x i8> @trunc_v16i64_v16i8(ptr %in) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v32i64_v32i8(ptr %in, ptr %out) #0 {
+define void @trunc_v32i64_v32i8(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v32i64_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #224]
@@ -574,7 +575,7 @@ define void @trunc_v32i64_v32i8(ptr %in, ptr %out) #0 {
 ; truncate i64 -> i16
 ;
 
-define <4 x i16> @trunc_v4i64_v4i16(ptr %in) #0 {
+define <4 x i16> @trunc_v4i64_v4i16(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v4i64_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -590,7 +591,7 @@ define <4 x i16> @trunc_v4i64_v4i16(ptr %in) #0 {
   ret <4 x i16> %b
 }
 
-define <8 x i16> @trunc_v8i64_v8i16(ptr %in) #0 {
+define <8 x i16> @trunc_v8i64_v8i16(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v8i64_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -614,7 +615,7 @@ define <8 x i16> @trunc_v8i64_v8i16(ptr %in) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v16i64_v16i16(ptr %in, ptr %out) #0 {
+define void @trunc_v16i64_v16i16(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v16i64_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #96]
@@ -653,7 +654,7 @@ define void @trunc_v16i64_v16i16(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v32i64_v32i16(ptr %in, ptr %out) #0 {
+define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v32i64_v32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #128]
@@ -720,7 +721,7 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) #0 {
 ; truncate i64 -> i32
 ;
 
-define <4 x i32> @trunc_v4i64_v4i32(ptr %in) #0 {
+define <4 x i32> @trunc_v4i64_v4i32(ptr %in) nounwind {
 ; CHECK-LABEL: trunc_v4i64_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0]
@@ -736,7 +737,7 @@ define <4 x i32> @trunc_v4i64_v4i32(ptr %in) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v8i64_v8i32(ptr %in, ptr %out) #0 {
+define void @trunc_v8i64_v8i32(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v8i64_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #32]
@@ -760,7 +761,7 @@ define void @trunc_v8i64_v8i32(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v16i64_v16i32(ptr %in, ptr %out) #0 {
+define void @trunc_v16i64_v16i32(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v16i64_v16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #64]
@@ -795,7 +796,7 @@ define void @trunc_v16i64_v16i32(ptr %in, ptr %out) #0 {
 }
 
 ; NOTE: Extra 'add' is to prevent the truncate being combined with the store.
-define void @trunc_v32i64_v32i32(ptr %in, ptr %out) #0 {
+define void @trunc_v32i64_v32i32(ptr %in, ptr %out) nounwind {
 ; CHECK-LABEL: trunc_v32i64_v32i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x0, #192]
@@ -850,5 +851,3 @@ define void @trunc_v32i64_v32i32(ptr %in, ptr %out) #0 {
   store <32 x i32> %c, ptr %out
   ret void
 }
-
-attributes #0 = { nounwind "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
index c067b35a3396f..dc0e49fafcea7 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
-define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
+define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
@@ -27,7 +28,7 @@ define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
   ret <4 x i8> %ret
 }
 
-define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -41,7 +42,7 @@ define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
   ret <8 x i8> %ret
 }
 
-define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -56,7 +57,7 @@ define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
   ret <16 x i8> %ret
 }
 
-define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -80,7 +81,7 @@ define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i16> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
+define <2 x i16> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -92,7 +93,7 @@ define <2 x i16> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
   ret <2 x i16> %ret
 }
 
-define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -106,7 +107,7 @@ define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
   ret <4 x i16> %ret
 }
 
-define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -120,7 +121,7 @@ define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
   ret <8 x i16> %ret
 }
 
-define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -142,7 +143,7 @@ define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+define <2 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -156,7 +157,7 @@ define <2 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
   ret <2 x i32> %ret
 }
 
-define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -170,7 +171,7 @@ define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
   ret <4 x i32> %ret
 }
 
-define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -191,7 +192,7 @@ define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -205,7 +206,7 @@ define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
   ret <2 x i64> %ret
 }
 
-define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -227,7 +228,7 @@ define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) #0 {
 }
 
 
-define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -240,7 +241,7 @@ define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) #0
   ret <4 x half> %ret
 }
 
-define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -253,7 +254,7 @@ define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) #0
   ret <8 x half> %ret
 }
 
-define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x1]
@@ -272,7 +273,7 @@ define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x float> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+define <2 x float> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
@@ -285,7 +286,7 @@ define <2 x float> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2)
   ret <2 x float> %ret
 }
 
-define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -298,7 +299,7 @@ define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2)
   ret <4 x float> %ret
 }
 
-define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x1]
@@ -316,7 +317,7 @@ define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op2) {
 ; CHECK-LABEL: shuffle_ext_byone_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
@@ -329,7 +330,7 @@ define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op
   ret <2 x double> %ret
 }
 
-define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x1]
@@ -347,7 +348,7 @@ define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_byone_reverse:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q2, [x0]
@@ -365,7 +366,7 @@ define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) #0 {
   ret void
 }
 
-define void @shuffle_ext_invalid(ptr %a, ptr %b) #0 {
+define void @shuffle_ext_invalid(ptr %a, ptr %b) {
 ; CHECK-LABEL: shuffle_ext_invalid:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0, #16]
@@ -378,5 +379,3 @@ define void @shuffle_ext_invalid(ptr %a, ptr %b) #0 {
   store <4 x double> %ret, ptr %a
   ret void
 }
-
-attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
index 159a085b05ed0..47a2ae01d2443 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
@@ -1,10 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
+
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; A NEON Q-register mov is not valid in streaming mode, but an SVE Z-register mov is.
-define fp128 @test_streaming_compatible_register_mov(fp128 %q0, fp128 %q1) #0 {
+define fp128 @test_streaming_compatible_register_mov(fp128 %q0, fp128 %q1) {
 ; CHECK-LABEL: test_streaming_compatible_register_mov:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, z1.d
@@ -13,7 +14,7 @@ define fp128 @test_streaming_compatible_register_mov(fp128 %q0, fp128 %q1) #0 {
 }
 
 ; Test that `movi` isn't used (invalid in streaming mode), but fmov or SVE mov instead.
-define double @fp_zero_constant() #0 {
+define double @fp_zero_constant() {
 ; CHECK-LABEL: fp_zero_constant:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov d0, xzr
@@ -21,7 +22,7 @@ define double @fp_zero_constant() #0 {
   ret double 0.0
 }
 
-define <2 x i64> @fixed_vec_zero_constant() #0 {
+define <2 x i64> @fixed_vec_zero_constant() {
 ; CHECK-LABEL: fixed_vec_zero_constant:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #0 // =0x0
@@ -30,7 +31,7 @@ define <2 x i64> @fixed_vec_zero_constant() #0 {
   ret <2 x i64> zeroinitializer
 }
 
-define <2 x double> @fixed_vec_fp_zero_constant() #0 {
+define <2 x double> @fixed_vec_fp_zero_constant() {
 ; CHECK-LABEL: fixed_vec_fp_zero_constant:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z0.d, #0 // =0x0
@@ -38,5 +39,3 @@ define <2 x double> @fixed_vec_fp_zero_constant() #0 {
 ; CHECK-NEXT:    ret
   ret <2 x double> <double 0.0, double 0.0>
 }
-
-attributes #0 = { "target-features"="+sve" }