diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 494e4b52a5b5e..c6db8a7bbeb85 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -45,6 +45,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/InitializePasses.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" using namespace llvm; @@ -95,6 +96,13 @@ static cl::opt cl::desc("enable optimization of conditional traps"), cl::init(false), cl::Hidden); +DEBUG_COUNTER( + PeepholeXToICounter, "ppc-xtoi-peephole", + "Controls whether PPC reg+reg to reg+imm peephole is performed on a MI"); + +DEBUG_COUNTER(PeepholePerOpCounter, "ppc-per-op-peephole", + "Controls whether PPC per opcode peephole is performed on a MI"); + namespace { struct PPCMIPeephole : public MachineFunctionPass { @@ -469,6 +477,9 @@ bool PPCMIPeephole::simplifyCode() { if (MI.isDebugInstr()) continue; + if (!DebugCounter::shouldExecute(PeepholeXToICounter)) + continue; + SmallSet RRToRIRegsToUpdate; if (!TII->convertToImmediateForm(MI, RRToRIRegsToUpdate)) continue; @@ -538,6 +549,9 @@ bool PPCMIPeephole::simplifyCode() { if (MI.isDebugInstr()) continue; + if (!DebugCounter::shouldExecute(PeepholePerOpCounter)) + continue; + // Per-opcode peepholes. switch (MI.getOpcode()) { diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir new file mode 100644 index 0000000000000..d8f2b08adaf2f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir @@ -0,0 +1,85 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# REQUIRES: asserts +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=0,ppc-xtoi-peephole-count=8 \ +# RUN: | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=3,ppc-xtoi-peephole-count=2 \ +# RUN: | FileCheck %s --check-prefix=ONE-FIRSTSTORE +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=5,ppc-xtoi-peephole-count=2 \ +# RUN: | FileCheck %s --check-prefix=ONE-SECONDSTORE +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=3,ppc-xtoi-peephole-count=4 \ +# RUN: | FileCheck %s --check-prefix=TWO + +--- +name: foldDForm +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x3 + + ; ALL-LABEL: name: foldDForm + ; ALL: liveins: $x3 + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; ALL-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; ALL-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; ALL-NEXT: STD [[LI8_]], 160, [[COPY]] + ; ALL-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; ALL-NEXT: STD [[LI8_]], 176, [[COPY]] + ; ALL-NEXT: dead [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176 + ; ALL-NEXT: STD killed [[LI8_]], 192, killed [[COPY]] + ; ALL-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-FIRSTSTORE-LABEL: name: foldDForm + ; ONE-FIRSTSTORE: liveins: $x3 + ; ONE-FIRSTSTORE-NEXT: {{ $}} + ; ONE-FIRSTSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; ONE-FIRSTSTORE-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; ONE-FIRSTSTORE-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 160, [[COPY]] + ; ONE-FIRSTSTORE-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 16, killed [[ADDI8_1]] + ; ONE-FIRSTSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176 + ; ONE-FIRSTSTORE-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]] + ; ONE-FIRSTSTORE-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-SECONDSTORE-LABEL: name: foldDForm + ; ONE-SECONDSTORE: liveins: $x3 + ; ONE-SECONDSTORE-NEXT: {{ $}} + ; ONE-SECONDSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; ONE-SECONDSTORE-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; ONE-SECONDSTORE-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 16, killed [[ADDI8_]] + ; ONE-SECONDSTORE-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 176, [[COPY]] + ; ONE-SECONDSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176 + ; ONE-SECONDSTORE-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]] + ; ONE-SECONDSTORE-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; TWO-LABEL: name: foldDForm + ; TWO: liveins: $x3 + ; TWO-NEXT: {{ $}} + ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; TWO-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; TWO-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; TWO-NEXT: STD [[LI8_]], 160, [[COPY]] + ; TWO-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; TWO-NEXT: STD [[LI8_]], 176, [[COPY]] + ; TWO-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176 + ; TWO-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]] + ; TWO-NEXT: BLR8 implicit $lr8, implicit $rm + %0:g8rc_and_g8rc_nox0 = COPY $x3 + %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144 + %2:g8rc = LI8 0 + STD %2:g8rc, 16, %1:g8rc_and_g8rc_nox0 + %3:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 160 + STD %2:g8rc, 16, %3:g8rc_and_g8rc_nox0 + %4:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 176 + STD killed %2:g8rc, 16, %4:g8rc_and_g8rc_nox0 + BLR8 implicit $lr8, implicit $rm +... diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir new file mode 100644 index 0000000000000..cf3ff291e26c6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir @@ -0,0 +1,74 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# REQUIRES: asserts +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=0,ppc-per-op-peephole-count=6 \ +# RUN: | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=3,ppc-per-op-peephole-count=1 \ +# RUN: | FileCheck %s --check-prefix=ONE-FIRST-RLWINM +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=4,ppc-per-op-peephole-count=1 \ +# RUN: | FileCheck %s --check-prefix=ONE-SECOND-RLWINM +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=3,ppc-per-op-peephole-count=2 \ +# RUN: | FileCheck %s --check-prefix=TWO + +--- +name: testFoldRLWINM +#CHECK: name: testFoldRLWINM +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x3 + ; ALL-LABEL: name: testFoldRLWINM + ; ALL: liveins: $x3 + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; ALL-NEXT: dead [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12 + ; ALL-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 11 + ; ALL-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 10 + ; ALL-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-FIRST-RLWINM-LABEL: name: testFoldRLWINM + ; ONE-FIRST-RLWINM: liveins: $x3 + ; ONE-FIRST-RLWINM-NEXT: {{ $}} + ; ONE-FIRST-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; ONE-FIRST-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; ONE-FIRST-RLWINM-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31 + ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 12 + ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 11 + ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10 + ; ONE-FIRST-RLWINM-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-SECOND-RLWINM-LABEL: name: testFoldRLWINM + ; ONE-SECOND-RLWINM: liveins: $x3 + ; ONE-SECOND-RLWINM-NEXT: {{ $}} + ; ONE-SECOND-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; ONE-SECOND-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; ONE-SECOND-RLWINM-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31 + ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 12 + ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 11 + ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10 + ; ONE-SECOND-RLWINM-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; TWO-LABEL: name: testFoldRLWINM + ; TWO: liveins: $x3 + ; TWO-NEXT: {{ $}} + ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; TWO-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; TWO-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31 + ; TWO-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12 + ; TWO-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 11 + ; TWO-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10 + ; TWO-NEXT: BLR8 implicit $lr8, implicit $rm + %0:g8rc = COPY $x3 + %1:gprc = COPY %0.sub_32:g8rc + %2:gprc = RLWINM %1:gprc, 27, 5, 31 + %3:gprc = RLWINM %2:gprc, 19, 0, 12 + %4:gprc = RLWINM %2:gprc, 19, 0, 11 + %5:gprc = RLWINM %2:gprc, 19, 0, 10 + BLR8 implicit $lr8, implicit $rm +...