diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll new file mode 100644 index 00000000000000..7775789bd0d2f5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll @@ -0,0 +1,1171 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; Denormal mode shouldn't matter for f16, check with and without flushing. +; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-IEEE %s +; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-FLUSH %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8,GFX8-IEEE %s +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8,GFX8-FLUSH %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-IEEE %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-FLUSH %s + +define half @v_fdiv_f16(half %a, half %b) { +; GFX6-IEEE-LABEL: v_fdiv_f16: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_f16: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_fdiv_f16: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX89-NEXT: v_rcp_f32_e32 v2, v2 +; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 +; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv half %a, %b + ret half %fdiv +} + +define half @v_fdiv_f16_afn(half %a, half %b) { +; GFX6-IEEE-LABEL: v_fdiv_f16_afn: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_f16_afn: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_fdiv_f16_afn: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v1, v1 +; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn half %a, %b + ret half %fdiv +} + +define half @v_fdiv_f16_ulp25(half %a, half %b) { +; GFX6-IEEE-LABEL: v_fdiv_f16_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_f16_ulp25: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_fdiv_f16_ulp25: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX89-NEXT: v_rcp_f32_e32 v2, v2 +; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 +; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv half %a, %b, !fpmath !0 + ret half %fdiv +} + +define half @v_rcp_f16(half %x) { +; GFX6-IEEE-LABEL: v_rcp_f16: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_rcp_f16: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_rcp_f16: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v0, v0 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv half 1.0, %x + ret half %fdiv +} + +define half @v_rcp_f16_arcp(half %x) { +; GFX6-LABEL: v_rcp_f16_arcp: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, 1.0 +; GFX6-NEXT: v_rcp_f32_e32 v0, v0 +; GFX6-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_rcp_f16_arcp: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v0, v0 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp half 1.0, %x + ret half %fdiv +} + +define half @v_rcp_f16_arcp_afn(half %x) { +; GFX6-LABEL: v_rcp_f16_arcp_afn: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, 1.0 +; GFX6-NEXT: v_rcp_f32_e32 v0, v0 +; GFX6-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_rcp_f16_arcp_afn: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v0, v0 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp afn half 1.0, %x + ret half %fdiv +} + +define half @v_rcp_f16_ulp25(half %x) { +; GFX6-IEEE-LABEL: v_rcp_f16_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_rcp_f16_ulp25: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_rcp_f16_ulp25: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v0, v0 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv half 1.0, %x, !fpmath !0 + ret half %fdiv +} + +define half @v_fdiv_f16_afn_ulp25(half %a, half %b) { +; GFX6-IEEE-LABEL: v_fdiv_f16_afn_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_f16_afn_ulp25: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_fdiv_f16_afn_ulp25: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v1, v1 +; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn half %a, %b, !fpmath !0 + ret half %fdiv +} + +define half @v_fdiv_f16_arcp_ulp25(half %a, half %b) { +; GFX6-LABEL: v_fdiv_f16_arcp_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_rcp_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-LABEL: v_fdiv_f16_arcp_ulp25: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_rcp_f16_e32 v1, v1 +; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX89-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp half %a, %b, !fpmath !0 + ret half %fdiv +} + +define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { +; GFX6-IEEE-LABEL: v_fdiv_v2f16: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_v2f16: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 +; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX8-NEXT: v_rcp_f32_e32 v2, v2 +; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 +; GFX8-NEXT: v_rcp_f32_e32 v5, v5 +; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 +; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 +; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 +; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 +; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX9-NEXT: v_rcp_f32_e32 v2, v2 +; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 +; GFX9-NEXT: v_rcp_f32_e32 v5, v5 +; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 +; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 +; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x half> %a, %b + ret <2 x half> %fdiv +} + +define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) { +; GFX6-IEEE-LABEL: v_fdiv_v2f16_afn: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_v2f16_afn: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f16_afn: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_e32 v2, v1 +; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v1, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f16_afn: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn <2 x half> %a, %b + ret <2 x half> %fdiv +} + +define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { +; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f16_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 +; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX8-NEXT: v_rcp_f32_e32 v2, v2 +; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 +; GFX8-NEXT: v_rcp_f32_e32 v5, v5 +; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 +; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 +; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f16_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 +; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 +; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX9-NEXT: v_rcp_f32_e32 v2, v2 +; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 +; GFX9-NEXT: v_rcp_f32_e32 v5, v5 +; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 +; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 +; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x half> %a, %b, !fpmath !0 + ret <2 x half> %fdiv +} + +define <2 x half> @v_rcp_v2f16(<2 x half> %x) { +; GFX6-IEEE-LABEL: v_rcp_v2f16: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, 1.0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v1, v2 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, v2 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_rcp_v2f16: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s6 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v4 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v1, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v4 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_rcp_f16_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v1, v0 +; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x half> , %x + ret <2 x half> %fdiv +} + +define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) { +; GFX6-LABEL: v_rcp_v2f16_arcp: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-NEXT: v_cvt_f32_f16_e32 v2, 1.0 +; GFX6-NEXT: v_rcp_f32_e32 v0, v0 +; GFX6-NEXT: v_rcp_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_f32_e32 v0, v2, v0 +; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f16_arcp: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_rcp_f16_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f16_arcp: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v1, v0 +; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp <2 x half> , %x + ret <2 x half> %fdiv +} + +define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) { +; GFX6-LABEL: v_rcp_v2f16_arcp_afn: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-NEXT: v_cvt_f32_f16_e32 v2, 1.0 +; GFX6-NEXT: v_rcp_f32_e32 v0, v0 +; GFX6-NEXT: v_rcp_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_f32_e32 v0, v2, v0 +; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f16_arcp_afn: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_rcp_f16_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f16_arcp_afn: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v1, v0 +; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp afn <2 x half> , %x + ret <2 x half> %fdiv +} + +define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) { +; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, 1.0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v1, v2 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, v2 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s6 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v4 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v1, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v4 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f16_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_rcp_f16_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f16_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v1, v0 +; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x half> , %x, !fpmath !0 + ret <2 x half> %fdiv +} + +define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) { +; GFX6-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_e32 v2, v1 +; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v1, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0 + ret <2 x half> %fdiv +} + +define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) { +; GFX6-LABEL: v_fdiv_v2f16_arcp_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-NEXT: v_rcp_f32_e32 v2, v2 +; GFX6-NEXT: v_rcp_f32_e32 v3, v3 +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_e32 v2, v1 +; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v1, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f16_arcp_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp <2 x half> %a, %b, !fpmath !0 + ret <2 x half> %fdiv +} + +define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) { +; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX6-NEXT: v_rcp_f32_e32 v2, v2 +; GFX6-NEXT: v_rcp_f32_e32 v3, v3 +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_rcp_f16_e32 v2, v1 +; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v1, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn arcp <2 x half> %a, %b, !fpmath !0 + ret <2 x half> %fdiv +} + +!0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll new file mode 100644 index 00000000000000..02114a058c8910 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll @@ -0,0 +1,651 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6,GFX6-IEEE %s +; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6,GFX6-FLUSH %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE,GFX89,GFX8,GFX8-IEEE %s +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89,GFX89-FLUSH,GFX8,GFX8-FLUSH %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89,GFX89-IEEE,GFX9,GFX9-IEEE %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89,GFX89-FLUSH,GFX9,GFX9-FLUSH %s + +define float @v_fdiv_f32(float %a, float %b) { +; GFX6-IEEE-LABEL: v_fdiv_f32: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_f32: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-IEEE-LABEL: v_fdiv_f32: +; GFX89-IEEE: ; %bb.0: +; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2 +; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4 +; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3 +; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5 +; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3 +; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-FLUSH-LABEL: v_fdiv_f32: +; GFX89-FLUSH: ; %bb.0: +; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 +; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 +; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0 +; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4 +; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4 +; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3 +; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5 +; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3 +; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5 +; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv float %a, %b + ret float %fdiv +} + +define float @v_fdiv_f32_afn(float %a, float %b) { +; GCN-LABEL: v_fdiv_f32_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn float %a, %b + ret float %fdiv +} + +define float @v_fdiv_f32_ulp25(float %a, float %b) { +; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_fdiv_f32_ulp25: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: v_mov_b32_e32 v2, 0x6f800000 +; GCN-FLUSH-NEXT: v_mov_b32_e32 v3, 0x2f800000 +; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, v2 +; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-IEEE-LABEL: v_fdiv_f32_ulp25: +; GFX89-IEEE: ; %bb.0: +; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2 +; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4 +; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3 +; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5 +; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3 +; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv float %a, %b, !fpmath !0 + ret float %fdiv +} + +define float @v_rcp_f32(float %x) { +; GFX6-IEEE-LABEL: v_rcp_f32: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1 +; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_rcp_f32: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-IEEE-LABEL: v_rcp_f32: +; GFX89-IEEE: ; %bb.0: +; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v3, v1 +; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3 +; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2 +; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4 +; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2 +; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 +; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv float 1.0, %x + ret float %fdiv +} + +define float @v_rcp_f32_arcp(float %x) { +; GCN-LABEL: v_rcp_f32_arcp: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp float 1.0, %x + ret float %fdiv +} + +define float @v_rcp_f32_arcp_afn(float %x) { +; GCN-LABEL: v_rcp_f32_arcp_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp afn float 1.0, %x + ret float %fdiv +} + +define float @v_rcp_f32_ulp25(float %x) { +; GCN-IEEE-LABEL: v_rcp_f32_ulp25: +; GCN-IEEE: ; %bb.0: +; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-IEEE-NEXT: v_mov_b32_e32 v1, 0x6f800000 +; GCN-IEEE-NEXT: v_mov_b32_e32 v2, 0x2f800000 +; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v1 +; GCN-IEEE-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-IEEE-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, v1, v0 +; GCN-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_rcp_f32_ulp25: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv float 1.0, %x, !fpmath !0 + ret float %fdiv +} + +define float @v_fdiv_f32_afn_ulp25(float %a, float %b) { +; GCN-LABEL: v_fdiv_f32_afn_ulp25: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn float %a, %b, !fpmath !0 + ret float %fdiv +} + +define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) { +; GCN-IEEE-LABEL: v_fdiv_f32_arcp_ulp25: +; GCN-IEEE: ; %bb.0: +; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-IEEE-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: v_mov_b32_e32 v2, 0x6f800000 +; GCN-FLUSH-NEXT: v_mov_b32_e32 v3, 0x2f800000 +; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, v2 +; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp float %a, %b, !fpmath !0 + ret float %fdiv +} + +define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) { +; GFX6-IEEE-LABEL: v_fdiv_v2f32: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v2 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v6, v2 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-FLUSH-LABEL: v_fdiv_v2f32: +; GFX6-FLUSH: ; %bb.0: +; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v6, v5 +; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v5, v6, 1.0 +; GFX6-FLUSH-NEXT: v_fma_f32 v4, v4, v6, v6 +; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v2, v4 +; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v5, v6, v2 +; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v5, v6, v2 +; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-IEEE-LABEL: v_fdiv_v2f32: +; GFX89-IEEE: ; %bb.0: +; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1 +; GFX89-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v4 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v9, v5 +; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v11, -v5, v9, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v8, v8 +; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v9, v9 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v10, v6, v8 +; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v6 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v11, v7, v9 +; GFX89-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v7 +; GFX89-IEEE-NEXT: v_fma_f32 v10, v12, v8, v10 +; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v6 +; GFX89-IEEE-NEXT: v_fma_f32 v11, v13, v9, v11 +; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v10 +; GFX89-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v7 +; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5] +; GFX89-IEEE-NEXT: v_div_fmas_f32 v5, v5, v9, v11 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 +; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-FLUSH-LABEL: v_fdiv_v2f32: +; GFX89-FLUSH: ; %bb.0: +; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX89-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v2, v0 +; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v6, v4 +; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v4, v6, 1.0 +; GFX89-FLUSH-NEXT: v_fma_f32 v6, v7, v6, v6 +; GFX89-FLUSH-NEXT: v_mul_f32_e32 v7, v5, v6 +; GFX89-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v5 +; GFX89-FLUSH-NEXT: v_fma_f32 v7, v8, v6, v7 +; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v5 +; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX89-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v6, v7 +; GFX89-FLUSH-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1 +; GFX89-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v1, v3, v1 +; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v7, v5 +; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v5, v7, 1.0 +; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v7, v7 +; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v2 +; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v5, v4, v6 +; GFX89-FLUSH-NEXT: v_fma_f32 v4, v7, v2, v4 +; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v5, v4, v6 +; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v5, v2, v4 +; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x float> %a, %b + ret <2 x float> %fdiv +} + +define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) { +; GCN-LABEL: v_fdiv_v2f32_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn <2 x float> %a, %b + ret <2 x float> %fdiv +} + +define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) { +; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 +; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 +; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1 +; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v2 +; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v6, v2 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: s_mov_b32 s4, 0x6f800000 +; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x2f800000 +; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, s4 +; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc +; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, s4 +; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc +; GCN-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v5 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v4 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v5, v0 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-IEEE-LABEL: v_fdiv_v2f32_ulp25: +; GFX89-IEEE: ; %bb.0: +; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1 +; GFX89-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v4 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v9, v5 +; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v11, -v5, v9, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v8, v8 +; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v9, v9 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v10, v6, v8 +; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v6 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v11, v7, v9 +; GFX89-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v7 +; GFX89-IEEE-NEXT: v_fma_f32 v10, v12, v8, v10 +; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v6 +; GFX89-IEEE-NEXT: v_fma_f32 v11, v13, v9, v11 +; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v10 +; GFX89-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v7 +; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5] +; GFX89-IEEE-NEXT: v_div_fmas_f32 v5, v5, v9, v11 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1 +; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x float> %a, %b, !fpmath !0 + ret <2 x float> %fdiv +} + +define <2 x float> @v_rcp_v2f32(<2 x float> %x) { +; GFX6-IEEE-LABEL: v_rcp_v2f32: +; GFX6-IEEE: ; %bb.0: +; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 +; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0 +; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0 +; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0 +; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4 +; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4 +; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2 +; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5 +; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2 +; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5 +; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0 +; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_rcp_v2f32: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX89-IEEE-LABEL: v_rcp_v2f32: +; GFX89-IEEE: ; %bb.0: +; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0 +; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v6, v2 +; GFX89-IEEE-NEXT: v_rcp_f32_e32 v7, v3 +; GFX89-IEEE-NEXT: v_fma_f32 v8, -v2, v6, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v9, -v3, v7, 1.0 +; GFX89-IEEE-NEXT: v_fma_f32 v6, v8, v6, v6 +; GFX89-IEEE-NEXT: v_fma_f32 v7, v9, v7, v7 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v6 +; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v4 +; GFX89-IEEE-NEXT: v_mul_f32_e32 v9, v5, v7 +; GFX89-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v5 +; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v6, v8 +; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v4 +; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v7, v9 +; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v6, v8 +; GFX89-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v5 +; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5] +; GFX89-IEEE-NEXT: v_div_fmas_f32 v3, v3, v7, v9 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0 +; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0 +; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x float> , %x + ret <2 x float> %fdiv +} + +define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) { +; GCN-LABEL: v_rcp_v2f32_arcp: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp <2 x float> , %x + ret <2 x float> %fdiv +} + +define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) { +; GCN-LABEL: v_rcp_v2f32_arcp_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp afn <2 x float> , %x + ret <2 x float> %fdiv +} + +define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) { +; GCN-IEEE-LABEL: v_rcp_v2f32_ulp25: +; GCN-IEEE: ; %bb.0: +; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-IEEE-NEXT: s_mov_b32 s4, 0x6f800000 +; GCN-IEEE-NEXT: v_mov_b32_e32 v2, 0x2f800000 +; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4 +; GCN-IEEE-NEXT: v_cndmask_b32_e32 v3, 1.0, v2, vcc +; GCN-IEEE-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4 +; GCN-IEEE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, v0, v3 +; GCN-IEEE-NEXT: v_mul_f32_e32 v1, v1, v2 +; GCN-IEEE-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-IEEE-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-IEEE-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, v3, v0 +; GCN-IEEE-NEXT: v_mul_f32_e32 v1, v2, v1 +; GCN-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_rcp_v2f32_ulp25: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x float> , %x, !fpmath !0 + ret <2 x float> %fdiv +} + +define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) { +; GCN-LABEL: v_fdiv_v2f32_afn_ulp25: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn <2 x float> %a, %b, !fpmath !0 + ret <2 x float> %fdiv +} + +define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) { +; GCN-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25: +; GCN-IEEE: ; %bb.0: +; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-IEEE-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-IEEE-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-IEEE-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-IEEE-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25: +; GCN-FLUSH: ; %bb.0: +; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FLUSH-NEXT: s_mov_b32 s4, 0x6f800000 +; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x2f800000 +; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, s4 +; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc +; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, s4 +; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc +; GCN-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v5 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v4 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v5, v0 +; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1 +; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0 + ret <2 x float> %fdiv +} + +define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) { +; GCN-LABEL: v_fdiv_v2f32_arcp_afn_ulp25: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v1, v3 +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn arcp <2 x float> %a, %b, !fpmath !0 + ret <2 x float> %fdiv +} + +!0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll new file mode 100644 index 00000000000000..4216892e1dd56a --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll @@ -0,0 +1,990 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +define double @v_fdiv_f64(double %a, double %b) { +; GFX6-LABEL: v_fdiv_f64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX6-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[0:1], v[2:3], v[0:1] +; GFX6-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v11 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v5 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] +; GFX6-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] +; GFX6-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_f64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX8-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX8-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX8-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1] +; GFX8-NEXT: v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0 +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] +; GFX8-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7] +; GFX8-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] +; GFX8-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX9-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX9-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX9-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1] +; GFX9-NEXT: v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0 +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] +; GFX9-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7] +; GFX9-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] +; GFX9-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv double %a, %b + ret double %fdiv +} + +define double @v_fdiv_f64_afn(double %a, double %b) { +; GCN-LABEL: v_fdiv_f64_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[2:3] +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn double %a, %b + ret double %fdiv +} + +define double @v_fdiv_f64_ulp25(double %a, double %b) { +; GFX6-LABEL: v_fdiv_f64_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX6-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[0:1], v[2:3], v[0:1] +; GFX6-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v11 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v5 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] +; GFX6-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] +; GFX6-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_f64_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX8-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX8-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX8-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1] +; GFX8-NEXT: v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0 +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] +; GFX8-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7] +; GFX8-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] +; GFX8-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_f64_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX9-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX9-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX9-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1] +; GFX9-NEXT: v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0 +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] +; GFX9-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7] +; GFX9-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] +; GFX9-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv double %a, %b, !fpmath !0 + ret double %fdiv +} + +define double @v_rcp_f64(double %x) { +; GFX6-LABEL: v_rcp_f64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], 1.0, v[0:1], 1.0 +; GFX6-NEXT: v_mov_b32_e32 v10, 0x3ff00000 +; GFX6-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v10, v9 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v3 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX6-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX6-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; GFX6-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] +; GFX6-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_f64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX8-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX8-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX8-NEXT: v_div_scale_f64 v[6:7], vcc, 1.0, v[0:1], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0 +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] +; GFX8-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5] +; GFX8-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7] +; GFX8-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX9-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX9-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX9-NEXT: v_div_scale_f64 v[6:7], vcc, 1.0, v[0:1], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0 +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] +; GFX9-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5] +; GFX9-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7] +; GFX9-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv double 1.0, %x + ret double %fdiv +} + +define double @v_rcp_f64_arcp(double %x) { +; GFX6-LABEL: v_rcp_f64_arcp: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], 1.0, v[0:1], 1.0 +; GFX6-NEXT: v_mov_b32_e32 v10, 0x3ff00000 +; GFX6-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v10, v9 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v3 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX6-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX6-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; GFX6-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] +; GFX6-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_f64_arcp: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX8-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX8-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX8-NEXT: v_div_scale_f64 v[6:7], vcc, 1.0, v[0:1], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0 +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] +; GFX8-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5] +; GFX8-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7] +; GFX8-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_f64_arcp: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX9-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX9-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX9-NEXT: v_div_scale_f64 v[6:7], vcc, 1.0, v[0:1], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0 +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] +; GFX9-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5] +; GFX9-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7] +; GFX9-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp double 1.0, %x + ret double %fdiv +} + +define double @v_rcp_f64_arcp_afn(double %x) { +; GCN-LABEL: v_rcp_f64_arcp_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[0:1], v[0:1] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp afn double 1.0, %x + ret double %fdiv +} + +define double @v_rcp_f64_ulp25(double %x) { +; GFX6-LABEL: v_rcp_f64_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], 1.0, v[0:1], 1.0 +; GFX6-NEXT: v_mov_b32_e32 v10, 0x3ff00000 +; GFX6-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v10, v9 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v3 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX6-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX6-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; GFX6-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] +; GFX6-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_f64_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX8-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX8-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX8-NEXT: v_div_scale_f64 v[6:7], vcc, 1.0, v[0:1], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0 +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] +; GFX8-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5] +; GFX8-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7] +; GFX8-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_f64_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0 +; GFX9-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; GFX9-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; GFX9-NEXT: v_div_scale_f64 v[6:7], vcc, 1.0, v[0:1], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0 +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] +; GFX9-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5] +; GFX9-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7] +; GFX9-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv double 1.0, %x, !fpmath !0 + ret double %fdiv +} + +define double @v_fdiv_f64_afn_ulp25(double %a, double %b) { +; GCN-LABEL: v_fdiv_f64_afn_ulp25: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[2:3] +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn double %a, %b, !fpmath !0 + ret double %fdiv +} + +define double @v_fdiv_f64_arcp_ulp25(double %a, double %b) { +; GFX6-LABEL: v_fdiv_f64_arcp_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX6-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[0:1], v[2:3], v[0:1] +; GFX6-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v11 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v5 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] +; GFX6-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] +; GFX6-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_f64_arcp_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX8-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX8-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX8-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1] +; GFX8-NEXT: v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0 +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] +; GFX8-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7] +; GFX8-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] +; GFX8-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_f64_arcp_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1] +; GFX9-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX9-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX9-NEXT: v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1] +; GFX9-NEXT: v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0 +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] +; GFX9-NEXT: v_mul_f64 v[10:11], v[8:9], v[6:7] +; GFX9-NEXT: v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] +; GFX9-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp double %a, %b, !fpmath !0 + ret double %fdiv +} + +define <2 x double> @v_fdiv_v2f64(<2 x double> %a, <2 x double> %b) { +; GFX6-LABEL: v_fdiv_v2f64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX6-NEXT: v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX6-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1] +; GFX6-NEXT: v_rcp_f64_e32 v[10:11], v[8:9] +; GFX6-NEXT: v_rcp_f64_e32 v[16:17], v[14:15] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v19 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v9 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v15 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 +; GFX6-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; GFX6-NEXT: v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0 +; GFX6-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17] +; GFX6-NEXT: v_mul_f64 v[16:17], v[18:19], v[10:11] +; GFX6-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17] +; GFX6-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13] +; GFX6-NEXT: v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1] +; GFX6-NEXT: v_mul_f64 v[16:17], v[12:13], v[8:9] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v13 +; GFX6-NEXT: v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: s_nop 1 +; GFX6-NEXT: v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17] +; GFX6-NEXT: v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3] +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX8-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX8-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX8-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX8-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 +; GFX8-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX8-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] +; GFX8-NEXT: v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX8-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] +; GFX8-NEXT: v_mul_f64 v[16:17], v[18:19], v[12:13] +; GFX8-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19] +; GFX8-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3] +; GFX8-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17] +; GFX8-NEXT: s_mov_b64 vcc, s[4:5] +; GFX8-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] +; GFX8-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19] +; GFX8-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21] +; GFX8-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX9-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX9-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX9-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX9-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 +; GFX9-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX9-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] +; GFX9-NEXT: v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX9-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] +; GFX9-NEXT: v_mul_f64 v[16:17], v[18:19], v[12:13] +; GFX9-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19] +; GFX9-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3] +; GFX9-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17] +; GFX9-NEXT: s_mov_b64 vcc, s[4:5] +; GFX9-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] +; GFX9-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19] +; GFX9-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21] +; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x double> %a, %b + ret <2 x double> %fdiv +} + +define <2 x double> @v_fdiv_v2f64_afn(<2 x double> %a, <2 x double> %b) { +; GCN-LABEL: v_fdiv_v2f64_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[4:5], v[4:5] +; GCN-NEXT: v_rcp_f64_e32 v[6:7], v[6:7] +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn <2 x double> %a, %b + ret <2 x double> %fdiv +} + +define <2 x double> @v_fdiv_v2f64_ulp25(<2 x double> %a, <2 x double> %b) { +; GFX6-LABEL: v_fdiv_v2f64_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX6-NEXT: v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX6-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1] +; GFX6-NEXT: v_rcp_f64_e32 v[10:11], v[8:9] +; GFX6-NEXT: v_rcp_f64_e32 v[16:17], v[14:15] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v19 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v9 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v15 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 +; GFX6-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; GFX6-NEXT: v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0 +; GFX6-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17] +; GFX6-NEXT: v_mul_f64 v[16:17], v[18:19], v[10:11] +; GFX6-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17] +; GFX6-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13] +; GFX6-NEXT: v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1] +; GFX6-NEXT: v_mul_f64 v[16:17], v[12:13], v[8:9] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v13 +; GFX6-NEXT: v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: s_nop 1 +; GFX6-NEXT: v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17] +; GFX6-NEXT: v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3] +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f64_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX8-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX8-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX8-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX8-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 +; GFX8-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX8-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] +; GFX8-NEXT: v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX8-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] +; GFX8-NEXT: v_mul_f64 v[16:17], v[18:19], v[12:13] +; GFX8-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19] +; GFX8-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3] +; GFX8-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17] +; GFX8-NEXT: s_mov_b64 vcc, s[4:5] +; GFX8-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] +; GFX8-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19] +; GFX8-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21] +; GFX8-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f64_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX9-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX9-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX9-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX9-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 +; GFX9-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX9-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] +; GFX9-NEXT: v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX9-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] +; GFX9-NEXT: v_mul_f64 v[16:17], v[18:19], v[12:13] +; GFX9-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19] +; GFX9-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3] +; GFX9-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17] +; GFX9-NEXT: s_mov_b64 vcc, s[4:5] +; GFX9-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] +; GFX9-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19] +; GFX9-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21] +; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x double> %a, %b, !fpmath !0 + ret <2 x double> %fdiv +} + +define <2 x double> @v_rcp_v2f64(<2 x double> %x) { +; GFX6-LABEL: v_rcp_v2f64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX6-NEXT: v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0 +; GFX6-NEXT: v_mov_b32_e32 v18, 0x3ff00000 +; GFX6-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v18, v11 +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v5 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7] +; GFX6-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX6-NEXT: v_mul_f64 v[14:15], v[10:11], v[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11] +; GFX6-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15] +; GFX6-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX6-NEXT: v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v9 +; GFX6-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v18, v17 +; GFX6-NEXT: v_mul_f64 v[12:13], v[16:17], v[4:5] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13] +; GFX6-NEXT: v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX8-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0 +; GFX8-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0 +; GFX8-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] +; GFX8-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] +; GFX8-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9] +; GFX8-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] +; GFX8-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0 +; GFX8-NEXT: v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9] +; GFX8-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11] +; GFX8-NEXT: v_mul_f64 v[14:15], v[12:13], v[8:9] +; GFX8-NEXT: v_mul_f64 v[18:19], v[16:17], v[10:11] +; GFX8-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13] +; GFX8-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17] +; GFX8-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15] +; GFX8-NEXT: s_mov_b64 vcc, s[4:5] +; GFX8-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 +; GFX8-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX9-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0 +; GFX9-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0 +; GFX9-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] +; GFX9-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] +; GFX9-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9] +; GFX9-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] +; GFX9-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0 +; GFX9-NEXT: v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9] +; GFX9-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11] +; GFX9-NEXT: v_mul_f64 v[14:15], v[12:13], v[8:9] +; GFX9-NEXT: v_mul_f64 v[18:19], v[16:17], v[10:11] +; GFX9-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13] +; GFX9-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17] +; GFX9-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15] +; GFX9-NEXT: s_mov_b64 vcc, s[4:5] +; GFX9-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 +; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x double> , %x + ret <2 x double> %fdiv +} + +define <2 x double> @v_rcp_v2f64_arcp(<2 x double> %x) { +; GFX6-LABEL: v_rcp_v2f64_arcp: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX6-NEXT: v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0 +; GFX6-NEXT: v_mov_b32_e32 v18, 0x3ff00000 +; GFX6-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v18, v11 +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v5 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7] +; GFX6-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX6-NEXT: v_mul_f64 v[14:15], v[10:11], v[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11] +; GFX6-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15] +; GFX6-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX6-NEXT: v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v9 +; GFX6-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v18, v17 +; GFX6-NEXT: v_mul_f64 v[12:13], v[16:17], v[4:5] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13] +; GFX6-NEXT: v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f64_arcp: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX8-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0 +; GFX8-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0 +; GFX8-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] +; GFX8-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] +; GFX8-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9] +; GFX8-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] +; GFX8-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0 +; GFX8-NEXT: v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9] +; GFX8-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11] +; GFX8-NEXT: v_mul_f64 v[14:15], v[12:13], v[8:9] +; GFX8-NEXT: v_mul_f64 v[18:19], v[16:17], v[10:11] +; GFX8-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13] +; GFX8-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17] +; GFX8-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15] +; GFX8-NEXT: s_mov_b64 vcc, s[4:5] +; GFX8-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 +; GFX8-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f64_arcp: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX9-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0 +; GFX9-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0 +; GFX9-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] +; GFX9-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] +; GFX9-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9] +; GFX9-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] +; GFX9-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0 +; GFX9-NEXT: v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9] +; GFX9-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11] +; GFX9-NEXT: v_mul_f64 v[14:15], v[12:13], v[8:9] +; GFX9-NEXT: v_mul_f64 v[18:19], v[16:17], v[10:11] +; GFX9-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13] +; GFX9-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17] +; GFX9-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15] +; GFX9-NEXT: s_mov_b64 vcc, s[4:5] +; GFX9-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 +; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp <2 x double> , %x + ret <2 x double> %fdiv +} + +define <2 x double> @v_rcp_v2f64_arcp_afn(<2 x double> %x) { +; GCN-LABEL: v_rcp_v2f64_arcp_afn: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[0:1], v[0:1] +; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp afn <2 x double> , %x + ret <2 x double> %fdiv +} + +define <2 x double> @v_rcp_v2f64_ulp25(<2 x double> %x) { +; GFX6-LABEL: v_rcp_v2f64_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX6-NEXT: v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0 +; GFX6-NEXT: v_mov_b32_e32 v18, 0x3ff00000 +; GFX6-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v18, v11 +; GFX6-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v5 +; GFX6-NEXT: v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7] +; GFX6-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX6-NEXT: v_mul_f64 v[14:15], v[10:11], v[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11] +; GFX6-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15] +; GFX6-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX6-NEXT: v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0 +; GFX6-NEXT: v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v9 +; GFX6-NEXT: v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v18, v17 +; GFX6-NEXT: v_mul_f64 v[12:13], v[16:17], v[4:5] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13] +; GFX6-NEXT: v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_rcp_v2f64_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX8-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0 +; GFX8-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0 +; GFX8-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] +; GFX8-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] +; GFX8-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9] +; GFX8-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] +; GFX8-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0 +; GFX8-NEXT: v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0 +; GFX8-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9] +; GFX8-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11] +; GFX8-NEXT: v_mul_f64 v[14:15], v[12:13], v[8:9] +; GFX8-NEXT: v_mul_f64 v[18:19], v[16:17], v[10:11] +; GFX8-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13] +; GFX8-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17] +; GFX8-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15] +; GFX8-NEXT: s_mov_b64 vcc, s[4:5] +; GFX8-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 +; GFX8-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_rcp_v2f64_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0 +; GFX9-NEXT: v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0 +; GFX9-NEXT: v_div_scale_f64 v[16:17], s[4:5], 1.0, v[2:3], 1.0 +; GFX9-NEXT: v_rcp_f64_e32 v[8:9], v[4:5] +; GFX9-NEXT: v_rcp_f64_e32 v[10:11], v[6:7] +; GFX9-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9] +; GFX9-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] +; GFX9-NEXT: v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], -v[4:5], v[8:9], 1.0 +; GFX9-NEXT: v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0 +; GFX9-NEXT: v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9] +; GFX9-NEXT: v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11] +; GFX9-NEXT: v_mul_f64 v[14:15], v[12:13], v[8:9] +; GFX9-NEXT: v_mul_f64 v[18:19], v[16:17], v[10:11] +; GFX9-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13] +; GFX9-NEXT: v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17] +; GFX9-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15] +; GFX9-NEXT: s_mov_b64 vcc, s[4:5] +; GFX9-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[18:19] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[4:5], v[0:1], 1.0 +; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[6:7], v[2:3], 1.0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv <2 x double> , %x, !fpmath !0 + ret <2 x double> %fdiv +} + +define <2 x double> @v_fdiv_v2f64_afn_ulp25(<2 x double> %a, <2 x double> %b) { +; GCN-LABEL: v_fdiv_v2f64_afn_ulp25: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[4:5], v[4:5] +; GCN-NEXT: v_rcp_f64_e32 v[6:7], v[6:7] +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn <2 x double> %a, %b, !fpmath !0 + ret <2 x double> %fdiv +} + +define <2 x double> @v_fdiv_v2f64_arcp_ulp25(<2 x double> %a, <2 x double> %b) { +; GFX6-LABEL: v_fdiv_v2f64_arcp_ulp25: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX6-NEXT: v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX6-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1] +; GFX6-NEXT: v_rcp_f64_e32 v[10:11], v[8:9] +; GFX6-NEXT: v_rcp_f64_e32 v[16:17], v[14:15] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v19 +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v9 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v15 +; GFX6-NEXT: v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 +; GFX6-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; GFX6-NEXT: v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0 +; GFX6-NEXT: v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17] +; GFX6-NEXT: v_mul_f64 v[16:17], v[18:19], v[10:11] +; GFX6-NEXT: v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19] +; GFX6-NEXT: v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0 +; GFX6-NEXT: v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17] +; GFX6-NEXT: v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13] +; GFX6-NEXT: v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3] +; GFX6-NEXT: v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1] +; GFX6-NEXT: v_mul_f64 v[16:17], v[12:13], v[8:9] +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v13 +; GFX6-NEXT: v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: s_nop 1 +; GFX6-NEXT: v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17] +; GFX6-NEXT: v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3] +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_fdiv_v2f64_arcp_ulp25: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX8-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX8-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX8-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX8-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 +; GFX8-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX8-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] +; GFX8-NEXT: v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX8-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX8-NEXT: v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0 +; GFX8-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] +; GFX8-NEXT: v_mul_f64 v[16:17], v[18:19], v[12:13] +; GFX8-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19] +; GFX8-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3] +; GFX8-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17] +; GFX8-NEXT: s_mov_b64 vcc, s[4:5] +; GFX8-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15] +; GFX8-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] +; GFX8-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19] +; GFX8-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21] +; GFX8-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_fdiv_v2f64_arcp_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1] +; GFX9-NEXT: v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3] +; GFX9-NEXT: v_rcp_f64_e32 v[12:13], v[8:9] +; GFX9-NEXT: v_rcp_f64_e32 v[14:15], v[10:11] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX9-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 +; GFX9-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX9-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] +; GFX9-NEXT: v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0 +; GFX9-NEXT: v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] +; GFX9-NEXT: v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0 +; GFX9-NEXT: v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] +; GFX9-NEXT: v_mul_f64 v[16:17], v[18:19], v[12:13] +; GFX9-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19] +; GFX9-NEXT: v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3] +; GFX9-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17] +; GFX9-NEXT: s_mov_b64 vcc, s[4:5] +; GFX9-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15] +; GFX9-NEXT: v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1] +; GFX9-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19] +; GFX9-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21] +; GFX9-NEXT: v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv arcp <2 x double> %a, %b, !fpmath !0 + ret <2 x double> %fdiv +} + +define <2 x double> @v_fdiv_v2f64_arcp_afn_ulp25(<2 x double> %a, <2 x double> %b) { +; GCN-LABEL: v_fdiv_v2f64_arcp_afn_ulp25: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_rcp_f64_e32 v[4:5], v[4:5] +; GCN-NEXT: v_rcp_f64_e32 v[6:7], v[6:7] +; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GCN-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7] +; GCN-NEXT: s_setpc_b64 s[30:31] + %fdiv = fdiv afn arcp <2 x double> %a, %b, !fpmath !0 + ret <2 x double> %fdiv +} + +!0 = !{float 2.500000e+00}