diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index c094163c2f9d77..22ef0829a7ef65 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -10,7 +10,6 @@ #include "MCTargetDesc/RISCVMCExpr.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "MCTargetDesc/RISCVTargetStreamer.h" -#include "RISCVInstrInfo.h" #include "TargetInfo/RISCVTargetInfo.h" #include "Utils/RISCVBaseInfo.h" #include "Utils/RISCVMatInt.h" @@ -20,7 +19,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringSwitch.h" -#include "llvm/CodeGen/Register.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" @@ -99,7 +97,7 @@ class RISCVAsmParser : public MCTargetAsmParser { // Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that // synthesize the desired immedate value into the destination register. - void emitLoadImm(Register DestReg, int64_t Value, MCStreamer &Out); + void emitLoadImm(MCRegister DestReg, int64_t Value, MCStreamer &Out); // Helper to emit a combination of AUIPC and SecondOpcode. Used to implement // helpers such as emitLoadLocalAddress and emitLoadAddress. @@ -262,7 +260,7 @@ struct RISCVOperand : public MCParsedAsmOperand { bool IsRV64; struct RegOp { - Register RegNum; + MCRegister RegNum; }; struct ImmOp { @@ -984,7 +982,7 @@ struct RISCVOperand : public MCParsedAsmOperand { #define GET_MNEMONIC_SPELL_CHECKER #include "RISCVGenAsmMatcher.inc" -static Register convertFPR64ToFPR32(Register Reg) { +static MCRegister convertFPR64ToFPR32(MCRegister Reg) { assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); return Reg - RISCV::F0_D + RISCV::F0_F; } @@ -995,7 +993,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, if (!Op.isReg()) return Match_InvalidOperand; - Register Reg = Op.getReg(); + MCRegister Reg = Op.getReg(); bool IsRegFPR64 = RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); bool IsRegFPR64C = @@ -1236,7 +1234,7 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // alternative ABI names), setting RegNo to the matching register. Upon // failure, returns true and sets RegNo to 0. If IsRV32E then registers // x16-x31 will be rejected. -static bool matchRegisterNameHelper(bool IsRV32E, Register &RegNo, +static bool matchRegisterNameHelper(bool IsRV32E, MCRegister &RegNo, StringRef Name) { RegNo = MatchRegisterName(Name); // The 32- and 64-bit FPRs have the same asm name. Check that the initial @@ -1267,7 +1265,7 @@ OperandMatchResultTy RISCVAsmParser::tryParseRegister(unsigned &RegNo, RegNo = 0; StringRef Name = getLexer().getTok().getIdentifier(); - if (matchRegisterNameHelper(isRV32E(), (Register &)RegNo, Name)) + if (matchRegisterNameHelper(isRV32E(), (MCRegister &)RegNo, Name)) return MatchOperand_NoMatch; getParser().Lex(); // Eat identifier token. @@ -1299,7 +1297,7 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands, return MatchOperand_NoMatch; case AsmToken::Identifier: StringRef Name = getLexer().getTok().getIdentifier(); - Register RegNo; + MCRegister RegNo; matchRegisterNameHelper(isRV32E(), RegNo, Name); if (RegNo == RISCV::NoRegister) { @@ -1659,7 +1657,7 @@ OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) { Error(getLoc(), "expected '.t' suffix"); return MatchOperand_ParseFail; } - Register RegNo; + MCRegister RegNo; matchRegisterNameHelper(isRV32E(), RegNo, Name); if (RegNo == RISCV::NoRegister) @@ -2181,12 +2179,12 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { S.emitInstruction((Res ? CInst : Inst), getSTI()); } -void RISCVAsmParser::emitLoadImm(Register DestReg, int64_t Value, +void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value, MCStreamer &Out) { RISCVMatInt::InstSeq Seq; RISCVMatInt::generateInstSeq(Value, isRV64(), Seq); - Register SrcReg = RISCV::X0; + MCRegister SrcReg = RISCV::X0; for (RISCVMatInt::Inst &Inst : Seq) { if (Inst.Opc == RISCV::LUI) { emitToStreamer( @@ -2339,27 +2337,27 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, OperandVector &Operands) { const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); unsigned TargetFlags = - (MCID.TSFlags >> RISCV::ConstraintOffset) & RISCV::ConstraintMask; - if (TargetFlags == RISCV::NoConstraint) + (MCID.TSFlags >> RISCVII::ConstraintOffset) & RISCVII::ConstraintMask; + if (TargetFlags == RISCVII::NoConstraint) return false; unsigned DestReg = Inst.getOperand(0).getReg(); unsigned CheckReg; // Operands[1] will be the first operand, DestReg. SMLoc Loc = Operands[1]->getStartLoc(); - if (TargetFlags & RISCV::VS2Constraint) { + if (TargetFlags & RISCVII::VS2Constraint) { CheckReg = Inst.getOperand(1).getReg(); if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" " the source vector register group."); } - if ((TargetFlags & RISCV::VS1Constraint) && (Inst.getOperand(2).isReg())) { + if ((TargetFlags & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) { CheckReg = Inst.getOperand(2).getReg(); if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" " the source vector register group."); } - if ((TargetFlags & RISCV::VMConstraint) && (DestReg == RISCV::V0)) { + if ((TargetFlags & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { // vadc, vsbc are special cases. These instructions have no mask register. // The destination register could not be V0. unsigned Opcode = Inst.getOpcode(); @@ -2372,7 +2370,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister" // actually. We need to check the last operand to ensure whether it is // masked or not. - if ((TargetFlags & RISCV::OneInput) && (Inst.getNumOperands() == 3)) + if ((TargetFlags & RISCVII::OneInput) && (Inst.getNumOperands() == 3)) CheckReg = Inst.getOperand(2).getReg(); else if (Inst.getNumOperands() == 4) CheckReg = Inst.getOperand(3).getReg(); @@ -2392,7 +2390,7 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, default: break; case RISCV::PseudoLI: { - Register Reg = Inst.getOperand(0).getReg(); + MCRegister Reg = Inst.getOperand(0).getReg(); const MCOperand &Op1 = Inst.getOperand(1); if (Op1.isExpr()) { // We must have li reg, %lo(sym) or li reg, %pcrel_lo(sym) or similar. diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 37edc19398a551..d26add046be110 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -13,7 +13,6 @@ #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "TargetInfo/RISCVTargetInfo.h" #include "Utils/RISCVBaseInfo.h" -#include "llvm/CodeGen/Register.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" @@ -71,7 +70,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) return MCDisassembler::Fail; - Register Reg = RISCV::X0 + RegNo; + MCRegister Reg = RISCV::X0 + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -82,7 +81,7 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 32) return MCDisassembler::Fail; - Register Reg = RISCV::F0_F + RegNo; + MCRegister Reg = RISCV::F0_F + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -93,7 +92,7 @@ static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 8) { return MCDisassembler::Fail; } - Register Reg = RISCV::F8_F + RegNo; + MCRegister Reg = RISCV::F8_F + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -104,7 +103,7 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 32) return MCDisassembler::Fail; - Register Reg = RISCV::F0_D + RegNo; + MCRegister Reg = RISCV::F0_D + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -115,7 +114,7 @@ static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 8) { return MCDisassembler::Fail; } - Register Reg = RISCV::F8_D + RegNo; + MCRegister Reg = RISCV::F8_D + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -146,7 +145,7 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 8) return MCDisassembler::Fail; - Register Reg = RISCV::X8 + RegNo; + MCRegister Reg = RISCV::X8 + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -157,14 +156,14 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, if (RegNo >= 32) return MCDisassembler::Fail; - Register Reg = RISCV::V0 + RegNo; + MCRegister Reg = RISCV::V0 + RegNo; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - Register Reg = RISCV::NoRegister; + MCRegister Reg = RISCV::NoRegister; switch (RegNo) { default: return MCDisassembler::Fail; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 8e0698966d05f6..ddbf85e9ab32c0 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -15,7 +15,6 @@ #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "Utils/RISCVBaseInfo.h" #include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/Register.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" @@ -116,7 +115,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS, const MCSubtargetInfo &STI) const { MCInst TmpInst; MCOperand Func; - Register Ra; + MCRegister Ra; if (MI.getOpcode() == RISCV::PseudoTAIL) { Func = MI.getOperand(0); Ra = RISCV::X6; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp index 2a6f372e50bee2..8ce2184c7a411e 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp @@ -13,7 +13,6 @@ #include "RISCVMCExpr.h" #include "MCTargetDesc/RISCVAsmBackend.h" -#include "RISCV.h" #include "RISCVFixupKinds.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmLayout.h" diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp index e97dafd05aeed1..05cf99bd503abb 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -18,7 +18,6 @@ #include "TargetInfo/RISCVTargetInfo.h" #include "Utils/RISCVBaseInfo.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/CodeGen/Register.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" @@ -56,7 +55,7 @@ static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const MCTargetOptions &Options) { MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); - Register SP = MRI.getDwarfRegNum(RISCV::X2, true); + MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); MAI->addInitialFrameState(Inst); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 54a2fb2885797f..5683214c13fd1a 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "RISCVTargetStreamer.h" -#include "RISCVSubtarget.h" +#include "RISCVMCTargetDesc.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/RISCVAttributes.h" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 180a3e88bc8f06..0b034210aa5524 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -137,62 +137,5 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { const RISCVSubtarget &STI; }; -namespace RISCV { -// Match with the definitions in RISCVInstrFormatsV.td -enum RVVConstraintType { - NoConstraint = 0, - VS2Constraint = 0b0001, - VS1Constraint = 0b0010, - VMConstraint = 0b0100, - OneInput = 0b1000, - - // Illegal instructions: - // - // * The destination vector register group for a masked vector instruction - // cannot overlap the source mask register (v0), unless the destination vector - // register is being written with a mask value (e.g., comparisons) or the - // scalar result of a reduction. - // - // * Widening: The destination vector register group cannot overlap a source - // vector register group of a different EEW - // - // * Narrowing: The destination vector register group cannot overlap the - // first source vector register group - // - // * For vadc and vsbc, an illegal instruction exception is raised if the - // destination vector register is v0. - // - // * For vmadc and vmsbc, an illegal instruction exception is raised if the - // destination vector register overlaps a source vector register group. - // - // * viota: An illegal instruction exception is raised if the destination - // vector register group overlaps the source vector mask register. If the - // instruction is masked, an illegal instruction exception is issued if the - // destination vector register group overlaps v0. - // - // * v[f]slide[1]up: The destination vector register group for vslideup cannot - // overlap the source vector register group. - // - // * vrgather: The destination vector register group cannot overlap with the - // source vector register groups. - // - // * vcompress: The destination vector register group cannot overlap the - // source vector register group or the source mask register - WidenV = VS2Constraint | VS1Constraint | VMConstraint, - WidenW = VS1Constraint | VMConstraint, - WidenCvt = VS2Constraint | VMConstraint | OneInput, - Narrow = VS2Constraint | VMConstraint, - NarrowCvt = VS2Constraint | VMConstraint | OneInput, - Vmadc = VS2Constraint | VS1Constraint, - Iota = VS2Constraint | VMConstraint | OneInput, - SlideUp = VS2Constraint | VMConstraint, - Vrgather = VS2Constraint | VS1Constraint | VMConstraint, - Vcompress = VS2Constraint | VS1Constraint, - - ConstraintOffset = 5, - ConstraintMask = 0b1111 -}; -} // end namespace RISCV - } // end namespace llvm #endif diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h index 0f30397fd30aed..0affca31880fef 100644 --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -45,6 +45,61 @@ enum { InstFormatOther = 17, InstFormatMask = 31, + + ConstraintOffset = 5, + ConstraintMask = 0b1111 +}; + +// Match with the definitions in RISCVInstrFormatsV.td +enum RVVConstraintType { + NoConstraint = 0, + VS2Constraint = 0b0001, + VS1Constraint = 0b0010, + VMConstraint = 0b0100, + OneInput = 0b1000, + + // Illegal instructions: + // + // * The destination vector register group for a masked vector instruction + // cannot overlap the source mask register (v0), unless the destination vector + // register is being written with a mask value (e.g., comparisons) or the + // scalar result of a reduction. + // + // * Widening: The destination vector register group cannot overlap a source + // vector register group of a different EEW + // + // * Narrowing: The destination vector register group cannot overlap the + // first source vector register group + // + // * For vadc and vsbc, an illegal instruction exception is raised if the + // destination vector register is v0. + // + // * For vmadc and vmsbc, an illegal instruction exception is raised if the + // destination vector register overlaps a source vector register group. + // + // * viota: An illegal instruction exception is raised if the destination + // vector register group overlaps the source vector mask register. If the + // instruction is masked, an illegal instruction exception is issued if the + // destination vector register group overlaps v0. + // + // * v[f]slide[1]up: The destination vector register group for vslideup cannot + // overlap the source vector register group. + // + // * vrgather: The destination vector register group cannot overlap with the + // source vector register groups. + // + // * vcompress: The destination vector register group cannot overlap the + // source vector register group or the source mask register + WidenV = VS2Constraint | VS1Constraint | VMConstraint, + WidenW = VS1Constraint | VMConstraint, + WidenCvt = VS2Constraint | VMConstraint | OneInput, + Narrow = VS2Constraint | VMConstraint, + NarrowCvt = VS2Constraint | VMConstraint | OneInput, + Vmadc = VS2Constraint | VS1Constraint, + Iota = VS2Constraint | VMConstraint | OneInput, + SlideUp = VS2Constraint | VMConstraint, + Vrgather = VS2Constraint | VS1Constraint | VMConstraint, + Vcompress = VS2Constraint | VS1Constraint, }; // RISC-V Specific Machine Operand Flags