From 0cbd5d3ded6c1d6c5a0f9a874f755b09e7a238b7 Mon Sep 17 00:00:00 2001
From: "chenglin.bi" <chenglin.bi@cixcomputing.com>
Date: Mon, 6 Jun 2022 09:59:41 +0800
Subject: [PATCH] [InstCombine] Add more tests for shl+lshr transforms; NFC

---
 llvm/test/Transforms/InstCombine/and.ll | 30 +++++++++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 2617ac1eb6def..b9cad04d73ea6 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -1622,8 +1622,8 @@ define i8 @not_lshr_bitwidth_mask(i8 %x, i8 %y) {
   ret i8 %r
 }
 
-define i16 @shl_lshr_pow2_const(i16 %x) {
-; CHECK-LABEL: @shl_lshr_pow2_const(
+define i16 @shl_lshr_pow2_const_case1(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case1(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i16 4, [[X:%.*]]
 ; CHECK-NEXT:    [[LSHR:%.*]] = lshr i16 [[SHL]], 6
 ; CHECK-NEXT:    [[R:%.*]] = and i16 [[LSHR]], 8
@@ -1635,6 +1635,32 @@ define i16 @shl_lshr_pow2_const(i16 %x) {
   ret i16 %r
 }
 
+define i16 @shl_lshr_pow2_const_case2(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case2(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i16 4, [[X:%.*]]
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i16 [[SHL]], 6
+; CHECK-NEXT:    [[R:%.*]] = or i16 [[LSHR]], -9
+; CHECK-NEXT:    ret i16 [[R]]
+;
+  %shl = shl i16 4, %x
+  %lshr = lshr i16 %shl, 6
+  %r = or i16 %lshr, 65527 ; ~8
+  ret i16 %r
+}
+
+define i13 @shl_lshr_pow2_const_case3(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case3(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i16 4, [[X:%.*]]
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i16 [[SHL]], 6
+; CHECK-NEXT:    [[R:%.*]] = trunc i16 [[LSHR]] to i13
+; CHECK-NEXT:    ret i13 [[R]]
+;
+  %shl = shl i16 4, %x
+  %lshr = lshr i16 %shl, 6
+  %r = trunc i16 %lshr to i13
+  ret i13 %r
+}
+
 define i16 @shl_lshr_pow2_const_negative_oneuse(i16 %x) {
 ; CHECK-LABEL: @shl_lshr_pow2_const_negative_oneuse(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i16 4, [[X:%.*]]