diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index a8ce01f703f33..bd3662c942de8 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -91,13 +91,6 @@ class RISCVInstructionSelector : public InstructionSelector {
   void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
                  int OpIdx) const;
 
-  /// Sets CC, LHS, and RHS so that they form an equivelent G_ICMP (ICMPCC, LHS,
-  /// RHS) to that of MI, but whose condition code matches one of the
-  /// comparisons supported directly by branches in the RISC-V ISA.
-  void getICMPOperandsForBranch(MachineInstr &MI, MachineIRBuilder &MIB,
-                                MachineRegisterInfo &MRI, RISCVCC::CondCode &CC,
-                                Register &LHS, Register &RHS) const;
-
   void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
                            int OpIdx) const;
 
@@ -594,9 +587,10 @@ static RISCVCC::CondCode getRISCVCCFromICMP(CmpInst::Predicate CC) {
   }
 }
 
-void RISCVInstructionSelector::getICMPOperandsForBranch(
-    MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI,
-    RISCVCC::CondCode &CC, Register &LHS, Register &RHS) const {
+static void getICMPOperandsForBranch(MachineInstr &MI, MachineIRBuilder &MIB,
+                                     MachineRegisterInfo &MRI,
+                                     RISCVCC::CondCode &CC, Register &LHS,
+                                     Register &RHS) {
   assert(MI.getOpcode() == TargetOpcode::G_ICMP);
   CmpInst::Predicate ICMPCC =
       static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
@@ -609,21 +603,17 @@ void RISCVInstructionSelector::getICMPOperandsForBranch(
     case CmpInst::Predicate::ICMP_SGT:
       // Convert X > -1 to X >= 0
       if (*Constant == -1) {
-        MachineInstr *Zero = MIB.buildConstant(MRI.getType(RHS), 0);
-        selectConstant(*Zero, MIB, MRI);
         CC = RISCVCC::COND_GE;
-        RHS = Zero->getOperand(0).getReg();
+        RHS = RISCV::X0;
         return;
       }
       break;
     case CmpInst::Predicate::ICMP_SLT:
       // Convert X < 1 to 0 >= X
       if (*Constant == 1) {
-        MachineInstr *Zero = MIB.buildConstant(MRI.getType(RHS), 0);
-        selectConstant(*Zero, MIB, MRI);
         CC = RISCVCC::COND_GE;
         RHS = LHS;
-        LHS = Zero->getOperand(0).getReg();
+        LHS = RISCV::X0;
         return;
       }
       break;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
index b9bd9b980e2e4..552a270b54a79 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir
@@ -128,8 +128,7 @@ body:            |
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
-    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 3, [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], $x0, 3, [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s32) = COPY $x10
@@ -159,8 +158,7 @@ body:            |
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
-    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 3, [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR $x0, [[COPY2]], 3, [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir
index 6eee273d320be..16342a83d2275 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir
@@ -128,8 +128,7 @@ body:            |
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
-    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 3, [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], $x0, 3, [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s64) = COPY $x10
@@ -159,8 +158,7 @@ body:            |
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
-    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 3, [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR $x0, [[COPY2]], 3, [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s64) = COPY $x10